From nobody Fri Nov 14 23:29:48 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1759893799; cv=none; d=zohomail.com; s=zohoarc; b=jM5wOVI51GuG+V9ZRawdN3LCQ9INZezfRUp9U4e4eUtbZHKnRTCm1fy+/Z7Xs8CWp0YJiUoQVHsSO0nzhoBD/4BNEyzqsL+IbKpcyadCdhkcMZBUrlb0WUF7jktYv7C3sZn0FlXkIrXUn0wtcWPZSIEKlu1JXPGzMiTMIlstkYk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1759893799; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=awomYRFw+VnYrRXQl7BJr79ygJLhCHEqAtF5NcFhsag=; b=QkBNAKNyWZh3NBeNBDQnQeBPlPY+t1lt0qxK7t6RyWMMtr1wOgJt0nq4g8sD1UU9wEi0KlQE3gXCeXqA9zFFkbNwwLNRWboMrv9bgwm2vov3XzSDT8ErqQKwglM8JhboAswEnvzqnjk/larMida+R5ppxFnv6V3A/s6V2JYUAIM= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1759893798947274.8553824006465; Tue, 7 Oct 2025 20:23:18 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v6Kli-0002DN-UT; Tue, 07 Oct 2025 23:23:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v6Kle-00025Q-On; Tue, 07 Oct 2025 23:23:08 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v6KlX-0000bG-VC; Tue, 07 Oct 2025 23:23:05 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 8 Oct 2025 11:22:13 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 8 Oct 2025 11:22:13 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , Subject: [PATCH v1 13/16] hw/arm/aspeed_ast27x0-tsp: Change to use Aspeed27x0CoprocessorState Date: Wed, 8 Oct 2025 11:21:58 +0800 Message-ID: <20251008032207.593353-14-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251008032207.593353-1-jamin_lin@aspeedtech.com> References: <20251008032207.593353-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, KHOP_HELO_FCRDNS=0.398, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, T_SPF_TEMPERROR=0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1759893805355116600 Content-Type: text/plain; charset="utf-8" Refactor the AST27x0 TSP implementation to use the unified Aspeed27x0CoprocessorState, matching the prior SSP change and removing the duplicated Aspeed27x0TSPSoCState. Key updates: - Delete Aspeed27x0TSPSoCState and reuse Aspeed27x0CoprocessorState. Update Ast2700FCState to declare tsp as Aspeed27x0CoprocessorState. This aligns TSP with SSP on a single coprocessor state type, reducing code duplication and simplifying maintenance. No functional change. Signed-off-by: Jamin Lin --- include/hw/arm/aspeed_coprocessor.h | 12 ++---------- hw/arm/aspeed_ast27x0-fc.c | 2 +- hw/arm/aspeed_ast27x0-tsp.c | 8 ++++---- 3 files changed, 7 insertions(+), 15 deletions(-) diff --git a/include/hw/arm/aspeed_coprocessor.h b/include/hw/arm/aspeed_co= processor.h index 89e46100a5..51c0e195f9 100644 --- a/include/hw/arm/aspeed_coprocessor.h +++ b/include/hw/arm/aspeed_coprocessor.h @@ -54,16 +54,8 @@ struct Aspeed27x0CoprocessorState { #define TYPE_ASPEED27X0SSP_SOC "aspeed27x0ssp-soc" OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0CoprocessorState, ASPEED27X0SSP_SOC) =20 -struct Aspeed27x0TSPSoCState { - AspeedCoprocessorState parent; - AspeedINTCState intc[2]; - UnimplementedDeviceState ipc[2]; - UnimplementedDeviceState scuio; - - ARMv7MState armv7m; -}; - #define TYPE_ASPEED27X0TSP_SOC "aspeed27x0tsp-soc" -OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0TSPSoCState, ASPEED27X0TSP_SOC) +DECLARE_OBJ_CHECKERS(Aspeed27x0CoprocessorState, AspeedCoprocessorClass, + ASPEED27X0TSP_SOC, TYPE_ASPEED27X0TSP_SOC) =20 #endif /* ASPEED_COPROCESSOR_H */ diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c index cd09a2dcf0..c2fa8df33c 100644 --- a/hw/arm/aspeed_ast27x0-fc.c +++ b/hw/arm/aspeed_ast27x0-fc.c @@ -43,7 +43,7 @@ struct Ast2700FCState { =20 Aspeed27x0SoCState ca35; Aspeed27x0CoprocessorState ssp; - Aspeed27x0TSPSoCState tsp; + Aspeed27x0CoprocessorState tsp; =20 bool mmio_exec; }; diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c index 8b13ab526d..c00f7d056c 100644 --- a/hw/arm/aspeed_ast27x0-tsp.c +++ b/hw/arm/aspeed_ast27x0-tsp.c @@ -108,7 +108,7 @@ static struct nvic_intc_irq_info ast2700_tsp_intcmap[] = =3D { static qemu_irq aspeed_soc_ast27x0tsp_get_irq(void *ctx, int dev) { AspeedCoprocessorState *s =3D (AspeedCoprocessorState *)ctx; - Aspeed27x0TSPSoCState *a =3D ASPEED27X0TSP_SOC(s); + Aspeed27x0CoprocessorState *a =3D ASPEED27X0TSP_SOC(s); AspeedCoprocessorClass *sc =3D ASPEED_COPROCESSOR_GET_CLASS(s); =20 int or_idx; @@ -130,7 +130,7 @@ static qemu_irq aspeed_soc_ast27x0tsp_get_irq(void *ctx= , int dev) =20 static void aspeed_soc_ast27x0tsp_init(Object *obj) { - Aspeed27x0TSPSoCState *a =3D ASPEED27X0TSP_SOC(obj); + Aspeed27x0CoprocessorState *a =3D ASPEED27X0TSP_SOC(obj); AspeedCoprocessorState *s =3D ASPEED_COPROCESSOR(obj); AspeedCoprocessorClass *sc =3D ASPEED_COPROCESSOR_GET_CLASS(s); int i; @@ -161,7 +161,7 @@ static void aspeed_soc_ast27x0tsp_init(Object *obj) =20 static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **er= rp) { - Aspeed27x0TSPSoCState *a =3D ASPEED27X0TSP_SOC(dev_soc); + Aspeed27x0CoprocessorState *a =3D ASPEED27X0TSP_SOC(dev_soc); AspeedCoprocessorState *s =3D ASPEED_COPROCESSOR(dev_soc); AspeedCoprocessorClass *sc =3D ASPEED_COPROCESSOR_GET_CLASS(s); DeviceState *armv7m; @@ -289,7 +289,7 @@ static const TypeInfo aspeed_soc_ast27x0tsp_types[] =3D= { { .name =3D TYPE_ASPEED27X0TSP_SOC, .parent =3D TYPE_ASPEED_COPROCESSOR, - .instance_size =3D sizeof(Aspeed27x0TSPSoCState), + .instance_size =3D sizeof(Aspeed27x0CoprocessorState), .instance_init =3D aspeed_soc_ast27x0tsp_init, .class_init =3D aspeed_soc_ast27x0tsp_class_init, }, --=20 2.43.0