From nobody Fri Nov 14 23:29:53 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1759893986; cv=none; d=zohomail.com; s=zohoarc; b=cDTeUojQoreYzm0fH8AcL89eyuN+x8wGvSHNpUxpNNdB/1qQ/WbKYI3BCFPVIG2pHOwa9UFayccucuWfjPAN3EI/2owPyQhG0cJ0DO7lcYoT5rMgN4vh4/DdRY1oPr4jJTN0PHi4X4UY6B8tKb3v+kY5Y/et70buukAYyFzCBBg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1759893986; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=zvDMVHnXFlmj10hXkh+EBm2YQGVlalvME4G47nOH4pU=; b=URfL/RNsZkzMFjk4DVNlP2D7GatmLdC9k88b8HsHR+fKbotZDyfly4+WQ3pq4McwX+N3UZwnQfsL1hq6/9fcvTOMdwmCq1pVR7GpYRrr8HE/1kHjv7BtRYuKI9oE9LWm58HxLKLK9syU7RYkFciTtn2W0/OJgfOII+kmfqOHmm0= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1759893986478162.69681702804803; Tue, 7 Oct 2025 20:26:26 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v6KlO-0001u3-5y; Tue, 07 Oct 2025 23:22:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v6KlN-0001ta-2F; Tue, 07 Oct 2025 23:22:49 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v6KlL-0000T8-6j; Tue, 07 Oct 2025 23:22:48 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 8 Oct 2025 11:22:11 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 8 Oct 2025 11:22:11 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , Subject: [PATCH v1 10/16] hw/arm/aspeed_ast27x0-ssp: Make AST27x0 SSP inherit from AspeedCoprocessor instead of AspeedSoC Date: Wed, 8 Oct 2025 11:21:55 +0800 Message-ID: <20251008032207.593353-11-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251008032207.593353-1-jamin_lin@aspeedtech.com> References: <20251008032207.593353-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1759893993803116600 Content-Type: text/plain; charset="utf-8" Refactor the AST27x0 SSP implementation to derive from the newly introduced AspeedCoprocessor base class rather than AspeedSoC. The AspeedSoC class contains many SoC-level fields and behaviors that are not applicable to coprocessor subsystems like SSP, leading to unnecessary coupling and code s= ize. This change moves the Aspeed27x0SSPSoCState structure definition into aspeed_coprocessor.h and updates related references in aspeed_ast27x0-ssp.c and aspeed_ast27x0-fc.c to use AspeedCoprocessorState and AspeedCoprocessorClass. Key updates include: - Replace inheritance from AspeedSoC -> AspeedCoprocessor. - Replace type casts and class access macros (ASPEED_SOC_*) with ASPEED_COPROCESSOR_*. This refactor improves modularity, reduces memory footprint, and prepares for future coprocessor variants to share a lighter-weight common base. No functional change. Signed-off-by: Jamin Lin --- include/hw/arm/aspeed_coprocessor.h | 12 ++++++++++++ include/hw/arm/aspeed_soc.h | 12 ------------ hw/arm/aspeed_ast27x0-fc.c | 10 +++++----- hw/arm/aspeed_ast27x0-ssp.c | 29 ++++++++++++----------------- 4 files changed, 29 insertions(+), 34 deletions(-) diff --git a/include/hw/arm/aspeed_coprocessor.h b/include/hw/arm/aspeed_co= processor.h index 6938dfe24c..927e8675b0 100644 --- a/include/hw/arm/aspeed_coprocessor.h +++ b/include/hw/arm/aspeed_coprocessor.h @@ -42,4 +42,16 @@ struct AspeedCoprocessorClass { qemu_irq (*get_irq)(void *ctx, int dev); }; =20 +struct Aspeed27x0SSPSoCState { + AspeedCoprocessorState parent; + AspeedINTCState intc[2]; + UnimplementedDeviceState ipc[2]; + UnimplementedDeviceState scuio; + + ARMv7MState armv7m; +}; + +#define TYPE_ASPEED27X0SSP_SOC "aspeed27x0ssp-soc" +OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0SSPSoCState, ASPEED27X0SSP_SOC) + #endif /* ASPEED_COPROCESSOR_H */ diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 3cd9ad189f..b100a404f1 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -153,18 +153,6 @@ struct Aspeed10x0SoCState { ARMv7MState armv7m; }; =20 -struct Aspeed27x0SSPSoCState { - AspeedSoCState parent; - AspeedINTCState intc[2]; - UnimplementedDeviceState ipc[2]; - UnimplementedDeviceState scuio; - - ARMv7MState armv7m; -}; - -#define TYPE_ASPEED27X0SSP_SOC "aspeed27x0ssp-soc" -OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0SSPSoCState, ASPEED27X0SSP_SOC) - struct Aspeed27x0TSPSoCState { AspeedSoCState parent; AspeedINTCState intc[2]; diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c index e598f57ca2..4315e8da98 100644 --- a/hw/arm/aspeed_ast27x0-fc.c +++ b/hw/arm/aspeed_ast27x0-fc.c @@ -21,7 +21,7 @@ #include "hw/loader.h" #include "hw/arm/boot.h" #include "hw/block/flash.h" - +#include "hw/arm/aspeed_coprocessor.h" =20 #define TYPE_AST2700A1FC MACHINE_TYPE_NAME("ast2700fc") OBJECT_DECLARE_SIMPLE_TYPE(Ast2700FCState, AST2700A1FC); @@ -115,8 +115,8 @@ static bool ast2700fc_ca35_init(MachineState *machine, = Error **errp) =20 static bool ast2700fc_ssp_init(MachineState *machine, Error **errp) { - AspeedSoCState *soc; - AspeedSoCClass *sc; + AspeedCoprocessorState *soc; + AspeedCoprocessorClass *sc; Ast2700FCState *s =3D AST2700A1FC(machine); s->ssp_sysclk =3D clock_new(OBJECT(s), "SSP_SYSCLK"); clock_set_hz(s->ssp_sysclk, 200000000ULL); @@ -129,8 +129,8 @@ static bool ast2700fc_ssp_init(MachineState *machine, E= rror **errp) object_property_set_link(OBJECT(&s->ssp), "memory", OBJECT(&s->ssp_memory), &error_abort); =20 - soc =3D ASPEED_SOC(&s->ssp); - sc =3D ASPEED_SOC_GET_CLASS(soc); + soc =3D ASPEED_COPROCESSOR(&s->ssp); + sc =3D ASPEED_COPROCESSOR_GET_CLASS(soc); aspeed_soc_uart_set_chr(soc->uart, ASPEED_DEV_UART4, sc->uarts_base, sc->uarts_num, serial_hd(1)); if (!qdev_realize(DEVICE(&s->ssp), NULL, errp)) { diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c index 57dd588af4..0e68c0f6a8 100644 --- a/hw/arm/aspeed_ast27x0-ssp.c +++ b/hw/arm/aspeed_ast27x0-ssp.c @@ -14,6 +14,7 @@ #include "hw/qdev-clock.h" #include "hw/misc/unimp.h" #include "hw/arm/aspeed_soc.h" +#include "hw/arm/aspeed_coprocessor.h" =20 #define AST2700_SSP_RAM_SIZE (32 * MiB) =20 @@ -106,9 +107,9 @@ static struct nvic_intc_irq_info ast2700_ssp_intcmap[] = =3D { =20 static qemu_irq aspeed_soc_ast27x0ssp_get_irq(void *ctx, int dev) { - AspeedSoCState *s =3D (AspeedSoCState *)ctx; + AspeedCoprocessorState *s =3D (AspeedCoprocessorState *)ctx; Aspeed27x0SSPSoCState *a =3D ASPEED27X0SSP_SOC(s); - AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s); + AspeedCoprocessorClass *sc =3D ASPEED_COPROCESSOR_GET_CLASS(s); =20 int or_idx; int idx; @@ -130,8 +131,8 @@ static qemu_irq aspeed_soc_ast27x0ssp_get_irq(void *ctx= , int dev) static void aspeed_soc_ast27x0ssp_init(Object *obj) { Aspeed27x0SSPSoCState *a =3D ASPEED27X0SSP_SOC(obj); - AspeedSoCState *s =3D ASPEED_SOC(obj); - AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s); + AspeedCoprocessorState *s =3D ASPEED_COPROCESSOR(obj); + AspeedCoprocessorClass *sc =3D ASPEED_COPROCESSOR_GET_CLASS(s); int i; =20 object_initialize_child(obj, "armv7m", &a->armv7m, TYPE_ARMV7M); @@ -161,8 +162,8 @@ static void aspeed_soc_ast27x0ssp_init(Object *obj) static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **er= rp) { Aspeed27x0SSPSoCState *a =3D ASPEED27X0SSP_SOC(dev_soc); - AspeedSoCState *s =3D ASPEED_SOC(dev_soc); - AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s); + AspeedCoprocessorState *s =3D ASPEED_COPROCESSOR(dev_soc); + AspeedCoprocessorClass *sc =3D ASPEED_COPROCESSOR_GET_CLASS(s); DeviceState *armv7m; g_autofree char *sram_name =3D NULL; int uart; @@ -186,8 +187,8 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *= dev_soc, Error **errp) sram_name =3D g_strdup_printf("aspeed.dram.%d", CPU(a->armv7m.cpu)->cpu_index); =20 - if (!memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_s= ize, - errp)) { + if (!memory_region_init_ram(&s->sram, OBJECT(s), sram_name, + AST2700_SSP_RAM_SIZE, errp)) { return; } memory_region_add_subregion(s->memory, @@ -269,31 +270,25 @@ static void aspeed_soc_ast27x0ssp_class_init(ObjectCl= ass *klass, const void *dat NULL }; DeviceClass *dc =3D DEVICE_CLASS(klass); - AspeedSoCClass *sc =3D ASPEED_SOC_CLASS(dc); + AspeedCoprocessorClass *sc =3D ASPEED_COPROCESSOR_CLASS(dc); =20 - /* Reason: The Aspeed SoC can only be instantiated from a board */ + /* Reason: The Aspeed Coprocessor can only be instantiated from a boar= d */ dc->user_creatable =3D false; dc->realize =3D aspeed_soc_ast27x0ssp_realize; =20 sc->valid_cpu_types =3D valid_cpu_types; sc->silicon_rev =3D AST2700_A1_SILICON_REV; - sc->sram_size =3D AST2700_SSP_RAM_SIZE; - sc->spis_num =3D 0; - sc->ehcis_num =3D 0; - sc->wdts_num =3D 0; - sc->macs_num =3D 0; sc->uarts_num =3D 13; sc->uarts_base =3D ASPEED_DEV_UART0; sc->irqmap =3D aspeed_soc_ast27x0ssp_irqmap; sc->memmap =3D aspeed_soc_ast27x0ssp_memmap; - sc->num_cpus =3D 1; sc->get_irq =3D aspeed_soc_ast27x0ssp_get_irq; } =20 static const TypeInfo aspeed_soc_ast27x0ssp_types[] =3D { { .name =3D TYPE_ASPEED27X0SSP_SOC, - .parent =3D TYPE_ASPEED_SOC, + .parent =3D TYPE_ASPEED_COPROCESSOR, .instance_size =3D sizeof(Aspeed27x0SSPSoCState), .instance_init =3D aspeed_soc_ast27x0ssp_init, .class_init =3D aspeed_soc_ast27x0ssp_class_init, --=20 2.43.0