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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-46e78c5d290sm167037135e9.0.2025.10.07.07.12.03 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Oct 2025 07:12:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1759846324; x=1760451124; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=KcUfUVnFehZbBqb4WCtH4FXczD/yYJ2ZxZlXOz2VXG4=; b=tcEn+VG6esQg+2Q0VtcTibMHNYbaMgr/vOPBJEOm2d26fJnOx4pfZpQUmNpX/BuWv9 ru1puJZr2bl3Hsp0iUHd6Bm9RmSS50gGvOybPT8kFllUfNypxcKvu4iVq2rvPXeKY14M Wbe4/jrIdqo4+t+/QtGuyUwFHWRYf4HG1WHGWquNJMHvDSaHOrmWcxZ86/KWyVES1jLZ vj1L4l+BDO44SFeeocKC6MK0GZeRKdnxrw1Vf8Q0dFYThCHJFLdEQgg3fOflNzHJaXD8 Y/9SEL6VHZqU6DeTVUEOepIkx1sepaLAYRLmhIi0FoT/U+O78ne9m2HrO97FhrsUyDWq Ku6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1759846324; x=1760451124; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KcUfUVnFehZbBqb4WCtH4FXczD/yYJ2ZxZlXOz2VXG4=; b=vOrJpSVhr93wxZel69YoRpb5DX6smBDYB8rTaKYozakWw2up+IjXn5XJSLEf7yDMk+ 9V75smJxpaERuKXn29QOG2T+7F+t0VbIvmcyykje5qYKin097hcaBpsrLVGjFP6INXSZ ghsDX4REkYjoVy4lFysz/ZspGAT7DGUcYqPfC61hc6txjftY0oHWlhqgJE4ENI/+unBp itXCE9oqT9m7HhmukjMJ7seEDaF1s4lwCNrXTLLgLILQmZI5e5GRFEkQrqW84P+P10cy MJj7s1Cf+7syHY4Z6DkrM7dC46DhddXpZgc9hWKeuBhnvgZwV9bhTfFwAzJkEDBj1v48 IzHQ== X-Gm-Message-State: AOJu0Yxk7Ai0HMcD1A1eIouHi0R1VXLjGqQ9uqcNRu7Xbf+k7E6gwJII r1H485o8QPzdGsVCn5pi8pEZ+07YEvDZuNjmWE/lHuzGHptm3E+5MTgPy31Ac2/CwnqPB3OfsaZ siEnI X-Gm-Gg: ASbGncuKIrkpuQb9hjmhKgWh0paqX6LauGk09x/M0yzT/abtmwXpwYs27XT/K1W7kCn ygixyqV+KNIPcMdu6zPpDYU0d8M4eS59aoFSSEq/VaV4X4WMQQgBgTiNsD+nxMZE426uV3GKe8P cXR9WgAxhI5Jid3lzWnsQmgJCeptIfO2c8tRllbsMqukRUwWWeBcxtY8gbyCdC+CExUENrAamyw R7Td+awpZ/FOASvThkrA/4Vwu6DnMQD4mqgG2Ab5/biWNelM/FpoWyzbgkI/+97P+6tHap9U/jb ibgI5castV+PaZYpuE3JKUc+C+wdwHKdgv1LeVRRRnNRPdZOc8XvzQLF7ZRIBIWEvZ2ewGfD+PF 9+xz9a9m5s16FzAaY4T30C4XkDxuVceTtwOoPsuprQlZQu1KmWC9IAstr X-Google-Smtp-Source: AGHT+IGoxb6ivevyQjtrhBN+uTGJE2nPsXdR5Kkdl9i8wkfYI/3OD/KaW1m6plc0019xugP+dT++8g== X-Received: by 2002:a05:600c:83cf:b0:46e:4705:4958 with SMTP id 5b1f17b1804b1-46e7114e8a1mr126895075e9.30.1759846323840; Tue, 07 Oct 2025 07:12:03 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 36/62] hw/arm/xlnx-versal: tidy up Date: Tue, 7 Oct 2025 15:10:56 +0100 Message-ID: <20251007141123.3239867-37-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251007141123.3239867-1-peter.maydell@linaro.org> References: <20251007141123.3239867-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1759847625942116600 From: Luc Michel Remove now unused macros in xlnx-versal.[ch]. Those macros have been replaced by the VersalMap structure that serves as a central description for the SoC. The ones still in use in the versal_unimp function are inlined. Signed-off-by: Luc Michel Reviewed-by: Francisco Iglesias Reviewed-by: Edgar E. Iglesias Tested-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20250926070806.292065-36-luc.michel@amd.com Signed-off-by: Peter Maydell --- include/hw/arm/xlnx-versal.h | 204 ----------------------------------- hw/arm/xlnx-versal.c | 28 ++--- 2 files changed, 7 insertions(+), 225 deletions(-) diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h index da0260b83de..b6cc71f7209 100644 --- a/include/hw/arm/xlnx-versal.h +++ b/include/hw/arm/xlnx-versal.h @@ -23,18 +23,6 @@ OBJECT_DECLARE_TYPE(Versal, VersalClass, XLNX_VERSAL_BAS= E) =20 #define TYPE_XLNX_VERSAL "xlnx-versal" =20 -#define XLNX_VERSAL_NR_ACPUS 2 -#define XLNX_VERSAL_NR_RCPUS 2 -#define XLNX_VERSAL_NR_UARTS 2 -#define XLNX_VERSAL_NR_GEMS 2 -#define XLNX_VERSAL_NR_ADMAS 8 -#define XLNX_VERSAL_NR_SDS 2 -#define XLNX_VERSAL_NR_XRAM 4 -#define XLNX_VERSAL_NR_IRQS 192 -#define XLNX_VERSAL_NR_CANFD 2 -#define XLNX_VERSAL_CANFD_REF_CLK (24 * 1000 * 1000) -#define XLNX_VERSAL_NR_CFRAME 15 - struct Versal { /*< private >*/ SysBusDevice parent_obj; @@ -84,196 +72,4 @@ int versal_get_num_cpu(VersalVersion version); int versal_get_num_can(VersalVersion version); int versal_get_num_sdhci(VersalVersion version); =20 -/* Memory-map and IRQ definitions. Copied a subset from - * auto-generated files. */ - -#define VERSAL_CRL_IRQ 10 -#define VERSAL_UART0_IRQ_0 18 -#define VERSAL_UART1_IRQ_0 19 -#define VERSAL_CANFD0_IRQ_0 20 -#define VERSAL_CANFD1_IRQ_0 21 -#define VERSAL_USB0_IRQ_0 22 -#define VERSAL_GEM0_IRQ_0 56 -#define VERSAL_GEM0_WAKE_IRQ_0 57 -#define VERSAL_GEM1_IRQ_0 58 -#define VERSAL_GEM1_WAKE_IRQ_0 59 -#define VERSAL_ADMA_IRQ_0 60 -#define VERSAL_XRAM_IRQ_0 79 -#define VERSAL_CFU_IRQ_0 120 -#define VERSAL_PMC_APB_IRQ 121 -#define VERSAL_OSPI_IRQ 124 -#define VERSAL_SD0_IRQ_0 126 -#define VERSAL_EFUSE_IRQ 139 -#define VERSAL_TRNG_IRQ 141 -#define VERSAL_RTC_ALARM_IRQ 142 -#define VERSAL_RTC_SECONDS_IRQ 143 - -/* Architecturally reserved IRQs suitable for virtualization. */ -#define VERSAL_RSVD_IRQ_FIRST 111 -#define VERSAL_RSVD_IRQ_LAST 118 - -#define MM_TOP_RSVD 0xa0000000U -#define MM_TOP_RSVD_SIZE 0x4000000 -#define MM_GIC_APU_DIST_MAIN 0xf9000000U -#define MM_GIC_APU_DIST_MAIN_SIZE 0x10000 -#define MM_GIC_APU_REDIST_0 0xf9080000U -#define MM_GIC_APU_REDIST_0_SIZE 0x80000 - -#define MM_UART0 0xff000000U -#define MM_UART0_SIZE 0x10000 -#define MM_UART1 0xff010000U -#define MM_UART1_SIZE 0x10000 - -#define MM_CANFD0 0xff060000U -#define MM_CANFD0_SIZE 0x10000 -#define MM_CANFD1 0xff070000U -#define MM_CANFD1_SIZE 0x10000 - -#define MM_GEM0 0xff0c0000U -#define MM_GEM0_SIZE 0x10000 -#define MM_GEM1 0xff0d0000U -#define MM_GEM1_SIZE 0x10000 - -#define MM_ADMA_CH0 0xffa80000U -#define MM_ADMA_CH0_SIZE 0x10000 - -#define MM_OCM 0xfffc0000U -#define MM_OCM_SIZE 0x40000 - -#define MM_XRAM 0xfe800000 -#define MM_XRAMC 0xff8e0000 -#define MM_XRAMC_SIZE 0x10000 - -#define MM_USB2_CTRL_REGS 0xFF9D0000 -#define MM_USB2_CTRL_REGS_SIZE 0x10000 - -#define MM_USB_0 0xFE200000 -#define MM_USB_0_SIZE 0x10000 - -#define MM_TOP_DDR 0x0 -#define MM_TOP_DDR_SIZE 0x80000000U -#define MM_TOP_DDR_2 0x800000000ULL -#define MM_TOP_DDR_2_SIZE 0x800000000ULL -#define MM_TOP_DDR_3 0xc000000000ULL -#define MM_TOP_DDR_3_SIZE 0x4000000000ULL -#define MM_TOP_DDR_4 0x10000000000ULL -#define MM_TOP_DDR_4_SIZE 0xb780000000ULL - -#define MM_PSM_START 0xffc80000U -#define MM_PSM_END 0xffcf0000U - -#define MM_CRL 0xff5e0000U -#define MM_CRL_SIZE 0x300000 -#define MM_IOU_SCNTR 0xff130000U -#define MM_IOU_SCNTR_SIZE 0x10000 -#define MM_IOU_SCNTRS 0xff140000U -#define MM_IOU_SCNTRS_SIZE 0x10000 -#define MM_FPD_CRF 0xfd1a0000U -#define MM_FPD_CRF_SIZE 0x140000 -#define MM_FPD_FPD_APU 0xfd5c0000 -#define MM_FPD_FPD_APU_SIZE 0x100 - -#define MM_PMC_PMC_IOU_SLCR 0xf1060000 -#define MM_PMC_PMC_IOU_SLCR_SIZE 0x10000 - -#define MM_PMC_OSPI 0xf1010000 -#define MM_PMC_OSPI_SIZE 0x10000 - -#define MM_PMC_OSPI_DAC 0xc0000000 -#define MM_PMC_OSPI_DAC_SIZE 0x20000000 - -#define MM_PMC_OSPI_DMA_DST 0xf1011800 -#define MM_PMC_OSPI_DMA_SRC 0xf1011000 - -#define MM_PMC_SD0 0xf1040000U -#define MM_PMC_SD0_SIZE 0x10000 -#define MM_PMC_BBRAM_CTRL 0xf11f0000 -#define MM_PMC_BBRAM_CTRL_SIZE 0x00050 -#define MM_PMC_EFUSE_CTRL 0xf1240000 -#define MM_PMC_EFUSE_CTRL_SIZE 0x00104 -#define MM_PMC_EFUSE_CACHE 0xf1250000 -#define MM_PMC_EFUSE_CACHE_SIZE 0x00C00 - -#define MM_PMC_CFU_APB 0xf12b0000 -#define MM_PMC_CFU_APB_SIZE 0x10000 -#define MM_PMC_CFU_STREAM 0xf12c0000 -#define MM_PMC_CFU_STREAM_SIZE 0x1000 -#define MM_PMC_CFU_SFR 0xf12c1000 -#define MM_PMC_CFU_SFR_SIZE 0x1000 -#define MM_PMC_CFU_FDRO 0xf12c2000 -#define MM_PMC_CFU_FDRO_SIZE 0x1000 -#define MM_PMC_CFU_STREAM_2 0xf1f80000 -#define MM_PMC_CFU_STREAM_2_SIZE 0x40000 - -#define MM_PMC_CFRAME0_REG 0xf12d0000 -#define MM_PMC_CFRAME0_REG_SIZE 0x1000 -#define MM_PMC_CFRAME0_FDRI 0xf12d1000 -#define MM_PMC_CFRAME0_FDRI_SIZE 0x1000 -#define MM_PMC_CFRAME1_REG 0xf12d2000 -#define MM_PMC_CFRAME1_REG_SIZE 0x1000 -#define MM_PMC_CFRAME1_FDRI 0xf12d3000 -#define MM_PMC_CFRAME1_FDRI_SIZE 0x1000 -#define MM_PMC_CFRAME2_REG 0xf12d4000 -#define MM_PMC_CFRAME2_REG_SIZE 0x1000 -#define MM_PMC_CFRAME2_FDRI 0xf12d5000 -#define MM_PMC_CFRAME2_FDRI_SIZE 0x1000 -#define MM_PMC_CFRAME3_REG 0xf12d6000 -#define MM_PMC_CFRAME3_REG_SIZE 0x1000 -#define MM_PMC_CFRAME3_FDRI 0xf12d7000 -#define MM_PMC_CFRAME3_FDRI_SIZE 0x1000 -#define MM_PMC_CFRAME4_REG 0xf12d8000 -#define MM_PMC_CFRAME4_REG_SIZE 0x1000 -#define MM_PMC_CFRAME4_FDRI 0xf12d9000 -#define MM_PMC_CFRAME4_FDRI_SIZE 0x1000 -#define MM_PMC_CFRAME5_REG 0xf12da000 -#define MM_PMC_CFRAME5_REG_SIZE 0x1000 -#define MM_PMC_CFRAME5_FDRI 0xf12db000 -#define MM_PMC_CFRAME5_FDRI_SIZE 0x1000 -#define MM_PMC_CFRAME6_REG 0xf12dc000 -#define MM_PMC_CFRAME6_REG_SIZE 0x1000 -#define MM_PMC_CFRAME6_FDRI 0xf12dd000 -#define MM_PMC_CFRAME6_FDRI_SIZE 0x1000 -#define MM_PMC_CFRAME7_REG 0xf12de000 -#define MM_PMC_CFRAME7_REG_SIZE 0x1000 -#define MM_PMC_CFRAME7_FDRI 0xf12df000 -#define MM_PMC_CFRAME7_FDRI_SIZE 0x1000 -#define MM_PMC_CFRAME8_REG 0xf12e0000 -#define MM_PMC_CFRAME8_REG_SIZE 0x1000 -#define MM_PMC_CFRAME8_FDRI 0xf12e1000 -#define MM_PMC_CFRAME8_FDRI_SIZE 0x1000 -#define MM_PMC_CFRAME9_REG 0xf12e2000 -#define MM_PMC_CFRAME9_REG_SIZE 0x1000 -#define MM_PMC_CFRAME9_FDRI 0xf12e3000 -#define MM_PMC_CFRAME9_FDRI_SIZE 0x1000 -#define MM_PMC_CFRAME10_REG 0xf12e4000 -#define MM_PMC_CFRAME10_REG_SIZE 0x1000 -#define MM_PMC_CFRAME10_FDRI 0xf12e5000 -#define MM_PMC_CFRAME10_FDRI_SIZE 0x1000 -#define MM_PMC_CFRAME11_REG 0xf12e6000 -#define MM_PMC_CFRAME11_REG_SIZE 0x1000 -#define MM_PMC_CFRAME11_FDRI 0xf12e7000 -#define MM_PMC_CFRAME11_FDRI_SIZE 0x1000 -#define MM_PMC_CFRAME12_REG 0xf12e8000 -#define MM_PMC_CFRAME12_REG_SIZE 0x1000 -#define MM_PMC_CFRAME12_FDRI 0xf12e9000 -#define MM_PMC_CFRAME12_FDRI_SIZE 0x1000 -#define MM_PMC_CFRAME13_REG 0xf12ea000 -#define MM_PMC_CFRAME13_REG_SIZE 0x1000 -#define MM_PMC_CFRAME13_FDRI 0xf12eb000 -#define MM_PMC_CFRAME13_FDRI_SIZE 0x1000 -#define MM_PMC_CFRAME14_REG 0xf12ec000 -#define MM_PMC_CFRAME14_REG_SIZE 0x1000 -#define MM_PMC_CFRAME14_FDRI 0xf12ed000 -#define MM_PMC_CFRAME14_FDRI_SIZE 0x1000 -#define MM_PMC_CFRAME_BCAST_REG 0xf12ee000 -#define MM_PMC_CFRAME_BCAST_REG_SIZE 0x1000 -#define MM_PMC_CFRAME_BCAST_FDRI 0xf12ef000 -#define MM_PMC_CFRAME_BCAST_FDRI_SIZE 0x1000 - -#define MM_PMC_CRP 0xf1260000U -#define MM_PMC_CRP_SIZE 0x10000 -#define MM_PMC_RTC 0xf12a0000 -#define MM_PMC_RTC_SIZE 0x10000 -#define MM_PMC_TRNG 0xf1230000 -#define MM_PMC_TRNG_SIZE 0x10000 #endif diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c index dc388300185..49b5b244403 100644 --- a/hw/arm/xlnx-versal.c +++ b/hw/arm/xlnx-versal.c @@ -18,7 +18,6 @@ #include "hw/sysbus.h" #include "net/net.h" #include "system/system.h" -#include "hw/arm/boot.h" #include "hw/misc/unimp.h" #include "hw/arm/xlnx-versal.h" #include "qemu/log.h" @@ -51,13 +50,6 @@ #include "hw/cpu/cluster.h" #include "hw/arm/bsa.h" =20 -#define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72") -#define XLNX_VERSAL_RCPU_TYPE ARM_CPU_TYPE_NAME("cortex-r5f") -#define GEM_REVISION 0x40070106 - -#define VERSAL_NUM_PMC_APB_IRQS 18 -#define NUM_OSPI_IRQ_LINES 3 - /* * IRQ descriptor to catch the following cases: * - Multiple devices can connect to the same IRQ. They are OR'ed togeth= er. @@ -1364,7 +1356,7 @@ static DeviceState *versal_create_ospi(Versal *s, linear_mr); =20 /* OSPI irq */ - orgate =3D create_or_gate(s, OBJECT(dev), "irq-orgate", NUM_OSPI_IRQ_L= INES, + orgate =3D create_or_gate(s, OBJECT(dev), "irq-orgate", 3, map->irq); =20 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(orgate, 0)= ); @@ -1625,18 +1617,12 @@ static void versal_unimp(Versal *s) DeviceState *slcr; qemu_irq gpio_in; =20 - versal_unimp_area(s, "psm", &s->mr_ps, - MM_PSM_START, MM_PSM_END - MM_PSM_START); - versal_unimp_area(s, "crf", &s->mr_ps, - MM_FPD_CRF, MM_FPD_CRF_SIZE); - versal_unimp_area(s, "apu", &s->mr_ps, - MM_FPD_FPD_APU, MM_FPD_FPD_APU_SIZE); - versal_unimp_area(s, "crp", &s->mr_ps, - MM_PMC_CRP, MM_PMC_CRP_SIZE); - versal_unimp_area(s, "iou-scntr", &s->mr_ps, - MM_IOU_SCNTR, MM_IOU_SCNTR_SIZE); - versal_unimp_area(s, "iou-scntr-seucre", &s->mr_ps, - MM_IOU_SCNTRS, MM_IOU_SCNTRS_SIZE); + versal_unimp_area(s, "psm", &s->mr_ps, 0xffc80000, 0x70000); + versal_unimp_area(s, "crf", &s->mr_ps, 0xfd1a0000, 0x140000); + versal_unimp_area(s, "apu", &s->mr_ps, 0xfd5c0000, 0x100); + versal_unimp_area(s, "crp", &s->mr_ps, 0xf1260000, 0x10000); + versal_unimp_area(s, "iou-scntr", &s->mr_ps, 0xff130000, 0x10000); + versal_unimp_area(s, "iou-scntr-seucre", &s->mr_ps, 0xff140000, 0x1000= 0); =20 qdev_init_gpio_in_named(DEVICE(s), versal_unimp_sd_emmc_sel, "sd-emmc-sel-dummy", 2); --=20 2.43.0