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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-46e78c5d290sm167037135e9.0.2025.10.07.07.11.59 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Oct 2025 07:12:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1759846321; x=1760451121; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=6K1r/UXmoqTTIwRgeNIErMtpaMXoLBqHoCdPYTCanlM=; b=yT2InjFgbLob4s9aSmxVjB0TC7jsOCv8lEHFJwgl1HHhzIrAKTQGRY7NOAe3Nd3TNg d6EFcJZs0vAMD9ITKLs+9tdm4zpDKNTosuLEuvLJHp6oAdBwOdtCV3Sr3HRsKWh7Ssf8 RgUVhA2aHJkemBASFcSQ3W21ue1BRV9bHJ/j1iWt/RRPHy3B4Jq84eOQYN9CF2qO5zat U7iP0hi9G01nT4C3LXGCTpY71lj1Lk0s+6XD8yFfRXF52kuQltiH2gLhcnLiJnWon7Ac 3uUoZ85+aakOv0gpqvBUY8yWafMpoAnHgh1fcT0RcuXTvNSD5vTEbhSrHp7hWyC+c13e OBjw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1759846321; x=1760451121; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6K1r/UXmoqTTIwRgeNIErMtpaMXoLBqHoCdPYTCanlM=; b=gVQmcOQX1LO55liy0sAljY4Obk7hbG9daD+gWABl43jUk22pQKl8t+xxgfC1hNi16Q Ok9e31gJy3Ez5mh2qzTCkpVnUnVaxj2ywg6F+PWh0om8Txs031K4pPtwCByevIGzt0Er MOYHBL9Ozwf4LxL7EdcCxagDjCr5WJRejzUoMV2eXwQLg/1GIU2Az85DFyRfZWUZA1lW FfHDpcl++mrZRKT+pRdtACyDqNuoGDeTROMryD/3wSfM75no14BSKQAnz6FZSF3o05oV dXN9qts3Sm3N2rgfZUjhKBdOv4sXnzoImKmkLfNyO5yHyTAdCXN8dypwleS2ZRXCMQTK eRVw== X-Gm-Message-State: AOJu0YwbG5BZicW/9E4BA0vJu2NHVoxC+gaKzbqHyYYFplKi0oKNNA0X 2yVXYl5+opj4eDcTVT6S2Fy28Y6rDChQkXVljmWTNxxLsgMeC1jywggcxWefGS3VrlHAvz8u4Gg 3G1k7 X-Gm-Gg: ASbGncvaNYD+qLmM1xf43RAOgI6VWpJ2pNDqv7KeJDZ++xMRQAjUfwsLl+DAUnNaFaK z8S3JIK5Ee5ULxIYEGTbnUHAwqfljwNrpy9gmYWTayUWHFghcZeDrtyagbF3eIiIPGM04CDDoM4 DHpnMgx6YhXRNCMK6PWvi9y/mD75ExjPYeGyistQteEroc5WHX9LCsFm+J1iWKnB9nqYMPrVByV 6PABeVGRyTY5eeg/nDENpOHTeKUhvt5Noz38g+Y0Q85+HEYWGbZLGaB6WQA5OT0feRSUVgVOjWk ySWeYDB3GS62kUwQYj4C9wfz2K2PhSL4y27K/ZQ/7ZHLSzTSTztTyEN36C9+TV22ZHsluzttzOn EhXilfEG+qJUndHLjTuMg/ItdJHrdfEKejct3UI9COZ6Yqds0whIEOIKB X-Google-Smtp-Source: AGHT+IH8h4eCg6GVh0cTAwM7KanAx3+R/ofGaEiPb40z3q2hICTj/WciHESDapeVdU6gu00qtw9k/A== X-Received: by 2002:a05:600c:4510:b0:46e:59bb:63cf with SMTP id 5b1f17b1804b1-46e71140be1mr130191695e9.24.1759846320785; Tue, 07 Oct 2025 07:12:00 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 33/62] hw/misc/xlnx-versal-crl: refactor device reset logic Date: Tue, 7 Oct 2025 15:10:53 +0100 Message-ID: <20251007141123.3239867-34-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251007141123.3239867-1-peter.maydell@linaro.org> References: <20251007141123.3239867-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1759847161340116600 From: Luc Michel Refactor the device reset logic to have a common register write callback for all the devices. This uses a decode function to map the register address to the actual peripheral to reset. This refactoring changes the CPU property name from cpu_r5[*] to rpu[*] to ease with the connections in the Versal SoC. It also fixes a bug where the gem device pointer was mapped to the usb link property. Signed-off-by: Luc Michel Reviewed-by: Francisco Iglesias Reviewed-by: Edgar E. Iglesias Tested-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20250926070806.292065-33-luc.michel@amd.com Signed-off-by: Peter Maydell --- include/hw/misc/xlnx-versal-crl.h | 8 +- hw/misc/xlnx-versal-crl.c | 169 ++++++++++++++++-------------- 2 files changed, 95 insertions(+), 82 deletions(-) diff --git a/include/hw/misc/xlnx-versal-crl.h b/include/hw/misc/xlnx-versa= l-crl.h index 2b39d203a67..7e50a95ad3c 100644 --- a/include/hw/misc/xlnx-versal-crl.h +++ b/include/hw/misc/xlnx-versal-crl.h @@ -220,8 +220,6 @@ REG32(PSM_RST_MODE, 0x370) =20 #define CRL_R_MAX (R_PSM_RST_MODE + 1) =20 -#define RPU_MAX_CPU 2 - struct XlnxVersalCRLBase { SysBusDevice parent_obj; =20 @@ -231,6 +229,8 @@ struct XlnxVersalCRLBase { =20 struct XlnxVersalCRLBaseClass { SysBusDeviceClass parent_class; + + DeviceState ** (*decode_periph_rst)(XlnxVersalCRLBase *s, hwaddr, size= _t *); }; =20 struct XlnxVersalCRL { @@ -238,11 +238,11 @@ struct XlnxVersalCRL { qemu_irq irq; =20 struct { - ARMCPU *cpu_r5[RPU_MAX_CPU]; + DeviceState *rpu[2]; DeviceState *adma[8]; DeviceState *uart[2]; DeviceState *gem[2]; - DeviceState *usb; + DeviceState *usb[1]; } cfg; =20 uint32_t regs[CRL_R_MAX]; diff --git a/hw/misc/xlnx-versal-crl.c b/hw/misc/xlnx-versal-crl.c index be89e0da40d..6225a92e0bd 100644 --- a/hw/misc/xlnx-versal-crl.c +++ b/hw/misc/xlnx-versal-crl.c @@ -55,90 +55,99 @@ static uint64_t crl_disable_prew(RegisterInfo *reg, uin= t64_t val64) return 0; } =20 -static void crl_reset_dev(XlnxVersalCRL *s, DeviceState *dev, - bool rst_old, bool rst_new) +static DeviceState **versal_decode_periph_rst(XlnxVersalCRLBase *s, + hwaddr addr, size_t *count) { - device_cold_reset(dev); -} + size_t idx; + XlnxVersalCRL *xvc =3D XLNX_VERSAL_CRL(s); =20 -static void crl_reset_cpu(XlnxVersalCRL *s, ARMCPU *armcpu, - bool rst_old, bool rst_new) -{ - if (rst_new) { - arm_set_cpu_off(arm_cpu_mp_affinity(armcpu)); - } else { - arm_set_cpu_on_and_reset(arm_cpu_mp_affinity(armcpu)); + *count =3D 1; + + switch (addr) { + case A_RST_CPU_R5: + return xvc->cfg.rpu; + + case A_RST_ADMA: + /* A single register fans out to all DMA reset inputs */ + *count =3D ARRAY_SIZE(xvc->cfg.adma); + return xvc->cfg.adma; + + case A_RST_UART0 ... A_RST_UART1: + idx =3D (addr - A_RST_UART0) / sizeof(uint32_t); + return xvc->cfg.uart + idx; + + case A_RST_GEM0 ... A_RST_GEM1: + idx =3D (addr - A_RST_GEM0) / sizeof(uint32_t); + return xvc->cfg.gem + idx; + + case A_RST_USB0: + return xvc->cfg.usb; + + default: + /* invalid or unimplemented */ + return NULL; } } =20 -#define REGFIELD_RESET(type, s, reg, f, new_val, dev) { \ - bool old_f =3D ARRAY_FIELD_EX32((s)->regs, reg, f); \ - bool new_f =3D FIELD_EX32(new_val, reg, f); \ - \ - /* Detect edges. */ \ - if (dev && old_f !=3D new_f) { \ - crl_reset_ ## type(s, dev, old_f, new_f); \ - } \ -} - -static uint64_t crl_rst_r5_prew(RegisterInfo *reg, uint64_t val64) +static uint64_t crl_rst_cpu_prew(RegisterInfo *reg, uint64_t val64) { - XlnxVersalCRL *s =3D XLNX_VERSAL_CRL(reg->opaque); + XlnxVersalCRLBase *s =3D XLNX_VERSAL_CRL_BASE(reg->opaque); + XlnxVersalCRLBaseClass *xvcbc =3D XLNX_VERSAL_CRL_BASE_GET_CLASS(s); + DeviceState **dev; + size_t i, count; =20 - REGFIELD_RESET(cpu, s, RST_CPU_R5, RESET_CPU0, val64, s->cfg.cpu_r5[0]= ); - REGFIELD_RESET(cpu, s, RST_CPU_R5, RESET_CPU1, val64, s->cfg.cpu_r5[1]= ); - return val64; -} + dev =3D xvcbc->decode_periph_rst(s, reg->access->addr, &count); =20 -static uint64_t crl_rst_adma_prew(RegisterInfo *reg, uint64_t val64) -{ - XlnxVersalCRL *s =3D XLNX_VERSAL_CRL(reg->opaque); - int i; + for (i =3D 0; i < 2; i++) { + bool prev, new; + uint64_t aff; =20 - /* A single register fans out to all ADMA reset inputs. */ - for (i =3D 0; i < ARRAY_SIZE(s->cfg.adma); i++) { - REGFIELD_RESET(dev, s, RST_ADMA, RESET, val64, s->cfg.adma[i]); + prev =3D extract32(s->regs[reg->access->addr / 4], i, 1); + new =3D extract32(val64, i, 1); + + if (prev =3D=3D new) { + continue; + } + + aff =3D arm_cpu_mp_affinity(ARM_CPU(dev[i])); + + if (new) { + arm_set_cpu_off(aff); + } else { + arm_set_cpu_on_and_reset(aff); + } } + return val64; } =20 -static uint64_t crl_rst_uart0_prew(RegisterInfo *reg, uint64_t val64) +static uint64_t crl_rst_dev_prew(RegisterInfo *reg, uint64_t val64) { - XlnxVersalCRL *s =3D XLNX_VERSAL_CRL(reg->opaque); + XlnxVersalCRLBase *s =3D XLNX_VERSAL_CRL_BASE(reg->opaque); + XlnxVersalCRLBaseClass *xvcbc =3D XLNX_VERSAL_CRL_BASE_GET_CLASS(s); + DeviceState **dev; + bool prev, new; + size_t i, count; =20 - REGFIELD_RESET(dev, s, RST_UART0, RESET, val64, s->cfg.uart[0]); - return val64; -} + dev =3D xvcbc->decode_periph_rst(s, reg->access->addr, &count); =20 -static uint64_t crl_rst_uart1_prew(RegisterInfo *reg, uint64_t val64) -{ - XlnxVersalCRL *s =3D XLNX_VERSAL_CRL(reg->opaque); + if (dev =3D=3D NULL) { + return val64; + } =20 - REGFIELD_RESET(dev, s, RST_UART1, RESET, val64, s->cfg.uart[1]); - return val64; -} + prev =3D s->regs[reg->access->addr / 4] & 0x1; + new =3D val64 & 0x1; =20 -static uint64_t crl_rst_gem0_prew(RegisterInfo *reg, uint64_t val64) -{ - XlnxVersalCRL *s =3D XLNX_VERSAL_CRL(reg->opaque); + if (prev =3D=3D new) { + return val64; + } =20 - REGFIELD_RESET(dev, s, RST_GEM0, RESET, val64, s->cfg.gem[0]); - return val64; -} + for (i =3D 0; i < count; i++) { + if (dev[i]) { + device_cold_reset(dev[i]); + } + } =20 -static uint64_t crl_rst_gem1_prew(RegisterInfo *reg, uint64_t val64) -{ - XlnxVersalCRL *s =3D XLNX_VERSAL_CRL(reg->opaque); - - REGFIELD_RESET(dev, s, RST_GEM1, RESET, val64, s->cfg.gem[1]); - return val64; -} - -static uint64_t crl_rst_usb_prew(RegisterInfo *reg, uint64_t val64) -{ - XlnxVersalCRL *s =3D XLNX_VERSAL_CRL(reg->opaque); - - REGFIELD_RESET(dev, s, RST_USB0, RESET, val64, s->cfg.usb); return val64; } =20 @@ -244,27 +253,27 @@ static const RegisterAccessInfo crl_regs_info[] =3D { },{ .name =3D "RST_CPU_R5", .addr =3D A_RST_CPU_R5, .reset =3D 0x17, .rsvd =3D 0x8, - .pre_write =3D crl_rst_r5_prew, + .pre_write =3D crl_rst_cpu_prew, },{ .name =3D "RST_ADMA", .addr =3D A_RST_ADMA, .reset =3D 0x1, - .pre_write =3D crl_rst_adma_prew, + .pre_write =3D crl_rst_dev_prew, },{ .name =3D "RST_GEM0", .addr =3D A_RST_GEM0, .reset =3D 0x1, - .pre_write =3D crl_rst_gem0_prew, + .pre_write =3D crl_rst_dev_prew, },{ .name =3D "RST_GEM1", .addr =3D A_RST_GEM1, .reset =3D 0x1, - .pre_write =3D crl_rst_gem1_prew, + .pre_write =3D crl_rst_dev_prew, },{ .name =3D "RST_SPARE", .addr =3D A_RST_SPARE, .reset =3D 0x1, },{ .name =3D "RST_USB0", .addr =3D A_RST_USB0, .reset =3D 0x1, - .pre_write =3D crl_rst_usb_prew, + .pre_write =3D crl_rst_dev_prew, },{ .name =3D "RST_UART0", .addr =3D A_RST_UART0, .reset =3D 0x1, - .pre_write =3D crl_rst_uart0_prew, + .pre_write =3D crl_rst_dev_prew, },{ .name =3D "RST_UART1", .addr =3D A_RST_UART1, .reset =3D 0x1, - .pre_write =3D crl_rst_uart1_prew, + .pre_write =3D crl_rst_dev_prew, },{ .name =3D "RST_SPI0", .addr =3D A_RST_SPI0, .reset =3D 0x1, },{ .name =3D "RST_SPI1", .addr =3D A_RST_SPI1, @@ -343,9 +352,9 @@ static void versal_crl_init(Object *obj) sysbus_init_mmio(sbd, &xvcb->reg_array->mem); sysbus_init_irq(sbd, &s->irq); =20 - for (i =3D 0; i < ARRAY_SIZE(s->cfg.cpu_r5); ++i) { - object_property_add_link(obj, "cpu_r5[*]", TYPE_ARM_CPU, - (Object **)&s->cfg.cpu_r5[i], + for (i =3D 0; i < ARRAY_SIZE(s->cfg.rpu); ++i) { + object_property_add_link(obj, "rpu[*]", TYPE_ARM_CPU, + (Object **)&s->cfg.rpu[i], qdev_prop_allow_set_link_before_realize, OBJ_PROP_LINK_STRONG); } @@ -371,10 +380,12 @@ static void versal_crl_init(Object *obj) OBJ_PROP_LINK_STRONG); } =20 - object_property_add_link(obj, "usb", TYPE_DEVICE, - (Object **)&s->cfg.gem[i], - qdev_prop_allow_set_link_before_realize, - OBJ_PROP_LINK_STRONG); + for (i =3D 0; i < ARRAY_SIZE(s->cfg.usb); ++i) { + object_property_add_link(obj, "usb[*]", TYPE_DEVICE, + (Object **)&s->cfg.usb[i], + qdev_prop_allow_set_link_before_realize, + OBJ_PROP_LINK_STRONG); + } } =20 static void crl_finalize(Object *obj) @@ -396,11 +407,13 @@ static const VMStateDescription vmstate_versal_crl = =3D { static void versal_crl_class_init(ObjectClass *klass, const void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); + XlnxVersalCRLBaseClass *xvcc =3D XLNX_VERSAL_CRL_BASE_CLASS(klass); ResettableClass *rc =3D RESETTABLE_CLASS(klass); =20 dc->vmsd =3D &vmstate_versal_crl; rc->phases.enter =3D versal_crl_reset_enter; rc->phases.hold =3D versal_crl_reset_hold; + xvcc->decode_periph_rst =3D versal_decode_periph_rst; } =20 static const TypeInfo crl_base_info =3D { --=20 2.43.0