From nobody Fri Nov 14 23:28:56 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1759846542; cv=none; d=zohomail.com; s=zohoarc; b=VXex3SQe/90n0E5pbiS5wVt/C/56PDe0shPXanjAyl1xwpIsR6EdiMrNoELubaE6oTo9U7sZIj/BkczuaiTkdqG60KtI4nd7KUBNCR+KnOLn5KxYRpvlvzsPoeQ3APxcTnDtScXKPsDG8Wg1jUJJCmw8KbKKg+E46kLTP4BQA54= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1759846542; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=KFDaQJ8q1spuEtlWey4phuXP7A/59oefPCkhFMboMnc=; b=BwvUVbe5ZAn7qiVzX/DwKJ/kayaKe/FsdlF+Eg59jrbghk1gM0bnVaw8YJIXVkRptEF1deqymILdPNNIOChFUuXeMrZpQhkdY3TuJRDblJXJQdnBurrmTibUPGHuBh0sRX/Ec58dr74rCacBcee//kUaoD4xCriAXpG7ob0WCEE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1759846542672848.5480354835069; Tue, 7 Oct 2025 07:15:42 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v68QQ-0005oQ-BV; Tue, 07 Oct 2025 10:12:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v68QK-0005mI-Qi for qemu-devel@nongnu.org; Tue, 07 Oct 2025 10:12:17 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1v68Q6-0002Cx-Tl for qemu-devel@nongnu.org; Tue, 07 Oct 2025 10:12:16 -0400 Received: by mail-wr1-x435.google.com with SMTP id ffacd0b85a97d-3f0308469a4so3642681f8f.0 for ; Tue, 07 Oct 2025 07:12:00 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-46e78c5d290sm167037135e9.0.2025.10.07.07.11.52 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Oct 2025 07:11:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1759846313; x=1760451113; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=KFDaQJ8q1spuEtlWey4phuXP7A/59oefPCkhFMboMnc=; b=Z7RI4/m2/ZSV2drPlqefKi59R5EHLHSvSnfLphvYPMw3uLMrhFaiKOZZn5NhV3/CJn P7vySjmgv1KKxFMu/ps4qyo25mOfl0aQRDj1Q+oHvCnwdad+Gf82fy0oNB+4dPLok4Kg y94dnPoa3N8LJQfdjn7tq2GXq8BdoNo5ce3417lvpIniw9kFu24LTzswILAq2lS3BxL9 PnD4GYGB7z46bHPb9xojrHlEdsOHTKzUOLb0JOjVKVa6Kb9X0trTBWk8K7zyGjgFdHUV zXGVJqYb1BYoRVGSRFs7i/fTUmwm8moihiz5sbIyhjvFg86nNceM9kXqKfQLC6J1WTh8 pU8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1759846313; x=1760451113; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KFDaQJ8q1spuEtlWey4phuXP7A/59oefPCkhFMboMnc=; b=Q/x2NmNTYs5UTyBaZfZ8wsRuvfVMXntH/X1f9ZPYkzVSDWUTroOwMokm516mN6wP0q SCGWgxLFkExrmPvkW+XyphX7QercqwRacBovS60Q4Q1X7qy+yI1MES3P7PepFj19/K3H AnAHpppechjormmnF+SRolEmHX6+n63DOBnjIqCIQZMVKRiQCrEwURtiT2yqL6Rs3Ifp ayU2b9fJra0bq5BBoQwqJHRMtfKfKsZ54K51mYf8Vav7oymEBEEGNozEtgyJEN6Yt93T ET7oyGQRsUBYbXc3rDlwOpV/aGs/xtRcXKI5YLMvND7jTNxc5zrsQti+CPxy/hEAQFAy 0SfQ== X-Gm-Message-State: AOJu0YynTrf93Faf1NZEJQRiYDgvm7re/OqWOGt6WeBCu3BbcbVQLB+K wDq2TIhans+18yzasLxMP53ZcgkofeAOugLuLPCYloE2jescHZHqrtdgmUinrV1OUUsKRWIMi12 +HYex X-Gm-Gg: ASbGncv+BK0+zAkoLprpvmQvGyRoqyqWrt9PlKf9VqgQrwu9j8s0afgpV6GkdRrB9Ax ZUBaVC6NZWJnKu2NAT1BMqXBUapX93KBACByUmxoLxa2ILh8nlUhrtrlgbqRQTEEPtt33tuCsi3 ukyunSQuvImZvy+XS8r77FnXqFywjjoD2sqZztOG7yRQglqrgMQaeccv1wmYbW4Tr+Mhe6srpUc lHKQ4EionONqwckrStRsnMoXXuq5RI0pT2S1oUjuyNDEt1dvIGxy2s2djSwq2xFHZGtX9spI6uQ 5My+kmEHZb9IhXzY1AG7i993Ut/52yU4m46SxY2/2tCcv8Y0Ekbdjj0n6fL0jHpjNI1r+J13K3O mqpoafKiiP2QA+/VuySFJDpDPhMWZbno1fabRjvxOyIi/M972maTcGgdS X-Google-Smtp-Source: AGHT+IH9Tl9uZTM7ox6wE5i9QHQ7goiQZtv10WfHnUgsKX+7u/uumr+7b4Fu0Cj8+XUM0tGhqIXR/w== X-Received: by 2002:a05:6000:1a85:b0:3e9:2fea:6795 with SMTP id ffacd0b85a97d-425671c7275mr10892978f8f.53.1759846313237; Tue, 07 Oct 2025 07:11:53 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 26/62] hw/arm/xlnx-versal: add support for GICv2 Date: Tue, 7 Oct 2025 15:10:46 +0100 Message-ID: <20251007141123.3239867-27-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251007141123.3239867-1-peter.maydell@linaro.org> References: <20251007141123.3239867-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1759846544475154101 From: Luc Michel Add support for GICv2 instantiation in the Versal SoC. This is in preparation for the RPU refactoring. Signed-off-by: Luc Michel Reviewed-by: Francisco Iglesias Reviewed-by: Edgar E. Iglesias Tested-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20250926070806.292065-26-luc.michel@amd.com Signed-off-by: Peter Maydell --- hw/arm/xlnx-versal.c | 82 +++++++++++++++++++++++++++++++++----------- 1 file changed, 62 insertions(+), 20 deletions(-) diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c index 9256eceffc7..45ea47a8b97 100644 --- a/hw/arm/xlnx-versal.c +++ b/hw/arm/xlnx-versal.c @@ -45,6 +45,7 @@ #include "hw/misc/xlnx-versal-crl.h" #include "hw/intc/arm_gicv3_common.h" #include "hw/intc/arm_gicv3_its_common.h" +#include "hw/intc/arm_gic.h" #include "hw/core/split-irq.h" =20 #define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72") @@ -74,6 +75,7 @@ typedef struct VersalGicMap { int version; uint64_t dist; uint64_t redist; + uint64_t cpu_iface; uint64_t its; size_t num_irq; bool has_its; @@ -503,6 +505,10 @@ static void versal_create_gic_its(Versal *s, g_autofree char *node_pat =3D NULL, *node =3D NULL; const char compatible[] =3D "arm,gic-v3-its"; =20 + if (map->gic.version !=3D 3) { + return; + } + if (!map->gic.has_its) { return; } @@ -542,45 +548,81 @@ static DeviceState *versal_create_gic(Versal *s, { DeviceState *dev; SysBusDevice *sbd; - QList *redist_region_count; g_autofree char *node =3D NULL; g_autofree char *name =3D NULL; - const char compatible[] =3D "arm,gic-v3"; + const char gicv3_compat[] =3D "arm,gic-v3"; + const char gicv2_compat[] =3D "arm,cortex-a15-gic"; + + switch (map->gic.version) { + case 2: + dev =3D qdev_new(gic_class_name()); + break; + + case 3: + dev =3D qdev_new(gicv3_class_name()); + break; + + default: + g_assert_not_reached(); + } =20 - dev =3D qdev_new(gicv3_class_name()); name =3D g_strdup_printf("%s-gic[*]", map->name); object_property_add_child(OBJECT(s), name, OBJECT(dev)); sbd =3D SYS_BUS_DEVICE(dev); - qdev_prop_set_uint32(dev, "revision", 3); + qdev_prop_set_uint32(dev, "revision", map->gic.version); qdev_prop_set_uint32(dev, "num-cpu", num_cpu); qdev_prop_set_uint32(dev, "num-irq", map->gic.num_irq + 32); - - redist_region_count =3D qlist_new(); - qlist_append_int(redist_region_count, num_cpu); - qdev_prop_set_array(dev, "redist-region-count", redist_region_count); - qdev_prop_set_bit(dev, "has-security-extensions", true); - qdev_prop_set_bit(dev, "has-lpi", map->gic.has_its); - object_property_set_link(OBJECT(dev), "sysmem", OBJECT(mr), &error_abo= rt); qdev_prop_set_uint32(dev, "first-cpu-index", first_cpu_idx); =20 + if (map->gic.version =3D=3D 3) { + QList *redist_region_count; + + redist_region_count =3D qlist_new(); + qlist_append_int(redist_region_count, num_cpu); + qdev_prop_set_array(dev, "redist-region-count", redist_region_coun= t); + qdev_prop_set_bit(dev, "has-lpi", map->gic.has_its); + object_property_set_link(OBJECT(dev), "sysmem", OBJECT(mr), + &error_abort); + + } + sysbus_realize_and_unref(sbd, &error_fatal); =20 memory_region_add_subregion(mr, map->gic.dist, sysbus_mmio_get_region(sbd, 0)); - memory_region_add_subregion(mr, map->gic.redist, - sysbus_mmio_get_region(sbd, 1)); + + if (map->gic.version =3D=3D 3) { + memory_region_add_subregion(mr, map->gic.redist, + sysbus_mmio_get_region(sbd, 1)); + } else { + memory_region_add_subregion(mr, map->gic.cpu_iface, + sysbus_mmio_get_region(sbd, 1)); + } =20 if (map->dtb_expose) { - node =3D versal_fdt_add_subnode(s, "/gic", map->gic.dist, compatib= le, - sizeof(compatible)); + if (map->gic.version =3D=3D 3) { + node =3D versal_fdt_add_subnode(s, "/gic", map->gic.dist, + gicv3_compat, + sizeof(gicv3_compat)); + qemu_fdt_setprop_sized_cells(s->cfg.fdt, node, "reg", + 2, map->gic.dist, + 2, 0x10000, + 2, map->gic.redist, + 2, GICV3_REDIST_SIZE * num_cpu); + } else { + node =3D versal_fdt_add_subnode(s, "/gic", map->gic.dist, + gicv2_compat, + sizeof(gicv2_compat)); + qemu_fdt_setprop_sized_cells(s->cfg.fdt, node, "reg", + 2, map->gic.dist, + 2, 0x1000, + 2, map->gic.cpu_iface, + 2, 0x1000); + } + qemu_fdt_setprop_cell(s->cfg.fdt, node, "phandle", s->phandle.gic); qemu_fdt_setprop_cell(s->cfg.fdt, node, "#interrupt-cells", 3); - qemu_fdt_setprop_sized_cells(s->cfg.fdt, node, "reg", - 2, map->gic.dist, - 2, 0x10000, - 2, map->gic.redist, - 2, GICV3_REDIST_SIZE * num_cpu); qemu_fdt_setprop_cells(s->cfg.fdt, node, "interrupts", GIC_FDT_IRQ_TYPE_PPI, VERSAL_GIC_MAINT_IRQ, GIC_FDT_IRQ_FLAGS_LEVEL_HI); --=20 2.43.0