From nobody Fri Nov 14 23:31:23 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1759685991492843.2325070955022; Sun, 5 Oct 2025 10:39:51 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v5Sgj-0000ZR-66; Sun, 05 Oct 2025 13:38:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v5Sga-0000QB-Mw; Sun, 05 Oct 2025 13:38:16 -0400 Received: from isrv.corpit.ru ([212.248.84.144]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v5SgN-0004eX-Ci; Sun, 05 Oct 2025 13:38:05 -0400 Received: from tsrv.corpit.ru (tsrv.tls.msk.ru [192.168.177.2]) by isrv.corpit.ru (Postfix) with ESMTP id ABA6A15AA8F; Sun, 05 Oct 2025 20:37:26 +0300 (MSK) Received: from think4mjt.tls.msk.ru (mjtthink.wg.tls.msk.ru [192.168.177.146]) by tsrv.corpit.ru (Postfix) with ESMTP id C9D1829973B; Sun, 5 Oct 2025 20:37:30 +0300 (MSK) From: Michael Tokarev To: qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, Max Chou , Alistair Francis , Michael Tokarev Subject: [Stable-10.0.5 52/58] target/riscv: rvv: Modify minimum VLEN according to enabled vector extensions Date: Sun, 5 Oct 2025 20:37:01 +0300 Message-ID: <20251005173712.445160-14-mjt@tls.msk.ru> X-Mailer: git-send-email 2.47.3 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=212.248.84.144; envelope-from=mjt@tls.msk.ru; helo=isrv.corpit.ru X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1759685993825116600 Content-Type: text/plain; charset="utf-8" From: Max Chou According to the RISC-V unprivileged specification, the VLEN should be grea= ter or equal to the ELEN. This commit modifies the minimum VLEN based on the ve= ctor extensions and introduces a check rule for VLEN and ELEN. Extension Minimum VLEN * V 128 * Zve64[d|f|x] 64 * Zve32[f|x] 32 Signed-off-by: Max Chou Reviewed-by: Alistair Francis Message-ID: <20250923090729.1887406-3-max.chou@sifive.com> Signed-off-by: Alistair Francis (cherry picked from commit be50ff3a73859ebbbdc0e6f704793062b1743d93) (Mjt: compensate #include for the lack of v10.0.0-214-g42fa9665e5 "exec: Re= strict 'cpu_ldst.h' to accel/tcg/") Signed-off-by: Michael Tokarev diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 2b21580ef7..863aebec45 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -280,12 +280,21 @@ static void riscv_cpu_validate_misa_priv(CPURISCVStat= e *env, Error **errp) static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg, Error **errp) { + uint32_t min_vlen; uint32_t vlen =3D cfg->vlenb << 3; =20 - if (vlen > RV_VLEN_MAX || vlen < 128) { + if (riscv_has_ext(env, RVV)) { + min_vlen =3D 128; + } else if (cfg->ext_zve64x) { + min_vlen =3D 64; + } else if (cfg->ext_zve32x) { + min_vlen =3D 32; + } + + if (vlen > RV_VLEN_MAX || vlen < min_vlen) { error_setg(errp, "Vector extension implementation only supports VLEN " - "in the range [128, %d]", RV_VLEN_MAX); + "in the range [%d, %d]", min_vlen, RV_VLEN_MAX); return; } =20 @@ -295,6 +304,12 @@ static void riscv_cpu_validate_v(CPURISCVState *env, R= ISCVCPUConfig *cfg, "in the range [8, 64]"); return; } + + if (vlen < cfg->elen) { + error_setg(errp, "Vector extension implementation requires VLEN " + "to be greater than or equal to ELEN"); + return; + } } =20 static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index fc31b21f29..e1e087a36b 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -25,7 +25,7 @@ #include "exec/helper-gen.h" =20 #include "exec/translator.h" -#include "accel/tcg/cpu-ldst.h" +#include "exec/cpu_ldst.h" #include "exec/translation-block.h" #include "exec/log.h" #include "semihosting/semihost.h" --=20 2.47.3