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Iglesias" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , "Vikram Garhwal" Subject: [PATCH v2 7/7] hw/net/can/xlnx-versal-canfd: remove register API usage for banked regs Date: Thu, 2 Oct 2025 09:34:16 +0200 Message-ID: <20251002073418.109375-8-luc.michel@amd.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251002073418.109375-1-luc.michel@amd.com> References: <20251002073418.109375-1-luc.michel@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: None (SATLEXMB05.amd.com: luc.michel@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044F3:EE_|MW4PR12MB6998:EE_ X-MS-Office365-Filtering-Correlation-Id: 6fbfec4c-fa38-4191-df62-08de018628a5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|376014|36860700013|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?xsXIvqiUGGiqXKx0LQ4wTFxUvC6m2cgIOdY0d8v14F/Fhe9YayC5tF/h8iog?= =?us-ascii?Q?rGZp6RXFztk0f6IoA9E1C6S3QcjxBAF2GESxaNOQre/3O2EgaKbBQUWQ4erv?= =?us-ascii?Q?hJt2THGtHprNvJdcbylVJb/88YdnpFD9bLlAV7mpAFT9/JVFzX561BVcJlWr?= =?us-ascii?Q?LwRnhITts3InQnnPbJW1IOjeEyoGvBvAZKk+CtD1iM/CJnmZh9Hj9M7ceobQ?= =?us-ascii?Q?vj9lirMIQ8iOMMhTTRkuv7ghY3DueCZBZ9l6dNzq9kpmPONLf2oMmaojze15?= =?us-ascii?Q?m18GjdKuWIrPfqGZEBvPGgchifxajaeFdInlMCfv1Qt3c4eq/7MbuXH1VRao?= =?us-ascii?Q?0ueh7hTyW5xQTTQK4SPAks7Lk4Gg6HUBzIltv/J1h+9aAyp/9qiTFFOrbapg?= =?us-ascii?Q?ulGHVyammaI1TWJbaA14GUBEDJbnfYGves9vES8O+Feii2NnTbOva5bQ45cd?= =?us-ascii?Q?+Iuup2Nl+Tw8ecGXUhYbWHoThtbg88V646qfpegR0Y0IKBCpgPZixcFIt45K?= =?us-ascii?Q?J0o6NAS1OVLH4oStCkjsXM4fc4AChTP3YW0eVvXeFPPtgyFn2siZDIIn+TDB?= =?us-ascii?Q?SKfriNbIbej5WBP6SLY8bD5Uww+seA0NZNjfz2o6KM6dN+ii2OhmhUREnQJ1?= =?us-ascii?Q?FA2AhbV1Iapk3+dWV/HsDsIearcu5KQjxd/VX9EILJTFYa/c++1Egamigg7e?= =?us-ascii?Q?dxKE0+AL6B0HwMqQeCS6W8+3b5GbA4kJaIxr6OWL0t8tb8Kgx/rWgFP+yFxW?= =?us-ascii?Q?uEPuKZtXEabI1L25CnfdPKwDfWmhkvucIHoTW3g1CsQDjDzNVLz8o62jZPPA?= =?us-ascii?Q?eytaIKxZQBpADi1ybRVVd7kMLNtzBTofxgW1MHRa0B1NrT7P075DtpFJ5JcQ?= =?us-ascii?Q?FRHaMApWdfel/mmc1bE6qPbq2U0MA46IWL37a3WC5axSuNlmls5Fj2oLbPoN?= =?us-ascii?Q?TQLMq4nM7v5YpU8DhLmyNW3/sHS837vdah4zbvwriVII3NcSU3IoqISftsHT?= =?us-ascii?Q?OaFoaAI52/Ey7Ye+GGPEtCKJtKu6KaUi9ArArw8haJffG3sh+MiZipQyLtTQ?= =?us-ascii?Q?UIRbpIpqfRPLSm6m4YyyPEkUv/VAmkZlp8SBOrMs69RctJiIIpZvssMYTMLc?= =?us-ascii?Q?FzEz3rL8jJ81BcDKw9aOUG6cheXrIcHMROKBWg/8VrYBbMOho4REzV+2HLIz?= =?us-ascii?Q?K0q2VzTulR1XTRusdxAFxKxcv8RXdwiF2j3EZUgwTXOcJd4Mv0l/gx95qBAk?= =?us-ascii?Q?fVd601zF/J5IxyvkybvH9VwE05n6asNksxdANumXjLiPcyDLZHFcQe97t8qa?= =?us-ascii?Q?8oIOQ6dkZLcUAVx7726OTxIUMjZ3ZGO6jnQ+kfe2AfxMg6qAMNeK1WfBVdzd?= =?us-ascii?Q?WfxF8Z09qwgUeYBsGY6SJW3HroG+xRUqlo8ZUeKjG6iR6SraRtlzgPWbdmEO?= =?us-ascii?Q?bVNESxaFlyk1LrLlkIC5BRLUrr1wjtl54wktScdjP2UQ9xZ4KzxlOuDBht0+?= =?us-ascii?Q?rCgnUT1fNn6EJeupS4QVnKk33pW9aYEXBGp7ks9tlOafI0d+XlaKfAG66hB/?= =?us-ascii?Q?FEH0yIfxucqwiAVlBps=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:satlexmb07.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(376014)(36860700013)(1800799024)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Oct 2025 07:34:45.0988 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6fbfec4c-fa38-4191-df62-08de018628a5 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044F3.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB6998 Received-SPF: permerror client-ip=2a01:111:f403:c105::5; envelope-from=Luc.Michel@amd.com; helo=CH5PR02CU005.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1759390707319116600 Content-Type: text/plain; charset="utf-8" Now that we have a simple decoding logic for all the banked registers, remove the register API usage for them. This restricts the register API usage to only the base registers (from 0x0 to 0xec). This also removes all the custom code that was creating register descriptors for the register API and was leading to memory leaks when the device was finalized. Reviewed-by: Francisco Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Luc Michel --- include/hw/net/xlnx-versal-canfd.h | 8 - hw/net/can/xlnx-versal-canfd.c | 295 +---------------------------- 2 files changed, 5 insertions(+), 298 deletions(-) diff --git a/include/hw/net/xlnx-versal-canfd.h b/include/hw/net/xlnx-versa= l-canfd.h index ad3104dd13f..396f90d6dc1 100644 --- a/include/hw/net/xlnx-versal-canfd.h +++ b/include/hw/net/xlnx-versal-canfd.h @@ -52,18 +52,10 @@ typedef struct XlnxVersalCANFDState { =20 qemu_irq irq_canfd_int; qemu_irq irq_addr_err; =20 RegisterInfo reg_info[XLNX_VERSAL_CANFD_R_MAX]; - RegisterAccessInfo *tx_regs; - RegisterAccessInfo *rx0_regs; - RegisterAccessInfo *rx1_regs; - RegisterAccessInfo *af_regs; - RegisterAccessInfo *txe_regs; - RegisterAccessInfo *rx_mailbox_regs; - RegisterAccessInfo *af_mask_regs_mailbox; - uint32_t regs[XLNX_VERSAL_CANFD_R_MAX]; =20 ptimer_state *canfd_timer; =20 CanBusClientState bus_client; diff --git a/hw/net/can/xlnx-versal-canfd.c b/hw/net/can/xlnx-versal-canfd.c index 81615bc52a6..49f1b174b70 100644 --- a/hw/net/can/xlnx-versal-canfd.c +++ b/hw/net/can/xlnx-versal-canfd.c @@ -1425,50 +1425,10 @@ static void filter_reg_write(XlnxVersalCANFDState *= s, hwaddr addr, HWADDR_PRIx " changed while filter %zu enabled\n", path, addr, bank_idx + 1); } } =20 -static uint64_t filter_mask(RegisterInfo *reg, uint64_t val64) -{ - XlnxVersalCANFDState *s =3D XILINX_CANFD(reg->opaque); - uint32_t reg_idx =3D (reg->access->addr) / 4; - uint32_t val =3D val64; - uint32_t filter_offset =3D (reg_idx - R_AFMR_REGISTER) / 2; - - if (!(s->regs[R_ACCEPTANCE_FILTER_CONTROL_REGISTER] & - (1 << filter_offset))) { - s->regs[reg_idx] =3D val; - } else { - g_autofree char *path =3D object_get_canonical_path(OBJECT(s)); - - qemu_log_mask(LOG_GUEST_ERROR, "%s: Acceptance filter %d not enabl= ed\n", - path, filter_offset + 1); - } - - return s->regs[reg_idx]; -} - -static uint64_t filter_id(RegisterInfo *reg, uint64_t val64) -{ - XlnxVersalCANFDState *s =3D XILINX_CANFD(reg->opaque); - hwaddr reg_idx =3D (reg->access->addr) / 4; - uint32_t val =3D val64; - uint32_t filter_offset =3D (reg_idx - R_AFIR_REGISTER) / 2; - - if (!(s->regs[R_ACCEPTANCE_FILTER_CONTROL_REGISTER] & - (1 << filter_offset))) { - s->regs[reg_idx] =3D val; - } else { - g_autofree char *path =3D object_get_canonical_path(OBJECT(s)); - - qemu_log_mask(LOG_GUEST_ERROR, "%s: Acceptance filter %d not enabl= ed\n", - path, filter_offset + 1); - } - - return s->regs[reg_idx]; -} - static uint64_t canfd_tx_fifo_status_prew(RegisterInfo *reg, uint64_t val6= 4) { XlnxVersalCANFDState *s =3D XILINX_CANFD(reg->opaque); uint32_t val =3D val64; uint8_t read_ind =3D 0; @@ -1590,129 +1550,10 @@ static uint64_t canfd_write_check_prew(RegisterInf= o *reg, uint64_t val64) return val; } return 0; } =20 -static const RegisterAccessInfo canfd_tx_regs[] =3D { - { .name =3D "TB_ID_REGISTER", .addr =3D A_TB_ID_REGISTER, - },{ .name =3D "TB0_DLC_REGISTER", .addr =3D A_TB0_DLC_REGISTER, - },{ .name =3D "TB_DW0_REGISTER", .addr =3D A_TB_DW0_REGISTER, - },{ .name =3D "TB_DW1_REGISTER", .addr =3D A_TB_DW1_REGISTER, - },{ .name =3D "TB_DW2_REGISTER", .addr =3D A_TB_DW2_REGISTER, - },{ .name =3D "TB_DW3_REGISTER", .addr =3D A_TB_DW3_REGISTER, - },{ .name =3D "TB_DW4_REGISTER", .addr =3D A_TB_DW4_REGISTER, - },{ .name =3D "TB_DW5_REGISTER", .addr =3D A_TB_DW5_REGISTER, - },{ .name =3D "TB_DW6_REGISTER", .addr =3D A_TB_DW6_REGISTER, - },{ .name =3D "TB_DW7_REGISTER", .addr =3D A_TB_DW7_REGISTER, - },{ .name =3D "TB_DW8_REGISTER", .addr =3D A_TB_DW8_REGISTER, - },{ .name =3D "TB_DW9_REGISTER", .addr =3D A_TB_DW9_REGISTER, - },{ .name =3D "TB_DW10_REGISTER", .addr =3D A_TB_DW10_REGISTER, - },{ .name =3D "TB_DW11_REGISTER", .addr =3D A_TB_DW11_REGISTER, - },{ .name =3D "TB_DW12_REGISTER", .addr =3D A_TB_DW12_REGISTER, - },{ .name =3D "TB_DW13_REGISTER", .addr =3D A_TB_DW13_REGISTER, - },{ .name =3D "TB_DW14_REGISTER", .addr =3D A_TB_DW14_REGISTER, - },{ .name =3D "TB_DW15_REGISTER", .addr =3D A_TB_DW15_REGISTER, - } -}; - -static const RegisterAccessInfo canfd_rx0_regs[] =3D { - { .name =3D "RB_ID_REGISTER", .addr =3D A_RB_ID_REGISTER, - .ro =3D 0xffffffff, - },{ .name =3D "RB_DLC_REGISTER", .addr =3D A_RB_DLC_REGISTER, - .ro =3D 0xfe1fffff, - },{ .name =3D "RB_DW0_REGISTER", .addr =3D A_RB_DW0_REGISTER, - .ro =3D 0xffffffff, - },{ .name =3D "RB_DW1_REGISTER", .addr =3D A_RB_DW1_REGISTER, - .ro =3D 0xffffffff, - },{ .name =3D "RB_DW2_REGISTER", .addr =3D A_RB_DW2_REGISTER, - .ro =3D 0xffffffff, - },{ .name =3D "RB_DW3_REGISTER", .addr =3D A_RB_DW3_REGISTER, - .ro =3D 0xffffffff, - },{ .name =3D "RB_DW4_REGISTER", .addr =3D A_RB_DW4_REGISTER, - .ro =3D 0xffffffff, - },{ .name =3D "RB_DW5_REGISTER", .addr =3D A_RB_DW5_REGISTER, - .ro =3D 0xffffffff, - },{ .name =3D "RB_DW6_REGISTER", .addr =3D A_RB_DW6_REGISTER, - .ro =3D 0xffffffff, - },{ .name =3D "RB_DW7_REGISTER", .addr =3D A_RB_DW7_REGISTER, - .ro =3D 0xffffffff, - },{ .name =3D "RB_DW8_REGISTER", .addr =3D A_RB_DW8_REGISTER, - .ro =3D 0xffffffff, - },{ .name =3D "RB_DW9_REGISTER", .addr =3D A_RB_DW9_REGISTER, - .ro =3D 0xffffffff, - },{ .name =3D "RB_DW10_REGISTER", .addr =3D A_RB_DW10_REGISTER, - .ro =3D 0xffffffff, - },{ .name =3D "RB_DW11_REGISTER", .addr =3D A_RB_DW11_REGISTER, - .ro =3D 0xffffffff, - },{ .name =3D "RB_DW12_REGISTER", .addr =3D A_RB_DW12_REGISTER, - .ro =3D 0xffffffff, - },{ .name =3D "RB_DW13_REGISTER", .addr =3D A_RB_DW13_REGISTER, - .ro =3D 0xffffffff, - },{ .name =3D "RB_DW14_REGISTER", .addr =3D A_RB_DW14_REGISTER, - .ro =3D 0xffffffff, - },{ .name =3D "RB_DW15_REGISTER", .addr =3D A_RB_DW15_REGISTER, - .ro =3D 0xffffffff, - } -}; - -static const RegisterAccessInfo canfd_rx1_regs[] =3D { - { .name =3D "RB_ID_REGISTER_1", .addr =3D A_RB_ID_REGISTER_1, - .ro =3D 0xffffffff, - },{ .name =3D "RB_DLC_REGISTER_1", .addr =3D A_RB_DLC_REGISTER_1, - .ro =3D 0xfe1fffff, - },{ .name =3D "RB0_DW0_REGISTER_1", .addr =3D A_RB0_DW0_REGISTER_1, - .ro =3D 0xffffffff, - },{ .name =3D "RB_DW1_REGISTER_1", .addr =3D A_RB_DW1_REGISTER_1, - .ro =3D 0xffffffff, - },{ .name =3D "RB_DW2_REGISTER_1", .addr =3D A_RB_DW2_REGISTER_1, - .ro =3D 0xffffffff, - },{ .name =3D "RB_DW3_REGISTER_1", .addr =3D A_RB_DW3_REGISTER_1, - .ro =3D 0xffffffff, - },{ .name =3D "RB_DW4_REGISTER_1", .addr =3D A_RB_DW4_REGISTER_1, - .ro =3D 0xffffffff, - },{ .name =3D "RB_DW5_REGISTER_1", .addr =3D A_RB_DW5_REGISTER_1, - .ro =3D 0xffffffff, - },{ .name =3D "RB_DW6_REGISTER_1", .addr =3D A_RB_DW6_REGISTER_1, - .ro =3D 0xffffffff, - },{ .name =3D "RB_DW7_REGISTER_1", .addr =3D A_RB_DW7_REGISTER_1, - .ro =3D 0xffffffff, - },{ .name =3D "RB_DW8_REGISTER_1", .addr =3D A_RB_DW8_REGISTER_1, - .ro =3D 0xffffffff, - },{ .name =3D "RB_DW9_REGISTER_1", .addr =3D A_RB_DW9_REGISTER_1, - .ro =3D 0xffffffff, - },{ .name =3D "RB_DW10_REGISTER_1", .addr =3D A_RB_DW10_REGISTER_1, - .ro =3D 0xffffffff, - },{ .name =3D "RB_DW11_REGISTER_1", .addr =3D A_RB_DW11_REGISTER_1, - .ro =3D 0xffffffff, - },{ .name =3D "RB_DW12_REGISTER_1", .addr =3D A_RB_DW12_REGISTER_1, - .ro =3D 0xffffffff, - },{ .name =3D "RB_DW13_REGISTER_1", .addr =3D A_RB_DW13_REGISTER_1, - .ro =3D 0xffffffff, - },{ .name =3D "RB_DW14_REGISTER_1", .addr =3D A_RB_DW14_REGISTER_1, - .ro =3D 0xffffffff, - },{ .name =3D "RB_DW15_REGISTER_1", .addr =3D A_RB_DW15_REGISTER_1, - .ro =3D 0xffffffff, - } -}; - -/* Acceptance filter registers. */ -static const RegisterAccessInfo canfd_af_regs[] =3D { - { .name =3D "AFMR_REGISTER", .addr =3D A_AFMR_REGISTER, - .pre_write =3D filter_mask, - },{ .name =3D "AFIR_REGISTER", .addr =3D A_AFIR_REGISTER, - .pre_write =3D filter_id, - } -}; - -static const RegisterAccessInfo canfd_txe_regs[] =3D { - { .name =3D "TXE_FIFO_TB_ID_REGISTER", .addr =3D A_TXE_FIFO_TB_ID_R= EGISTER, - .ro =3D 0xffffffff, - },{ .name =3D "TXE_FIFO_TB_DLC_REGISTER", .addr =3D A_TXE_FIFO_TB_DLC= _REGISTER, - .ro =3D 0xffffffff, - } -}; - static const RegisterAccessInfo canfd_regs_info[] =3D { { .name =3D "SOFTWARE_RESET_REGISTER", .addr =3D A_SOFTWARE_RESET_R= EGISTER, .pre_write =3D canfd_srr_pre_write, },{ .name =3D "MODE_SELECT_REGISTER", .addr =3D A_MODE_SELECT_REGISTE= R, .pre_write =3D canfd_msr_pre_write, @@ -2001,146 +1842,20 @@ static int xlnx_canfd_connect_to_bus(XlnxVersalCAN= FDState *s, s->bus_client.info =3D &canfd_xilinx_bus_client_info; =20 return can_bus_insert_client(bus, &s->bus_client); } =20 -#define NUM_REG_PER_AF ARRAY_SIZE(canfd_af_regs) -#define NUM_AF 32 -#define NUM_REG_PER_TXE ARRAY_SIZE(canfd_txe_regs) -#define NUM_TXE 32 - -static int canfd_populate_regarray(XlnxVersalCANFDState *s, - RegisterInfoArray *r_array, int pos, - const RegisterAccessInfo *rae, - int num_rae) -{ - int i; - - for (i =3D 0; i < num_rae; i++) { - int index =3D rae[i].addr / 4; - RegisterInfo *r =3D &s->reg_info[index]; - - object_initialize(r, sizeof(*r), TYPE_REGISTER); - - *r =3D (RegisterInfo) { - .data =3D &s->regs[index], - .data_size =3D sizeof(uint32_t), - .access =3D &rae[i], - .opaque =3D OBJECT(s), - }; - - r_array->r[i + pos] =3D r; - } - return i + pos; -} - -static void canfd_create_rai(RegisterAccessInfo *rai_array, - const RegisterAccessInfo *canfd_regs, - int template_rai_array_sz, - int num_template_to_copy) -{ - int i; - int reg_num; - - for (reg_num =3D 0; reg_num < num_template_to_copy; reg_num++) { - int pos =3D reg_num * template_rai_array_sz; - - memcpy(rai_array + pos, canfd_regs, - template_rai_array_sz * sizeof(RegisterAccessInfo)); - - for (i =3D 0; i < template_rai_array_sz; i++) { - const char *name =3D canfd_regs[i].name; - uint64_t addr =3D canfd_regs[i].addr; - rai_array[i + pos].name =3D g_strdup_printf("%s%d", name, reg_= num); - rai_array[i + pos].addr =3D addr + pos * 4; - } - } -} - -static RegisterInfoArray *canfd_create_regarray(XlnxVersalCANFDState *s) -{ - const char *device_prefix =3D object_get_typename(OBJECT(s)); - uint64_t memory_size =3D XLNX_VERSAL_CANFD_R_MAX * 4; - int num_regs; - int pos =3D 0; - RegisterInfoArray *r_array; - - num_regs =3D ARRAY_SIZE(canfd_regs_info) + - s->cfg.tx_fifo * NUM_REGS_PER_MSG_SPACE + - s->cfg.rx0_fifo * NUM_REGS_PER_MSG_SPACE + - NUM_AF * NUM_REG_PER_AF + - NUM_TXE * NUM_REG_PER_TXE; - - s->tx_regs =3D g_new0(RegisterAccessInfo, - s->cfg.tx_fifo * ARRAY_SIZE(canfd_tx_regs)); - - canfd_create_rai(s->tx_regs, canfd_tx_regs, - ARRAY_SIZE(canfd_tx_regs), s->cfg.tx_fifo); - - s->rx0_regs =3D g_new0(RegisterAccessInfo, - s->cfg.rx0_fifo * ARRAY_SIZE(canfd_rx0_regs)); - - canfd_create_rai(s->rx0_regs, canfd_rx0_regs, - ARRAY_SIZE(canfd_rx0_regs), s->cfg.rx0_fifo); - - s->af_regs =3D g_new0(RegisterAccessInfo, - NUM_AF * ARRAY_SIZE(canfd_af_regs)); - - canfd_create_rai(s->af_regs, canfd_af_regs, - ARRAY_SIZE(canfd_af_regs), NUM_AF); - - s->txe_regs =3D g_new0(RegisterAccessInfo, - NUM_TXE * ARRAY_SIZE(canfd_txe_regs)); - - canfd_create_rai(s->txe_regs, canfd_txe_regs, - ARRAY_SIZE(canfd_txe_regs), NUM_TXE); - - if (s->cfg.enable_rx_fifo1) { - num_regs +=3D s->cfg.rx1_fifo * NUM_REGS_PER_MSG_SPACE; - - s->rx1_regs =3D g_new0(RegisterAccessInfo, - s->cfg.rx1_fifo * ARRAY_SIZE(canfd_rx1_regs)); - - canfd_create_rai(s->rx1_regs, canfd_rx1_regs, - ARRAY_SIZE(canfd_rx1_regs), s->cfg.rx1_fifo); - } - - r_array =3D g_new0(RegisterInfoArray, 1); - r_array->r =3D g_new0(RegisterInfo * , num_regs); - r_array->num_elements =3D num_regs; - r_array->prefix =3D device_prefix; - - pos =3D canfd_populate_regarray(s, r_array, pos, - canfd_regs_info, - ARRAY_SIZE(canfd_regs_info)); - pos =3D canfd_populate_regarray(s, r_array, pos, - s->tx_regs, s->cfg.tx_fifo * - NUM_REGS_PER_MSG_SPACE); - pos =3D canfd_populate_regarray(s, r_array, pos, - s->rx0_regs, s->cfg.rx0_fifo * - NUM_REGS_PER_MSG_SPACE); - if (s->cfg.enable_rx_fifo1) { - pos =3D canfd_populate_regarray(s, r_array, pos, - s->rx1_regs, s->cfg.rx1_fifo * - NUM_REGS_PER_MSG_SPACE); - } - pos =3D canfd_populate_regarray(s, r_array, pos, - s->af_regs, NUM_AF * NUM_REG_PER_AF); - pos =3D canfd_populate_regarray(s, r_array, pos, - s->txe_regs, NUM_TXE * NUM_REG_PER_TXE); - - memory_region_init_io(&r_array->mem, OBJECT(s), &canfd_ops, r_array, - device_prefix, memory_size); - return r_array; -} - static void canfd_realize(DeviceState *dev, Error **errp) { XlnxVersalCANFDState *s =3D XILINX_CANFD(dev); RegisterInfoArray *reg_array; =20 - reg_array =3D canfd_create_regarray(s); + reg_array =3D register_init_block32(dev, canfd_regs_info, + ARRAY_SIZE(canfd_regs_info), s->reg_= info, + s->regs, &canfd_regs_ops, false, + A_RX_FIFO_WATERMARK_REGISTER + + sizeof(uint32_t)); memory_region_add_subregion(&s->iomem, 0x00, ®_array->mem); sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq_canfd_int); =20 if (s->canfdbus) { --=20 2.51.0