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Tue, 30 Sep 2025 18:02:28 -0700 (PDT) From: salil.mehta@opnsrc.net To: qemu-devel@nongnu.org, qemu-arm@nongnu.org, mst@redhat.com Cc: salil.mehta@huawei.com, maz@kernel.org, jean-philippe@linaro.org, jonathan.cameron@huawei.com, lpieralisi@kernel.org, peter.maydell@linaro.org, richard.henderson@linaro.org, imammedo@redhat.com, armbru@redhat.com, andrew.jones@linux.dev, david@redhat.com, philmd@linaro.org, eric.auger@redhat.com, will@kernel.org, ardb@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, gshan@redhat.com, rafael@kernel.org, borntraeger@linux.ibm.com, alex.bennee@linaro.org, gustavo.romero@linaro.org, npiggin@gmail.com, harshpb@linux.ibm.com, linux@armlinux.org.uk, darren@os.amperecomputing.com, ilkka@os.amperecomputing.com, vishnu@os.amperecomputing.com, gankulkarni@os.amperecomputing.com, karl.heubaum@oracle.com, miguel.luis@oracle.com, salil.mehta@opnsrc.net, zhukeqian1@huawei.com, wangxiongfeng2@huawei.com, wangyanan55@huawei.com, wangzhou1@hisilicon.com, linuxarm@huawei.com, jiakernel2@gmail.com, maobibo@loongson.cn, lixianglai@loongson.cn, shahuang@redhat.com, zhao1.liu@intel.com Subject: [PATCH RFC V6 07/24] arm/gicv3: Refactor CPU interface init for shared TCG/KVM use Date: Wed, 1 Oct 2025 01:01:10 +0000 Message-Id: <20251001010127.3092631-8-salil.mehta@opnsrc.net> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251001010127.3092631-1-salil.mehta@opnsrc.net> References: <20251001010127.3092631-1-salil.mehta@opnsrc.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=salil.mehta@opnsrc.net; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @opnsrc.net) X-ZM-MESSAGEID: 1759281301176116600 From: Salil Mehta GICv3 CPU interface initialization currently has separate logic paths for T= CG and KVM accelerators, even though much of the flow=E2=80=94such as iteratin= g over vCPUs and applying common setup=E2=80=94should be identical. This separation make= s it harder to add new CPU interface features that apply to both backends, as each need= s to be updated individually. To address this, the common CPU interface setup is now centralized in =E2=80=98gicv3_init_cpuif()=E2=80=99, called during GIC realization. Accele= rator-specific code is still handled via a class hook for register-level initialization, but all iteration and shared setup is unified. This refactoring is required to: - Ensure later patches can set =E2=80=98gicc_accessible=E2=80=98 for all v= CPUs in a consistent manner. - Provide a single entry point for any future common initialization, avoid= ing duplication between TCG and KVM. - Maintain correct initialization for both enabled and administratively disabled but present vCPUs. No functional change intended here. Co-developed-by: Keqian Zhu Signed-off-by: Keqian Zhu Signed-off-by: Salil Mehta --- hw/intc/arm_gicv3.c | 1 + hw/intc/arm_gicv3_cpuif.c | 262 ++++++++++++++--------------- hw/intc/arm_gicv3_cpuif_common.c | 11 ++ hw/intc/arm_gicv3_kvm.c | 12 +- hw/intc/gicv3_internal.h | 1 + include/hw/intc/arm_gicv3_common.h | 1 + 6 files changed, 150 insertions(+), 138 deletions(-) diff --git a/hw/intc/arm_gicv3.c b/hw/intc/arm_gicv3.c index 6059ce926a..8ca61413d2 100644 --- a/hw/intc/arm_gicv3.c +++ b/hw/intc/arm_gicv3.c @@ -459,6 +459,7 @@ static void arm_gicv3_class_init(ObjectClass *klass, co= nst void *data) ARMGICv3Class *agc =3D ARM_GICV3_CLASS(klass); =20 agcc->post_load =3D arm_gicv3_post_load; + agcc->init_cpu_reginfo =3D gicv3_init_cpu_reginfo; device_class_set_parent_realize(dc, arm_gic_realize, &agc->parent_real= ize); } =20 diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index 4b4cf09157..a7904237ac 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -3016,154 +3016,150 @@ static void gicv3_cpuif_el_change_hook(ARMCPU *cp= u, void *opaque) gicv3_cpuif_virt_irq_fiq_update(cs); } =20 -void gicv3_init_cpuif(GICv3State *s) +void gicv3_init_cpu_reginfo(CPUState *cs) { /* Called from the GICv3 realize function; register our system * registers with the CPU */ - int i; - - for (i =3D 0; i < s->num_cpu; i++) { - ARMCPU *cpu =3D ARM_CPU(qemu_get_cpu(i)); - GICv3CPUState *cs =3D &s->cpu[i]; + ARMCPU *cpu =3D ARM_CPU(cs); + GICv3CPUState *gcs =3D icc_cs_from_env(&cpu->env); =20 - /* - * If the CPU doesn't define a GICv3 configuration, probably becau= se - * in real hardware it doesn't have one, then we use default values - * matching the one used by most Arm CPUs. This applies to: - * cpu->gic_num_lrs - * cpu->gic_vpribits - * cpu->gic_vprebits - * cpu->gic_pribits - */ + /* + * If the CPU doesn't define a GICv3 configuration, probably because + * in real hardware it doesn't have one, then we use default values + * matching the one used by most Arm CPUs. This applies to: + * cpu->gic_num_lrs + * cpu->gic_vpribits + * cpu->gic_vprebits + * cpu->gic_pribits + */ =20 - /* Note that we can't just use the GICv3CPUState as an opaque poin= ter - * in define_arm_cp_regs_with_opaque(), because when we're called = back - * it might be with code translated by CPU 0 but run by CPU 1, in - * which case we'd get the wrong value. - * So instead we define the regs with no ri->opaque info, and - * get back to the GICv3CPUState from the CPUARMState. - * - * These CP regs callbacks can be called from either TCG or HVF co= de. - */ - define_arm_cp_regs(cpu, gicv3_cpuif_reginfo); + /* Note that we can't just use the GICv3CPUState as an opaque pointer + * in define_arm_cp_regs_with_opaque(), because when we're called back + * it might be with code translated by CPU 0 but run by CPU 1, in + * which case we'd get the wrong value. + * So instead we define the regs with no ri->opaque info, and + * get back to the GICv3CPUState from the CPUARMState. + * + * These CP regs callbacks can be called from either TCG or HVF code. + */ + define_arm_cp_regs(cpu, gicv3_cpuif_reginfo); =20 - /* - * If the CPU implements FEAT_NMI and FEAT_GICv3 it must also - * implement FEAT_GICv3_NMI, which is the CPU interface part - * of NMI support. This is distinct from whether the GIC proper - * (redistributors and distributor) have NMI support. In QEMU - * that is a property of the GIC device in s->nmi_support; - * cs->nmi_support indicates the CPU interface's support. - */ - if (cpu_isar_feature(aa64_nmi, cpu)) { - cs->nmi_support =3D true; - define_arm_cp_regs(cpu, gicv3_cpuif_gicv3_nmi_reginfo); - } + /* + * If the CPU implements FEAT_NMI and FEAT_GICv3 it must also + * implement FEAT_GICv3_NMI, which is the CPU interface part + * of NMI support. This is distinct from whether the GIC proper + * (redistributors and distributor) have NMI support. In QEMU + * that is a property of the GIC device in s->nmi_support; + * gcs->nmi_support indicates the CPU interface's support. + */ + if (cpu_isar_feature(aa64_nmi, cpu)) { + gcs->nmi_support =3D true; + define_arm_cp_regs(cpu, gicv3_cpuif_gicv3_nmi_reginfo); + } =20 - /* - * The CPU implementation specifies the number of supported - * bits of physical priority. For backwards compatibility - * of migration, we have a compat property that forces use - * of 8 priority bits regardless of what the CPU really has. - */ - if (s->force_8bit_prio) { - cs->pribits =3D 8; - } else { - cs->pribits =3D cpu->gic_pribits ?: 5; - } + /* + * The CPU implementation specifies the number of supported + * bits of physical priority. For backwards compatibility + * of migration, we have a compat property that forces use + * of 8 priority bits regardless of what the CPU really has. + */ + if (gcs->gic->force_8bit_prio) { + gcs->pribits =3D 8; + } else { + gcs->pribits =3D cpu->gic_pribits ?: 5; + } =20 - /* - * The GICv3 has separate ID register fields for virtual priority - * and preemption bit values, but only a single ID register field - * for the physical priority bits. The preemption bit count is - * always the same as the priority bit count, except that 8 bits - * of priority means 7 preemption bits. We precalculate the - * preemption bits because it simplifies the code and makes the - * parallels between the virtual and physical bits of the GIC - * a bit clearer. - */ - cs->prebits =3D cs->pribits; - if (cs->prebits =3D=3D 8) { - cs->prebits--; - } - /* - * Check that CPU code defining pribits didn't violate - * architectural constraints our implementation relies on. - */ - g_assert(cs->pribits >=3D 4 && cs->pribits <=3D 8); + /* + * The GICv3 has separate ID register fields for virtual priority + * and preemption bit values, but only a single ID register field + * for the physical priority bits. The preemption bit count is + * always the same as the priority bit count, except that 8 bits + * of priority means 7 preemption bits. We precalculate the + * preemption bits because it simplifies the code and makes the + * parallels between the virtual and physical bits of the GIC + * a bit clearer. + */ + gcs->prebits =3D gcs->pribits; + if (gcs->prebits =3D=3D 8) { + gcs->prebits--; + } + /* + * Check that CPU code defining pribits didn't violate + * architectural constraints our implementation relies on. + */ + g_assert(gcs->pribits >=3D 4 && gcs->pribits <=3D 8); =20 - /* - * gicv3_cpuif_reginfo[] defines ICC_AP*R0_EL1; add definitions - * for ICC_AP*R{1,2,3}_EL1 if the prebits value requires them. - */ - if (cs->prebits >=3D 6) { - define_arm_cp_regs(cpu, gicv3_cpuif_icc_apxr1_reginfo); - } - if (cs->prebits =3D=3D 7) { - define_arm_cp_regs(cpu, gicv3_cpuif_icc_apxr23_reginfo); - } + /* + * gicv3_cpuif_reginfo[] defines ICC_AP*R0_EL1; add definitions + * for ICC_AP*R{1,2,3}_EL1 if the prebits value requires them. + */ + if (gcs->prebits >=3D 6) { + define_arm_cp_regs(cpu, gicv3_cpuif_icc_apxr1_reginfo); + } + if (gcs->prebits =3D=3D 7) { + define_arm_cp_regs(cpu, gicv3_cpuif_icc_apxr23_reginfo); + } =20 - if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { - int j; + if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { + int j; =20 - cs->num_list_regs =3D cpu->gic_num_lrs ?: 4; - cs->vpribits =3D cpu->gic_vpribits ?: 5; - cs->vprebits =3D cpu->gic_vprebits ?: 5; + gcs->num_list_regs =3D cpu->gic_num_lrs ?: 4; + gcs->vpribits =3D cpu->gic_vpribits ?: 5; + gcs->vprebits =3D cpu->gic_vprebits ?: 5; =20 - /* Check against architectural constraints: getting these - * wrong would be a bug in the CPU code defining these, - * and the implementation relies on them holding. - */ - g_assert(cs->vprebits <=3D cs->vpribits); - g_assert(cs->vprebits >=3D 5 && cs->vprebits <=3D 7); - g_assert(cs->vpribits >=3D 5 && cs->vpribits <=3D 8); + /* Check against architectural constraints: getting these + * wrong would be a bug in the CPU code defining these, + * and the implementation relies on them holding. + */ + g_assert(gcs->vprebits <=3D gcs->vpribits); + g_assert(gcs->vprebits >=3D 5 && gcs->vprebits <=3D 7); + g_assert(gcs->vpribits >=3D 5 && gcs->vpribits <=3D 8); =20 - define_arm_cp_regs(cpu, gicv3_cpuif_hcr_reginfo); + define_arm_cp_regs(cpu, gicv3_cpuif_hcr_reginfo); =20 - for (j =3D 0; j < cs->num_list_regs; j++) { - /* Note that the AArch64 LRs are 64-bit; the AArch32 LRs - * are split into two cp15 regs, LR (the low part, with the - * same encoding as the AArch64 LR) and LRC (the high part= ). - */ - ARMCPRegInfo lr_regset[] =3D { - { .name =3D "ICH_LRn_EL2", .state =3D ARM_CP_STATE_BOT= H, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 12, - .crm =3D 12 + (j >> 3), .opc2 =3D j & 7, - .type =3D ARM_CP_IO | ARM_CP_NO_RAW, - .nv2_redirect_offset =3D 0x400 + 8 * j, - .access =3D PL2_RW, - .readfn =3D ich_lr_read, - .writefn =3D ich_lr_write, - }, - { .name =3D "ICH_LRCn_EL2", .state =3D ARM_CP_STATE_AA= 32, - .cp =3D 15, .opc1 =3D 4, .crn =3D 12, - .crm =3D 14 + (j >> 3), .opc2 =3D j & 7, - .type =3D ARM_CP_IO | ARM_CP_NO_RAW, - .access =3D PL2_RW, - .readfn =3D ich_lr_read, - .writefn =3D ich_lr_write, - }, - }; - define_arm_cp_regs(cpu, lr_regset); - } - if (cs->vprebits >=3D 6) { - define_arm_cp_regs(cpu, gicv3_cpuif_ich_apxr1_reginfo); - } - if (cs->vprebits =3D=3D 7) { - define_arm_cp_regs(cpu, gicv3_cpuif_ich_apxr23_reginfo); - } - } - if (tcg_enabled() || qtest_enabled()) { - /* - * We can only trap EL changes with TCG. However the GIC inter= rupt - * state only changes on EL changes involving EL2 or EL3, so f= or - * the non-TCG case this is OK, as EL2 and EL3 can't exist. + for (j =3D 0; j < gcs->num_list_regs; j++) { + /* Note that the AArch64 LRs are 64-bit; the AArch32 LRs + * are split into two cp15 regs, LR (the low part, with the + * same encoding as the AArch64 LR) and LRC (the high part). */ - arm_register_el_change_hook(cpu, gicv3_cpuif_el_change_hook, c= s); - } else { - assert(!arm_feature(&cpu->env, ARM_FEATURE_EL2)); - assert(!arm_feature(&cpu->env, ARM_FEATURE_EL3)); - } + ARMCPRegInfo lr_regset[] =3D { + { .name =3D "ICH_LRn_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 12, + .crm =3D 12 + (j >> 3), .opc2 =3D j & 7, + .type =3D ARM_CP_IO | ARM_CP_NO_RAW, + .nv2_redirect_offset =3D 0x400 + 8 * j, + .access =3D PL2_RW, + .readfn =3D ich_lr_read, + .writefn =3D ich_lr_write, + }, + { .name =3D "ICH_LRCn_EL2", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 4, .crn =3D 12, + .crm =3D 14 + (j >> 3), .opc2 =3D j & 7, + .type =3D ARM_CP_IO | ARM_CP_NO_RAW, + .access =3D PL2_RW, + .readfn =3D ich_lr_read, + .writefn =3D ich_lr_write, + }, + }; + define_arm_cp_regs(cpu, lr_regset); + } + if (gcs->vprebits >=3D 6) { + define_arm_cp_regs(cpu, gicv3_cpuif_ich_apxr1_reginfo); + } + if (gcs->vprebits =3D=3D 7) { + define_arm_cp_regs(cpu, gicv3_cpuif_ich_apxr23_reginfo); + } + } + if (tcg_enabled() || qtest_enabled()) { + /* + * We can only trap EL changes with TCG. However the GIC interrupt + * state only changes on EL changes involving EL2 or EL3, so for + * the non-TCG case this is OK, as EL2 and EL3 can't exist. + */ + arm_register_el_change_hook(cpu, gicv3_cpuif_el_change_hook, gcs); + } else { + assert(!arm_feature(&cpu->env, ARM_FEATURE_EL2)); + assert(!arm_feature(&cpu->env, ARM_FEATURE_EL3)); } } diff --git a/hw/intc/arm_gicv3_cpuif_common.c b/hw/intc/arm_gicv3_cpuif_com= mon.c index ff1239f65d..f9a9b2d8a3 100644 --- a/hw/intc/arm_gicv3_cpuif_common.c +++ b/hw/intc/arm_gicv3_cpuif_common.c @@ -20,3 +20,14 @@ void gicv3_set_gicv3state(CPUState *cpu, GICv3CPUState *= s) =20 env->gicv3state =3D (void *)s; }; + +void gicv3_init_cpuif(GICv3State *s) +{ + ARMGICv3CommonClass *agcc =3D ARM_GICV3_COMMON_GET_CLASS(s); + int i; + + /* define and register `system registers` with the vCPU */ + for (i =3D 0; i < s->num_cpu; i++) { + agcc->init_cpu_reginfo(s->cpu[i].cpu); + } +} diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c index 6166283cd1..4ca889da45 100644 --- a/hw/intc/arm_gicv3_kvm.c +++ b/hw/intc/arm_gicv3_kvm.c @@ -776,6 +776,10 @@ static void vm_change_state_handler(void *opaque, bool= running, } } =20 +static void kvm_gicv3_init_cpu_reginfo(CPUState *cs) +{ + define_arm_cp_regs(ARM_CPU(cs), gicv3_cpuif_reginfo); +} =20 static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp) { @@ -811,11 +815,8 @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Er= ror **errp) =20 gicv3_init_irqs_and_mmio(s, kvm_arm_gicv3_set_irq, NULL); =20 - for (i =3D 0; i < s->num_cpu; i++) { - ARMCPU *cpu =3D ARM_CPU(qemu_get_cpu(i)); - - define_arm_cp_regs(cpu, gicv3_cpuif_reginfo); - } + /* initialize vCPU interface */ + gicv3_init_cpuif(s); =20 /* Try to create the device via the device control API */ s->dev_fd =3D kvm_create_device(kvm_state, KVM_DEV_TYPE_ARM_VGIC_V3, f= alse); @@ -929,6 +930,7 @@ static void kvm_arm_gicv3_class_init(ObjectClass *klass= , const void *data) =20 agcc->pre_save =3D kvm_arm_gicv3_get; agcc->post_load =3D kvm_arm_gicv3_put; + agcc->init_cpu_reginfo =3D kvm_gicv3_init_cpu_reginfo; device_class_set_parent_realize(dc, kvm_arm_gicv3_realize, &kgc->parent_realize); resettable_class_set_parent_phases(rc, NULL, kvm_arm_gicv3_reset_hold,= NULL, diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h index bc9f518fe8..cc8edc499b 100644 --- a/hw/intc/gicv3_internal.h +++ b/hw/intc/gicv3_internal.h @@ -722,6 +722,7 @@ void gicv3_redist_vinvall(GICv3CPUState *cs, uint64_t v= ptaddr); =20 void gicv3_redist_send_sgi(GICv3CPUState *cs, int grp, int irq, bool ns); void gicv3_init_cpuif(GICv3State *s); +void gicv3_init_cpu_reginfo(CPUState *cs); =20 /** * gicv3_cpuif_update: diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3= _common.h index c18503869f..3720728227 100644 --- a/include/hw/intc/arm_gicv3_common.h +++ b/include/hw/intc/arm_gicv3_common.h @@ -313,6 +313,7 @@ struct ARMGICv3CommonClass { =20 void (*pre_save)(GICv3State *s); void (*post_load)(GICv3State *s); + void (*init_cpu_reginfo)(CPUState *cs); }; =20 void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler, --=20 2.34.1