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Tue, 30 Sep 2025 18:02:26 -0700 (PDT) From: salil.mehta@opnsrc.net To: qemu-devel@nongnu.org, qemu-arm@nongnu.org, mst@redhat.com Cc: salil.mehta@huawei.com, maz@kernel.org, jean-philippe@linaro.org, jonathan.cameron@huawei.com, lpieralisi@kernel.org, peter.maydell@linaro.org, richard.henderson@linaro.org, imammedo@redhat.com, armbru@redhat.com, andrew.jones@linux.dev, david@redhat.com, philmd@linaro.org, eric.auger@redhat.com, will@kernel.org, ardb@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, gshan@redhat.com, rafael@kernel.org, borntraeger@linux.ibm.com, alex.bennee@linaro.org, gustavo.romero@linaro.org, npiggin@gmail.com, harshpb@linux.ibm.com, linux@armlinux.org.uk, darren@os.amperecomputing.com, ilkka@os.amperecomputing.com, vishnu@os.amperecomputing.com, gankulkarni@os.amperecomputing.com, karl.heubaum@oracle.com, miguel.luis@oracle.com, salil.mehta@opnsrc.net, zhukeqian1@huawei.com, wangxiongfeng2@huawei.com, wangyanan55@huawei.com, wangzhou1@hisilicon.com, linuxarm@huawei.com, jiakernel2@gmail.com, maobibo@loongson.cn, lixianglai@loongson.cn, shahuang@redhat.com, zhao1.liu@intel.com Subject: [PATCH RFC V6 06/24] arm/virt, gicv3: Pre-size GIC with possible vCPUs at machine init Date: Wed, 1 Oct 2025 01:01:09 +0000 Message-Id: <20251001010127.3092631-7-salil.mehta@opnsrc.net> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251001010127.3092631-1-salil.mehta@opnsrc.net> References: <20251001010127.3092631-1-salil.mehta@opnsrc.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=salil.mehta@opnsrc.net; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1759281280884116600 From: Salil Mehta Pre-size the GIC with the maximum possible vCPUs during machine initializat= ion instead of the currently enabled CPU count. This ensures that the GIC is fu= lly provisioned for any vCPUs that may be enabled later by administrative or hot-add=E2=80=93like operations. Pre-sizing must also include redistributors for administratively disabled v= CPUs, ensuring the GIC is fully provisioned at initialization for all possible CP= Us. This is required because: 1. Memory regions and resources associated with GICC/GICR cannot be modified (added, deleted, or resized) after VM initialization. 2. The GICD_TYPER and related redistributor structures must be initialized = with correct mp_affinity and CPU interface numbering at creation time, and ca= nnot be altered later. 3. Avoids the need to dynamically resize GIC CPU interfaces, which is unsup= ported and would break architectural guarantees. This patch: - Replaces use of `ms->smp.cpus` with `ms->smp.max_cpus` for GIC sizing, redistributor allocation, and interrupt wiring. - Updates GICv3 realization to fetch CPU references via `machine_get_possible_cpu()` instead of `qemu_get_cpu()`, ensuring that = CPUs not yet realized but part of the possible set are accounted for. Co-developed-by: Keqian Zhu Signed-off-by: Keqian Zhu Signed-off-by: Salil Mehta --- hw/arm/virt.c | 24 ++++++++++++------------ hw/core/machine.c | 14 ++++++++++++++ hw/intc/arm_gicv3_common.c | 4 ++-- include/hw/arm/virt.h | 2 +- include/hw/boards.h | 12 ++++++++++++ 5 files changed, 41 insertions(+), 15 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index f4eeeacf6c..ee09aa19bd 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -793,7 +793,7 @@ static void create_gic(VirtMachineState *vms, MemoryReg= ion *mem) SysBusDevice *gicbusdev; const char *gictype; int i; - unsigned int smp_cpus =3D ms->smp.cpus; + unsigned int max_cpus =3D ms->smp.max_cpus; uint32_t nb_redist_regions =3D 0; int revision; =20 @@ -825,7 +825,7 @@ static void create_gic(VirtMachineState *vms, MemoryReg= ion *mem) =20 vms->gic =3D qdev_new(gictype); qdev_prop_set_uint32(vms->gic, "revision", revision); - qdev_prop_set_uint32(vms->gic, "num-cpu", smp_cpus); + qdev_prop_set_uint32(vms->gic, "num-cpu", max_cpus); /* Note that the num-irq property counts both internal and external * interrupts; there are always 32 of the former (mandated by GIC spec= ). */ @@ -837,7 +837,7 @@ static void create_gic(VirtMachineState *vms, MemoryReg= ion *mem) if (vms->gic_version !=3D VIRT_GIC_VERSION_2) { QList *redist_region_count; uint32_t redist0_capacity =3D virt_redist_capacity(vms, VIRT_GIC_R= EDIST); - uint32_t redist0_count =3D MIN(smp_cpus, redist0_capacity); + uint32_t redist0_count =3D MIN(max_cpus, redist0_capacity); =20 nb_redist_regions =3D virt_gicv3_redist_region_count(vms); =20 @@ -848,7 +848,7 @@ static void create_gic(VirtMachineState *vms, MemoryReg= ion *mem) virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2); =20 qlist_append_int(redist_region_count, - MIN(smp_cpus - redist0_count, redist1_capacity)); + MIN(max_cpus - redist0_count, redist1_capacity)); } qdev_prop_set_array(vms->gic, "redist-region-count", redist_region_count); @@ -896,8 +896,8 @@ static void create_gic(VirtMachineState *vms, MemoryReg= ion *mem) * and the GIC's IRQ/FIQ/VIRQ/VFIQ/NMI/VINMI interrupt outputs to the * CPU's inputs. */ - for (i =3D 0; i < smp_cpus; i++) { - DeviceState *cpudev =3D DEVICE(qemu_get_cpu(i)); + for (i =3D 0; i < max_cpus; i++) { + DeviceState *cpudev =3D DEVICE(machine_get_possible_cpu(i)); int intidbase =3D NUM_IRQS + i * GIC_INTERNAL; /* Mapping from the output timer irq lines from the CPU to the * GIC PPI inputs we use for the virt board. @@ -926,7 +926,7 @@ static void create_gic(VirtMachineState *vms, MemoryReg= ion *mem) } else if (vms->virt) { qemu_irq irq =3D qdev_get_gpio_in(vms->gic, intidbase + ARCH_GIC_MAINT_IRQ= ); - sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq); + sysbus_connect_irq(gicbusdev, i + 4 * max_cpus, irq); } =20 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, @@ -934,17 +934,17 @@ static void create_gic(VirtMachineState *vms, MemoryR= egion *mem) + VIRTUAL_PMU_IRQ)); =20 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_= IRQ)); - sysbus_connect_irq(gicbusdev, i + smp_cpus, + sysbus_connect_irq(gicbusdev, i + max_cpus, qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); - sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, + sysbus_connect_irq(gicbusdev, i + 2 * max_cpus, qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); - sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, + sysbus_connect_irq(gicbusdev, i + 3 * max_cpus, qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); =20 if (vms->gic_version !=3D VIRT_GIC_VERSION_2) { - sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, + sysbus_connect_irq(gicbusdev, i + 4 * max_cpus, qdev_get_gpio_in(cpudev, ARM_CPU_NMI)); - sysbus_connect_irq(gicbusdev, i + 5 * smp_cpus, + sysbus_connect_irq(gicbusdev, i + 5 * max_cpus, qdev_get_gpio_in(cpudev, ARM_CPU_VINMI)); } } diff --git a/hw/core/machine.c b/hw/core/machine.c index bd47527479..69d5632464 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -1369,6 +1369,20 @@ bool machine_require_guest_memfd(MachineState *machi= ne) return machine->cgs && machine->cgs->require_guest_memfd; } =20 +CPUState *machine_get_possible_cpu(int64_t cpu_index) +{ + MachineState *ms =3D MACHINE(qdev_get_machine()); + const CPUArchIdList *possible_cpus =3D ms->possible_cpus; + + for (int i =3D 0; i < possible_cpus->len; i++) { + if (possible_cpus->cpus[i].cpu && + possible_cpus->cpus[i].cpu->cpu_index =3D=3D cpu_index) { + return possible_cpus->cpus[i].cpu; + } + } + return NULL; +} + static char *cpu_slot_to_string(const CPUArchId *cpu) { GString *s =3D g_string_new(NULL); diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c index e438d8c042..f6a9f1c68b 100644 --- a/hw/intc/arm_gicv3_common.c +++ b/hw/intc/arm_gicv3_common.c @@ -32,7 +32,7 @@ #include "gicv3_internal.h" #include "hw/arm/linux-boot-if.h" #include "system/kvm.h" - +#include "hw/boards.h" =20 static void gicv3_gicd_no_migration_shift_bug_post_load(GICv3State *cs) { @@ -436,7 +436,7 @@ static void arm_gicv3_common_realize(DeviceState *dev, = Error **errp) s->cpu =3D g_new0(GICv3CPUState, s->num_cpu); =20 for (i =3D 0; i < s->num_cpu; i++) { - CPUState *cpu =3D qemu_get_cpu(i); + CPUState *cpu =3D machine_get_possible_cpu(i); uint64_t cpu_affid; =20 s->cpu[i].cpu =3D cpu; diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 683e4b965a..ace4154cc6 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -209,7 +209,7 @@ static inline int virt_gicv3_redist_region_count(VirtMa= chineState *vms) =20 assert(vms->gic_version !=3D VIRT_GIC_VERSION_2); =20 - return (MACHINE(vms)->smp.cpus > redist0_capacity && + return (MACHINE(vms)->smp.max_cpus > redist0_capacity && vms->highmem_redists) ? 2 : 1; } =20 diff --git a/include/hw/boards.h b/include/hw/boards.h index b27c2326a2..3ff77a8b3a 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -118,6 +118,18 @@ bool device_is_dynamic_sysbus(MachineClass *mc, Device= State *dev); MemoryRegion *machine_consume_memdev(MachineState *machine, HostMemoryBackend *backend); =20 +/** + * machine_get_possible_cpu: Gets 'CPUState' for the CPU with the given lo= gical + * cpu_index. The slot index in possible_cpus[] list is always sequential,= but + * 'cpu_index' values may not be sequential depending on machine implement= ation + * (e.g. with hotplug/unplug). Therefore, this function must scan the list= to + * find a match. + * @cpu_index: logical cpu index to search for 'CPUState' + * + * Returns: pointer to CPUState, or NULL if not found. + */ +CPUState *machine_get_possible_cpu(int64_t cpu_index); + /** * CPUArchId: * @arch_id - architecture-dependent CPU ID of present or possible CPU --=20 2.34.1