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Tue, 30 Sep 2025 18:02:22 -0700 (PDT) From: salil.mehta@opnsrc.net To: qemu-devel@nongnu.org, qemu-arm@nongnu.org, mst@redhat.com Cc: salil.mehta@huawei.com, maz@kernel.org, jean-philippe@linaro.org, jonathan.cameron@huawei.com, lpieralisi@kernel.org, peter.maydell@linaro.org, richard.henderson@linaro.org, imammedo@redhat.com, armbru@redhat.com, andrew.jones@linux.dev, david@redhat.com, philmd@linaro.org, eric.auger@redhat.com, will@kernel.org, ardb@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, gshan@redhat.com, rafael@kernel.org, borntraeger@linux.ibm.com, alex.bennee@linaro.org, gustavo.romero@linaro.org, npiggin@gmail.com, harshpb@linux.ibm.com, linux@armlinux.org.uk, darren@os.amperecomputing.com, ilkka@os.amperecomputing.com, vishnu@os.amperecomputing.com, gankulkarni@os.amperecomputing.com, karl.heubaum@oracle.com, miguel.luis@oracle.com, salil.mehta@opnsrc.net, zhukeqian1@huawei.com, wangxiongfeng2@huawei.com, wangyanan55@huawei.com, wangzhou1@hisilicon.com, linuxarm@huawei.com, jiakernel2@gmail.com, maobibo@loongson.cn, lixianglai@loongson.cn, shahuang@redhat.com, zhao1.liu@intel.com Subject: [PATCH RFC V6 04/24] arm/virt, target/arm: Add new ARMCPU {socket, cluster, core, thread}-id property Date: Wed, 1 Oct 2025 01:01:07 +0000 Message-Id: <20251001010127.3092631-5-salil.mehta@opnsrc.net> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251001010127.3092631-1-salil.mehta@opnsrc.net> References: <20251001010127.3092631-1-salil.mehta@opnsrc.net> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=salil.mehta@opnsrc.net; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1759280704574116600 Content-Type: text/plain; charset="utf-8" From: Salil Mehta Store the user-specified topology (socket/cluster/core/thread) and derive a unique 'vcpu-id'. The 'vcpu-id' is used as the slot index in the possible v= CPUs list when administratively enabling or disabling a vCPU. Co-developed-by: Keqian Zhu Signed-off-by: Keqian Zhu Signed-off-by: Salil Mehta Reviewed-by: Miguel Luis --- hw/arm/virt.c | 10 ++++++++++ include/hw/arm/virt.h | 36 ++++++++++++++++++++++++++++++++++++ target/arm/cpu.c | 4 ++++ target/arm/cpu.h | 4 ++++ 4 files changed, 54 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 76f21bd56a..4ded19dc69 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -2334,6 +2334,14 @@ static void machvirt_init(MachineState *machine) &error_fatal); =20 aarch64 &=3D object_property_get_bool(cpuobj, "aarch64", NULL); + object_property_set_int(cpuobj, "socket-id", virt_get_socket_id(n), + NULL); + object_property_set_int(cpuobj, "cluster-id", virt_get_cluster_id(= n), + NULL); + object_property_set_int(cpuobj, "core-id", virt_get_core_id(n), + NULL); + object_property_set_int(cpuobj, "thread-id", virt_get_thread_id(n), + NULL); =20 if (!vms->secure) { object_property_set_bool(cpuobj, "has_el3", false, NULL); @@ -2902,6 +2910,7 @@ static const CPUArchIdList *virt_possible_cpu_arch_id= s(MachineState *ms) { int n; unsigned int max_cpus =3D ms->smp.max_cpus; + unsigned int smp_threads =3D ms->smp.threads; VirtMachineState *vms =3D VIRT_MACHINE(ms); MachineClass *mc =3D MACHINE_GET_CLASS(vms); =20 @@ -2915,6 +2924,7 @@ static const CPUArchIdList *virt_possible_cpu_arch_id= s(MachineState *ms) ms->possible_cpus->len =3D max_cpus; for (n =3D 0; n < ms->possible_cpus->len; n++) { ms->possible_cpus->cpus[n].type =3D ms->cpu_type; + ms->possible_cpus->cpus[n].vcpus_count =3D smp_threads; ms->possible_cpus->cpus[n].arch_id =3D virt_cpu_mp_affinity(vms, n); =20 diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 365a28b082..683e4b965a 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -213,4 +213,40 @@ static inline int virt_gicv3_redist_region_count(VirtM= achineState *vms) vms->highmem_redists) ? 2 : 1; } =20 +static inline int virt_get_socket_id(int cpu_index) +{ + MachineState *ms =3D MACHINE(qdev_get_machine()); + + assert(cpu_index >=3D 0 && cpu_index < ms->possible_cpus->len); + + return ms->possible_cpus->cpus[cpu_index].props.socket_id; +} + +static inline int virt_get_cluster_id(int cpu_index) +{ + MachineState *ms =3D MACHINE(qdev_get_machine()); + + assert(cpu_index >=3D 0 && cpu_index < ms->possible_cpus->len); + + return ms->possible_cpus->cpus[cpu_index].props.cluster_id; +} + +static inline int virt_get_core_id(int cpu_index) +{ + MachineState *ms =3D MACHINE(qdev_get_machine()); + + assert(cpu_index >=3D 0 && cpu_index < ms->possible_cpus->len); + + return ms->possible_cpus->cpus[cpu_index].props.core_id; +} + +static inline int virt_get_thread_id(int cpu_index) +{ + MachineState *ms =3D MACHINE(qdev_get_machine()); + + assert(cpu_index >=3D 0 && cpu_index < ms->possible_cpus->len); + + return ms->possible_cpus->cpus[cpu_index].props.thread_id; +} + #endif /* QEMU_ARM_VIRT_H */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 0c9a2e7ea4..7e0d5b2ed8 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2607,6 +2607,10 @@ static const Property arm_cpu_properties[] =3D { DEFINE_PROP_UINT64("mp-affinity", ARMCPU, mp_affinity, ARM64_AFFINITY_INVALID), DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), + DEFINE_PROP_INT32("socket-id", ARMCPU, socket_id, 0), + DEFINE_PROP_INT32("cluster-id", ARMCPU, cluster_id, 0), + DEFINE_PROP_INT32("core-id", ARMCPU, core_id, 0), + DEFINE_PROP_INT32("thread-id", ARMCPU, thread_id, 0), DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1), /* True to default to the backward-compat old CNTFRQ rather than 1Ghz = */ DEFINE_PROP_BOOL("backcompat-cntfrq", ARMCPU, backcompat_cntfrq, false= ), diff --git a/target/arm/cpu.h b/target/arm/cpu.h index dc9b6dce4c..cd5982d362 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1126,6 +1126,10 @@ struct ArchCPU { QLIST_HEAD(, ARMELChangeHook) el_change_hooks; =20 int32_t node_id; /* NUMA node this CPU belongs to */ + int32_t socket_id; + int32_t cluster_id; + int32_t core_id; + int32_t thread_id; =20 /* Used to synchronize KVM and QEMU in-kernel device levels */ uint8_t device_irq_level; --=20 2.34.1