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Tue, 30 Sep 2025 18:02:38 -0700 (PDT) From: salil.mehta@opnsrc.net To: qemu-devel@nongnu.org, qemu-arm@nongnu.org, mst@redhat.com Cc: salil.mehta@huawei.com, maz@kernel.org, jean-philippe@linaro.org, jonathan.cameron@huawei.com, lpieralisi@kernel.org, peter.maydell@linaro.org, richard.henderson@linaro.org, imammedo@redhat.com, armbru@redhat.com, andrew.jones@linux.dev, david@redhat.com, philmd@linaro.org, eric.auger@redhat.com, will@kernel.org, ardb@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, gshan@redhat.com, rafael@kernel.org, borntraeger@linux.ibm.com, alex.bennee@linaro.org, gustavo.romero@linaro.org, npiggin@gmail.com, harshpb@linux.ibm.com, linux@armlinux.org.uk, darren@os.amperecomputing.com, ilkka@os.amperecomputing.com, vishnu@os.amperecomputing.com, gankulkarni@os.amperecomputing.com, karl.heubaum@oracle.com, miguel.luis@oracle.com, salil.mehta@opnsrc.net, zhukeqian1@huawei.com, wangxiongfeng2@huawei.com, wangyanan55@huawei.com, wangzhou1@hisilicon.com, linuxarm@huawei.com, jiakernel2@gmail.com, maobibo@loongson.cn, lixianglai@loongson.cn, shahuang@redhat.com, zhao1.liu@intel.com Subject: [PATCH RFC V6 11/24] hw/arm/acpi: MADT change to size the guest with possible vCPUs Date: Wed, 1 Oct 2025 01:01:14 +0000 Message-Id: <20251001010127.3092631-12-salil.mehta@opnsrc.net> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251001010127.3092631-1-salil.mehta@opnsrc.net> References: <20251001010127.3092631-1-salil.mehta@opnsrc.net> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=salil.mehta@opnsrc.net; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, T_SPF_HELO_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @opnsrc.net) X-ZM-MESSAGEID: 1759280805400116600 Content-Type: text/plain; charset="utf-8" From: Salil Mehta When QEMU builds the MADT table, modifications are needed to include inform= ation about possible vCPUs that are exposed as ACPI-disabled (i.e., `_STA.Enabled= =3D0`). This new information will help the guest kernel pre-size its resources duri= ng boot time. Pre-sizing based on possible vCPUs will facilitate the future hot-plugging of the currently disabled vCPUs. Additionally, this change addresses updates to the ACPI MADT GIC CPU interf= ace flags, as introduced in the UEFI ACPI 6.5 specification [1]. These updates enable deferred virtual CPU onlining in the guest kernel. Reference: [1] 5.2.12.14. GIC CPU Interface (GICC) Structure (Table 5.37 GICC CPU Inte= rface Flags) Link: https://uefi.org/specs/ACPI/6.5/05_ACPI_Software_Programming_Mode= l.html#gic-cpu-interface-gicc-structure Co-developed-by: Keqian Zhu Signed-off-by: Keqian Zhu Signed-off-by: Salil Mehta --- hw/arm/virt-acpi-build.c | 40 ++++++++++++++++++++++++++++++++++------ hw/core/machine.c | 14 ++++++++++++++ include/hw/boards.h | 20 ++++++++++++++++++++ 3 files changed, 68 insertions(+), 6 deletions(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index b01fc4f8ef..7c24dd6369 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -760,6 +760,32 @@ static void build_append_gicr(GArray *table_data, uint= 64_t base, uint32_t size) build_append_int_noprefix(table_data, size, 4); /* Discovery Range Len= gth */ } =20 +static uint32_t virt_acpi_get_gicc_flags(CPUState *cpu) +{ + MachineClass *mc =3D MACHINE_GET_CLASS(qdev_get_machine()); + const uint32_t GICC_FLAG_ENABLED =3D BIT(0); + const uint32_t GICC_FLAG_ONLINE_CAPABLE =3D BIT(3); + + /* ARM architecture does not support vCPU hotplug yet */ + if (!cpu) { + return 0; + } + + /* + * If the machine does not support online-capable CPUs, report the GIC= C as + * 'enabled' only. + */ + if (!mc->has_online_capable_cpus) { + return GICC_FLAG_ENABLED; + } + + /* + * ACPI 6.5, 5.2.12.14 (GICC): mark the boot CPU 'enabled' and all oth= ers + * 'online-capable'. + */ + return (cpu =3D=3D first_cpu) ? GICC_FLAG_ENABLED : GICC_FLAG_ONLINE_C= APABLE; +} + static void build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) { @@ -785,12 +811,14 @@ build_madt(GArray *table_data, BIOSLinker *linker, Vi= rtMachineState *vms) build_append_int_noprefix(table_data, vms->gic_version, 1); build_append_int_noprefix(table_data, 0, 3); /* Reserved */ =20 - for (i =3D 0; i < MACHINE(vms)->smp.cpus; i++) { - ARMCPU *armcpu =3D ARM_CPU(qemu_get_cpu(i)); + for (i =3D 0; i < MACHINE(vms)->smp.max_cpus; i++) { + CPUState *cpu =3D machine_get_possible_cpu(i); uint64_t physical_base_address =3D 0, gich =3D 0, gicv =3D 0; uint32_t vgic_interrupt =3D vms->virt ? ARCH_GIC_MAINT_IRQ : 0; - uint32_t pmu_interrupt =3D arm_feature(&armcpu->env, ARM_FEATURE_P= MU) ? - VIRTUAL_PMU_IRQ : 0; + uint32_t pmu_interrupt =3D vms->pmu ? VIRTUAL_PMU_IRQ : 0; + CPUArchId *archid =3D machine_get_possible_cpu_arch_id(i); + uint32_t flags =3D virt_acpi_get_gicc_flags(cpu); + uint64_t mpidr =3D archid->arch_id; =20 if (vms->gic_version =3D=3D VIRT_GIC_VERSION_2) { physical_base_address =3D memmap[VIRT_GIC_CPU].base; @@ -805,7 +833,7 @@ build_madt(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) build_append_int_noprefix(table_data, i, 4); /* GIC ID */ build_append_int_noprefix(table_data, i, 4); /* ACPI Processor = UID */ /* Flags */ - build_append_int_noprefix(table_data, 1, 4); /* Enabled */ + build_append_int_noprefix(table_data, flags, 4); /* Parking Protocol Version */ build_append_int_noprefix(table_data, 0, 4); /* Performance Interrupt GSIV */ @@ -819,7 +847,7 @@ build_madt(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) build_append_int_noprefix(table_data, vgic_interrupt, 4); build_append_int_noprefix(table_data, 0, 8); /* GICR Base Addre= ss*/ /* MPIDR */ - build_append_int_noprefix(table_data, arm_cpu_mp_affinity(armcpu),= 8); + build_append_int_noprefix(table_data, mpidr, 8); /* Processor Power Efficiency Class */ build_append_int_noprefix(table_data, 0, 1); /* Reserved */ diff --git a/hw/core/machine.c b/hw/core/machine.c index 69d5632464..65388d859a 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -1383,6 +1383,20 @@ CPUState *machine_get_possible_cpu(int64_t cpu_index) return NULL; } =20 +CPUArchId *machine_get_possible_cpu_arch_id(int64_t cpu_index) +{ + MachineState *ms =3D MACHINE(qdev_get_machine()); + CPUArchIdList *possible_cpus =3D ms->possible_cpus; + + for (int i =3D 0; i < possible_cpus->len; i++) { + if (possible_cpus->cpus[i].cpu && + possible_cpus->cpus[i].cpu->cpu_index =3D=3D cpu_index) { + return &possible_cpus->cpus[i]; + } + } + return NULL; +} + static char *cpu_slot_to_string(const CPUArchId *cpu) { GString *s =3D g_string_new(NULL); diff --git a/include/hw/boards.h b/include/hw/boards.h index 3ff77a8b3a..fe51ca58bf 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -461,6 +461,26 @@ struct MachineState { bool acpi_spcr_enabled; }; =20 +/* + * machine_get_possible_cpu_arch_id: + * @cpu_index: logical cpu_index to search for + * + * Return a pointer to the CPUArchId entry matching the given @cpu_index + * in the current machine's MachineState. The possible_cpus array holds + * the full set of CPUs that the machine could support, including those + * that may be created as disabled or taken offline. + * + * The slot index in ms->possible_cpus[] is always sequential, but the + * logical cpu_index values are assigned by QEMU and may or may not be + * sequential depending on the implementation of a particular machine. + * Direct indexing by cpu_index is therefore unsafe in general. This + * helper performs a linear search of the possible_cpus array to find + * the matching entry. + * + * Returns: pointer to the matching CPUArchId, or NULL if not found. + */ +CPUArchId *machine_get_possible_cpu_arch_id(int64_t cpu_index); + /* * The macros which follow are intended to facilitate the * definition of versioned machine types, using a somewhat --=20 2.34.1