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Tue, 30 Sep 2025 18:02:35 -0700 (PDT) From: salil.mehta@opnsrc.net To: qemu-devel@nongnu.org, qemu-arm@nongnu.org, mst@redhat.com Cc: salil.mehta@huawei.com, maz@kernel.org, jean-philippe@linaro.org, jonathan.cameron@huawei.com, lpieralisi@kernel.org, peter.maydell@linaro.org, richard.henderson@linaro.org, imammedo@redhat.com, armbru@redhat.com, andrew.jones@linux.dev, david@redhat.com, philmd@linaro.org, eric.auger@redhat.com, will@kernel.org, ardb@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, gshan@redhat.com, rafael@kernel.org, borntraeger@linux.ibm.com, alex.bennee@linaro.org, gustavo.romero@linaro.org, npiggin@gmail.com, harshpb@linux.ibm.com, linux@armlinux.org.uk, darren@os.amperecomputing.com, ilkka@os.amperecomputing.com, vishnu@os.amperecomputing.com, gankulkarni@os.amperecomputing.com, karl.heubaum@oracle.com, miguel.luis@oracle.com, salil.mehta@opnsrc.net, zhukeqian1@huawei.com, wangxiongfeng2@huawei.com, wangyanan55@huawei.com, wangzhou1@hisilicon.com, linuxarm@huawei.com, jiakernel2@gmail.com, maobibo@loongson.cn, lixianglai@loongson.cn, shahuang@redhat.com, zhao1.liu@intel.com Subject: [PATCH RFC V6 10/24] arm/virt: Init PMU at host for all present vCPUs Date: Wed, 1 Oct 2025 01:01:13 +0000 Message-Id: <20251001010127.3092631-11-salil.mehta@opnsrc.net> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251001010127.3092631-1-salil.mehta@opnsrc.net> References: <20251001010127.3092631-1-salil.mehta@opnsrc.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=salil.mehta@opnsrc.net; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @opnsrc.net) X-ZM-MESSAGEID: 1759281353763116600 From: Salil Mehta ARM architecture requires that all CPUs which form part of the VM must expose identical feature sets and consistent system components at creation time. This includes the Performance Monitoring Unit (PMU). If only the boot CPUs had their PMU state initialized, the remaining CPUs defined by `smp.disabled_cpus` would not match this architectural requirement, leading to inconsistencies and guest misbehavior. To comply with this constraint, PMU initialization must cover the entire set of present vCPUs: present =3D smp.cpus + smp.disabled_cpus CPUs outside this set (`smp.max_cpus - present`) are not considered part of the machine at creation and are therefore not initialized. Co-developed-by: Keqian Zhu Signed-off-by: Keqian Zhu Signed-off-by: Salil Mehta --- hw/arm/virt.c | 13 +++++++--- include/hw/arm/virt.h | 1 + include/hw/core/cpu.h | 57 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 67 insertions(+), 4 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index ee09aa19bd..3980f553db 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -2087,12 +2087,13 @@ static void finalize_gic_version(VirtMachineState *= vms) static void virt_post_cpus_gic_realized(VirtMachineState *vms, MemoryRegion *sysmem) { + CPUArchIdList *possible_cpus =3D vms->parent.possible_cpus; int max_cpus =3D MACHINE(vms)->smp.max_cpus; - bool aarch64, pmu, steal_time; + bool aarch64, steal_time; CPUState *cpu; =20 aarch64 =3D object_property_get_bool(OBJECT(first_cpu), "aarch64", NUL= L); - pmu =3D object_property_get_bool(OBJECT(first_cpu), "pmu", NULL); + vms->pmu =3D object_property_get_bool(OBJECT(first_cpu), "pmu", NULL); steal_time =3D object_property_get_bool(OBJECT(first_cpu), "kvm-steal-time", NULL); =20 @@ -2123,8 +2124,12 @@ static void virt_post_cpus_gic_realized(VirtMachineS= tate *vms, exit(1); } =20 - CPU_FOREACH(cpu) { - if (pmu) { + CPU_FOREACH_POSSIBLE(cpu, possible_cpus) { + if (!cpu) { + continue; + } + + if (vms->pmu) { assert(arm_feature(&ARM_CPU(cpu)->env, ARM_FEATURE_PMU)); if (kvm_irqchip_in_kernel()) { kvm_arm_pmu_set_irq(ARM_CPU(cpu), VIRTUAL_PMU_IRQ); diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index ace4154cc6..02cc311452 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -154,6 +154,7 @@ struct VirtMachineState { bool mte; bool dtb_randomness; bool second_ns_uart_present; + bool pmu; OnOffAuto acpi; VirtGICType gic_version; VirtIOMMUType iommu; diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 5eaf41a566..2ee202a8a5 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -602,6 +602,63 @@ extern CPUTailQ cpus_queue; #define CPU_FOREACH_SAFE(cpu, next_cpu) \ QTAILQ_FOREACH_SAFE_RCU(cpu, &cpus_queue, node, next_cpu) =20 + +/** + * CPU_FOREACH_POSSIBLE(cpu_, archid_list_) + * + * Iterate over all entries in a CPUArchIdList, assigning each entry=E2=80= =99s + * CPUState* to @cpu_. This hides the loop index and reads like a normal + * C for-loop. + * + * A CPUArchIdList represents the set of *possible* CPUs for a machine. + * Each entry contains: + * - @cpu: CPUState pointer, or NULL if not realized yet + * - @arch_id: architecture-specific identifier (e.g. MPIDR) + * - @vcpus_count: number of vCPUs represented (usually 1) + * + * The list models *possible* CPUs: it includes (a) currently plugged vCPUs + * made available through hotplug, (b) present (and perhaps visible to OSP= M) + * but kept ACPI-disabled vCPUs, and (c) reserved slots for CPUs that may = be + * created in the future. This supports co-existence of hotpluggable and + * admin-disabled vCPUs if architectures permit. + * + * Example: + * + * CPUArchIdList *alist =3D machine_possible_cpus(ms); + * CPUState *cpu; + * + * CPU_FOREACH_POSSIBLE(cpu, alist) { + * if (!cpu) { + * continue; // reserved slot for hotplug case + * } + * + * < Do Something > + * } + * + * Expanded equivalent: + * + * for (int __cpu_idx =3D 0; alist && __cpu_idx < alist->len; __cpu_idx+= +) { + * if ((cpu =3D alist->cpus[__cpu_idx].cpu, 1)) { + * if (!cpu) { + * continue; + * } + * + * < Do Something > + * } + * } + * + * Notes: + * - Callers must check @cpu for NULL when filtering unplugged CPUs. + * - Mirrors the style of CPU_FOREACH(), but iterates all *possible* CPUs + * (plugged, ACPI-disabled, and reserved slots) rather than only prese= nt + * and enabled vCPUs. + */ +#define CPU_FOREACH_POSSIBLE(cpu_, archid_list_) \ + for (int __cpu_idx =3D 0; \ + (archid_list_) && __cpu_idx < (archid_list_)->len; \ + __cpu_idx++) \ + if (((cpu_) =3D (archid_list_)->cpus[__cpu_idx].cpu, 1)) + extern __thread CPUState *current_cpu; =20 /** --=20 2.34.1