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Tue, 30 Sep 2025 18:02:33 -0700 (PDT) From: salil.mehta@opnsrc.net To: qemu-devel@nongnu.org, qemu-arm@nongnu.org, mst@redhat.com Cc: salil.mehta@huawei.com, maz@kernel.org, jean-philippe@linaro.org, jonathan.cameron@huawei.com, lpieralisi@kernel.org, peter.maydell@linaro.org, richard.henderson@linaro.org, imammedo@redhat.com, armbru@redhat.com, andrew.jones@linux.dev, david@redhat.com, philmd@linaro.org, eric.auger@redhat.com, will@kernel.org, ardb@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, gshan@redhat.com, rafael@kernel.org, borntraeger@linux.ibm.com, alex.bennee@linaro.org, gustavo.romero@linaro.org, npiggin@gmail.com, harshpb@linux.ibm.com, linux@armlinux.org.uk, darren@os.amperecomputing.com, ilkka@os.amperecomputing.com, vishnu@os.amperecomputing.com, gankulkarni@os.amperecomputing.com, karl.heubaum@oracle.com, miguel.luis@oracle.com, salil.mehta@opnsrc.net, zhukeqian1@huawei.com, wangxiongfeng2@huawei.com, wangyanan55@huawei.com, wangzhou1@hisilicon.com, linuxarm@huawei.com, jiakernel2@gmail.com, maobibo@loongson.cn, lixianglai@loongson.cn, shahuang@redhat.com, zhao1.liu@intel.com Subject: [PATCH RFC V6 09/24] hw/intc/arm_gicv3_common: Migrate & check 'GICv3CPUState' accessibility mismatch Date: Wed, 1 Oct 2025 01:01:12 +0000 Message-Id: <20251001010127.3092631-10-salil.mehta@opnsrc.net> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251001010127.3092631-1-salil.mehta@opnsrc.net> References: <20251001010127.3092631-1-salil.mehta@opnsrc.net> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=salil.mehta@opnsrc.net; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, T_SPF_HELO_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @opnsrc.net) X-ZM-MESSAGEID: 1759281382084116600 Content-Type: text/plain; charset="utf-8" From: Salil Mehta At the source, administratively disabled vCPUs may lack a CPU VMSD: either = they were never realized (never enabled once), or they were realized and later disabled, causing the VMSD to be unregistered. Such vCPUs are not migrated = as CPU devices. However, the GICv3CpuState for all vCPUs is still migrated to = the destination VM and must be checked for mismatches in their CPU interface accessibility. To preserve correctness, migrate the per-vCPU `gicc_accessible` bit as part= of the GICv3 device state, and fail migration on load if a mismatch is detecte= d. Administrators must ensure that the number of possible vCPUs and the number= of administratively disabled vCPUs remain consistent across hosts. Changes: - Add `VMSTATE_BOOL(gicc_accessible)` to the per-vCPU GICv3 state. - Add `post_load` hook that checks for mismatch in disabled vCPUs by verif= ying GIC CPU interface accessibility. Signed-off-by: Salil Mehta --- hw/core/qdev.c | 17 +++++++++++++++++ hw/intc/arm_gicv3_common.c | 37 +++++++++++++++++++++++++++++++++++++ include/hw/qdev-core.h | 15 +++++++++++++++ 3 files changed, 69 insertions(+) diff --git a/hw/core/qdev.c b/hw/core/qdev.c index 8e9a4da6b5..23b84a7756 100644 --- a/hw/core/qdev.c +++ b/hw/core/qdev.c @@ -326,6 +326,23 @@ bool qdev_disable(DeviceState *dev, BusState *bus, Err= or **errp) errp); } =20 +bool qdev_enable(DeviceState *dev, BusState *bus, Error **errp) +{ + g_assert(dev); + + if (bus) { + error_setg(errp, "Device %s does not supports 'enable' operation", + object_get_typename(OBJECT(dev))); + return false; + } + + /* devices like cpu don't have bus */ + g_assert(!DEVICE_GET_CLASS(dev)->bus_type); + + return object_property_set_str(OBJECT(dev), "admin_power_state", "enab= led", + errp); +} + int qdev_get_admin_power_state(DeviceState *dev) { DeviceClass *dc; diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c index f4428ad165..9139352330 100644 --- a/hw/intc/arm_gicv3_common.c +++ b/hw/intc/arm_gicv3_common.c @@ -84,6 +84,15 @@ static int gicv3_post_load(void *opaque, int version_id) { GICv3State *s =3D (GICv3State *)opaque; ARMGICv3CommonClass *c =3D ARM_GICV3_COMMON_GET_CLASS(s); + MachineState *ms =3D MACHINE(qdev_get_machine()); + + /* ensure source and destination VM 'maxcpu' count matches */ + if (s->num_cpu !=3D ms->smp.max_cpus) { + error_report("GICv3: source num_cpu(%u) !=3D dest maxcpus(%u). " + "Launch dest with -smp maxcpus=3D%u", + s->num_cpu, ms->smp.max_cpus, s->num_cpu); + return -1; + } =20 gicv3_gicd_no_migration_shift_bug_post_load(s); =20 @@ -127,6 +136,32 @@ static int vmstate_gicv3_cpu_pre_load(void *opaque) return 0; } =20 +static int vmstate_gicv3_cpu_post_load(void *opaque, int version_id) +{ + bool src_enabled, dst_enabled; + GICv3CPUState *gcs =3D opaque; + CPUState *cs =3D gcs->cpu; + + if (!cs) { + return 0; + } + + /* we derive the source vCPU admin state via GIC CPU Interface */ + src_enabled =3D gicv3_gicc_accessible(OBJECT(gcs->gic), cs->cpu_index); + dst_enabled =3D qdev_check_enabled(DEVICE(cs)); + + if (dst_enabled !=3D src_enabled) { + error_report("GICv3: CPU %d admin-state mismatch: dst=3D%s, src=3D= %s;" + " Aborting!", cs->cpu_index, + dst_enabled ? "enabled" : "disabled", + src_enabled ? "enabled" : "disabled"); + + return -1; + } + + return 0; +} + static bool icc_sre_el1_reg_needed(void *opaque) { GICv3CPUState *cs =3D opaque; @@ -187,6 +222,7 @@ static const VMStateDescription vmstate_gicv3_cpu =3D { .version_id =3D 1, .minimum_version_id =3D 1, .pre_load =3D vmstate_gicv3_cpu_pre_load, + .post_load =3D vmstate_gicv3_cpu_post_load, .fields =3D (const VMStateField[]) { VMSTATE_UINT32(level, GICv3CPUState), VMSTATE_UINT32(gicr_ctlr, GICv3CPUState), @@ -208,6 +244,7 @@ static const VMStateDescription vmstate_gicv3_cpu =3D { VMSTATE_UINT64_2DARRAY(icc_apr, GICv3CPUState, 3, 4), VMSTATE_UINT64_ARRAY(icc_igrpen, GICv3CPUState, 3), VMSTATE_UINT64(icc_ctlr_el3, GICv3CPUState), + VMSTATE_BOOL(gicc_accessible, GICv3CPUState), VMSTATE_END_OF_LIST() }, .subsections =3D (const VMStateDescription * const []) { diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h index b1d3fa4a25..855ff865ba 100644 --- a/include/hw/qdev-core.h +++ b/include/hw/qdev-core.h @@ -589,6 +589,21 @@ bool qdev_realize_and_unref(DeviceState *dev, BusState= *bus, Error **errp); */ bool qdev_disable(DeviceState *dev, BusState *bus, Error **errp); =20 +/** + * qdev_enable - Power on and administratively enable a device + * @dev: The device to be powered on and administratively enabled + * @bus: The bus on which the device is connected (may be NULL for CPUs) + * @errp: Pointer to a location where an error can be reported + * + * This function performs both administrative and operational power-on of + * the specified device. It transitions the device into ENABLED state and + * restores runtime availability. If applicable, the device is also re-add= ed + * to the migration stream. + * + * Returns true if the operation succeeds; false otherwise, with @errp set. + */ +bool qdev_enable(DeviceState *dev, BusState *bus, Error **errp); + /** * qdev_check_enabled - Check if a device is administratively enabled * @dev: The device to check --=20 2.34.1