From nobody Fri Nov 14 23:31:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1759204564759595.724738109858; Mon, 29 Sep 2025 20:56:04 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v3RQy-0000ur-Je; Mon, 29 Sep 2025 23:53:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v3RQw-0000uS-Cn for qemu-devel@nongnu.org; Mon, 29 Sep 2025 23:53:46 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v3RQq-0001pc-Vt for qemu-devel@nongnu.org; Mon, 29 Sep 2025 23:53:45 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8CxHvA+VNtoumsQAA--.34595S3; Tue, 30 Sep 2025 11:53:34 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJBxC8E8VNtoak+_AA--.40492S3; Tue, 30 Sep 2025 11:53:33 +0800 (CST) From: Bibo Mao To: Song Gao , Richard Henderson Cc: Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH v4 01/13] target/loongarch: Use auto method with PTW feature Date: Tue, 30 Sep 2025 11:53:20 +0800 Message-Id: <20250930035332.2609520-2-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250930035332.2609520-1-maobibo@loongson.cn> References: <20250930035332.2609520-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJBxC8E8VNtoak+_AA--.40492S3 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1759204566357116600 Content-Type: text/plain; charset="utf-8" PTW is short for page table walker, it is hardware page table walker function. With PTW supported, hardware MMU will parse page table table and update TLB entries automatically. This patch adds type OnOffAuto for PTW feature setting. Signed-off-by: Bibo Mao --- target/loongarch/cpu.c | 25 +++++++++++++++++++++++++ target/loongarch/cpu.h | 2 ++ 2 files changed, 27 insertions(+) diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 993602fb8c..c71e879791 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -514,6 +514,24 @@ static void loongarch_set_msgint(Object *obj, bool val= ue, Error **errp) cpu->env.cpucfg[1] =3D FIELD_DP32(cpu->env.cpucfg[1], CPUCFG1, MSG_IN= T, value); } =20 +static bool loongarch_get_ptw(Object *obj, Error **errp) +{ + return LOONGARCH_CPU(obj)->ptw !=3D ON_OFF_AUTO_OFF; +} + +static void loongarch_set_ptw(Object *obj, bool value, Error **errp) +{ + LoongArchCPU *cpu =3D LOONGARCH_CPU(obj); + + if (kvm_enabled()) { + /* PTW feature is only support in TCG mode now */ + return; + } + + cpu->ptw =3D value ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF; + cpu->env.cpucfg[2] =3D FIELD_DP32(cpu->env.cpucfg[2], CPUCFG2, HPTW, v= alue); +} + static void loongarch_cpu_post_init(Object *obj) { LoongArchCPU *cpu =3D LOONGARCH_CPU(obj); @@ -528,7 +546,10 @@ static void loongarch_cpu_post_init(Object *obj) loongarch_set_lasx); object_property_add_bool(obj, "msgint", loongarch_get_msgint, loongarch_set_msgint); + object_property_add_bool(obj, "ptw", loongarch_get_ptw, + loongarch_set_ptw); /* lbt is enabled only in kvm mode, not supported in tcg mode */ + if (kvm_enabled()) { kvm_loongarch_cpu_post_init(cpu); } @@ -636,6 +657,7 @@ static void loongarch_la464_initfn(Object *obj) env->CSR_PRCFG3 =3D FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_SETS,= 8); =20 cpu->msgint =3D ON_OFF_AUTO_OFF; + cpu->ptw =3D ON_OFF_AUTO_OFF; loongarch_la464_init_csr(obj); loongarch_cpu_post_init(obj); } @@ -667,6 +689,7 @@ static void loongarch_la132_initfn(Object *obj) data =3D FIELD_DP32(data, CPUCFG1, CRC, 1); env->cpucfg[1] =3D data; cpu->msgint =3D ON_OFF_AUTO_OFF; + cpu->ptw =3D ON_OFF_AUTO_OFF; } =20 static void loongarch_max_initfn(Object *obj) @@ -678,6 +701,8 @@ static void loongarch_max_initfn(Object *obj) if (tcg_enabled()) { cpu->env.cpucfg[1] =3D FIELD_DP32(cpu->env.cpucfg[1], CPUCFG1, MSG= _INT, 1); cpu->msgint =3D ON_OFF_AUTO_AUTO; + cpu->env.cpucfg[2] =3D FIELD_DP32(cpu->env.cpucfg[2], CPUCFG2, HPT= W, 1); + cpu->ptw =3D ON_OFF_AUTO_AUTO; } } =20 diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index b8e3b46c3a..b1d6799222 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -137,6 +137,7 @@ FIELD(CPUCFG2, LBT_MIPS, 20, 1) FIELD(CPUCFG2, LBT_ALL, 18, 3) FIELD(CPUCFG2, LSPW, 21, 1) FIELD(CPUCFG2, LAM, 22, 1) +FIELD(CPUCFG2, HPTW, 24, 1) =20 /* cpucfg[3] bits */ FIELD(CPUCFG3, CCDMA, 0, 1) @@ -402,6 +403,7 @@ struct ArchCPU { uint32_t phy_id; OnOffAuto lbt; OnOffAuto pmu; + OnOffAuto ptw; OnOffAuto lsx; OnOffAuto lasx; OnOffAuto msgint; --=20 2.39.3 From nobody Fri Nov 14 23:31:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1759204531942407.21205553377445; Mon, 29 Sep 2025 20:55:31 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v3RQy-0000uR-DP; Mon, 29 Sep 2025 23:53:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v3RQu-0000u5-SV for qemu-devel@nongnu.org; Mon, 29 Sep 2025 23:53:44 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v3RQq-0001pY-Vd for qemu-devel@nongnu.org; Mon, 29 Sep 2025 23:53:44 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8AxztI+VNtovGsQAA--.34338S3; Tue, 30 Sep 2025 11:53:34 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJBxC8E8VNtoak+_AA--.40492S4; Tue, 30 Sep 2025 11:53:34 +0800 (CST) From: Bibo Mao To: Song Gao , Richard Henderson Cc: Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH v4 02/13] target/loongarch: Add CSR_PWCH write helper function Date: Tue, 30 Sep 2025 11:53:21 +0800 Message-Id: <20250930035332.2609520-3-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250930035332.2609520-1-maobibo@loongson.cn> References: <20250930035332.2609520-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJBxC8E8VNtoak+_AA--.40492S4 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1759204534797116601 Content-Type: text/plain; charset="utf-8" Bit HPTW_EN in register CSR_PWCH controls enabling hardware page table walker feature when PTW feature is enabled. Otherwise it is reserved bit. Here add register CSR_PWCH write helper function. Signed-off-by: Bibo Mao --- target/loongarch/cpu-csr.h | 2 ++ target/loongarch/tcg/csr_helper.c | 15 +++++++++++++++ target/loongarch/tcg/helper.h | 1 + .../tcg/insn_trans/trans_privileged.c.inc | 1 + 4 files changed, 19 insertions(+) diff --git a/target/loongarch/cpu-csr.h b/target/loongarch/cpu-csr.h index 9097fddee1..0bcb51d3a3 100644 --- a/target/loongarch/cpu-csr.h +++ b/target/loongarch/cpu-csr.h @@ -105,6 +105,8 @@ FIELD(CSR_PWCH, DIR3_BASE, 0, 6) FIELD(CSR_PWCH, DIR3_WIDTH, 6, 6) FIELD(CSR_PWCH, DIR4_BASE, 12, 6) FIELD(CSR_PWCH, DIR4_WIDTH, 18, 6) +FIELD(CSR_PWCH, HPTW_EN, 24, 1) +FIELD(CSR_PWCH, RESERVE, 25, 7) =20 #define LOONGARCH_CSR_STLBPS 0x1e /* Stlb page size */ FIELD(CSR_STLBPS, PS, 0, 5) diff --git a/target/loongarch/tcg/csr_helper.c b/target/loongarch/tcg/csr_h= elper.c index 5ebe15f993..c1a8ba3089 100644 --- a/target/loongarch/tcg/csr_helper.c +++ b/target/loongarch/tcg/csr_helper.c @@ -163,3 +163,18 @@ target_ulong helper_csrwr_pwcl(CPULoongArchState *env,= target_ulong val) env->CSR_PWCL =3D val; return old_v; } + +target_ulong helper_csrwr_pwch(CPULoongArchState *env, target_ulong val) +{ + uint8_t has_ptw; + int64_t old_v =3D env->CSR_PWCH; + + val =3D FIELD_DP64(val, CSR_PWCH, RESERVE, 0); + has_ptw =3D FIELD_EX32(env->cpucfg[2], CPUCFG2, HPTW); + if (!has_ptw) { + val =3D FIELD_DP64(val, CSR_PWCH, HPTW_EN, 0); + } + + env->CSR_PWCH =3D val; + return old_v; + } diff --git a/target/loongarch/tcg/helper.h b/target/loongarch/tcg/helper.h index db57dbfc16..f1f690b880 100644 --- a/target/loongarch/tcg/helper.h +++ b/target/loongarch/tcg/helper.h @@ -107,6 +107,7 @@ DEF_HELPER_2(csrwr_asid, i64, env, tl) DEF_HELPER_2(csrwr_tcfg, i64, env, tl) DEF_HELPER_2(csrwr_ticlr, i64, env, tl) DEF_HELPER_2(csrwr_pwcl, i64, env, tl) +DEF_HELPER_2(csrwr_pwch, i64, env, tl) DEF_HELPER_2(iocsrrd_b, i64, env, tl) DEF_HELPER_2(iocsrrd_h, i64, env, tl) DEF_HELPER_2(iocsrrd_w, i64, env, tl) diff --git a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc b/targe= t/loongarch/tcg/insn_trans/trans_privileged.c.inc index a407ab51b7..c96390267c 100644 --- a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc +++ b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc @@ -79,6 +79,7 @@ void loongarch_csr_translate_init(void) SET_CSR_FUNC(ASID, NULL, gen_helper_csrwr_asid); SET_CSR_FUNC(PGD, gen_helper_csrrd_pgd, NULL); SET_CSR_FUNC(PWCL, NULL, gen_helper_csrwr_pwcl); + SET_CSR_FUNC(PWCH, NULL, gen_helper_csrwr_pwch); SET_CSR_FUNC(CPUID, gen_helper_csrrd_cpuid, NULL); SET_CSR_FUNC(TCFG, NULL, gen_helper_csrwr_tcfg); SET_CSR_FUNC(TVAL, gen_helper_csrrd_tval, NULL); --=20 2.39.3 From nobody Fri Nov 14 23:31:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1759204574259753.7003451341028; Mon, 29 Sep 2025 20:56:14 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v3RR2-0000wi-C9; Mon, 29 Sep 2025 23:53:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v3RR0-0000vq-8t for qemu-devel@nongnu.org; Mon, 29 Sep 2025 23:53:50 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v3RQs-0001pb-1P for qemu-devel@nongnu.org; Mon, 29 Sep 2025 23:53:50 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8Dx_78+VNtowWsQAA--.34087S3; Tue, 30 Sep 2025 11:53:34 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJBxC8E8VNtoak+_AA--.40492S5; Tue, 30 Sep 2025 11:53:34 +0800 (CST) From: Bibo Mao To: Song Gao , Richard Henderson Cc: Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH v4 03/13] target/loongarch: Add present and write bit with pte entry Date: Tue, 30 Sep 2025 11:53:22 +0800 Message-Id: <20250930035332.2609520-4-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250930035332.2609520-1-maobibo@loongson.cn> References: <20250930035332.2609520-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJBxC8E8VNtoak+_AA--.40492S5 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1759204576283116600 Content-Type: text/plain; charset="utf-8" With hardware PTW feature enabled, Present bit and Write bit is checked by hardware, rather Valid bit and Dirty bit. Bit P means that the page is valid and present, and bit W means that the page is writable. The original V bit is treated as access bit, hardware sets this bit if there is a read or write access. Bit D bit is updated by hardware if there is a write access. Signed-off-by: Bibo Mao --- target/loongarch/cpu-csr.h | 2 ++ target/loongarch/cpu-mmu.h | 31 +++++++++++++++++++++++++++++++ target/loongarch/cpu_helper.c | 7 ++++--- target/loongarch/tcg/tlb_helper.c | 16 ++++++++-------- 4 files changed, 45 insertions(+), 11 deletions(-) diff --git a/target/loongarch/cpu-csr.h b/target/loongarch/cpu-csr.h index 0bcb51d3a3..6898947498 100644 --- a/target/loongarch/cpu-csr.h +++ b/target/loongarch/cpu-csr.h @@ -70,6 +70,8 @@ FIELD(TLBENTRY, PLV, 2, 2) FIELD(TLBENTRY, MAT, 4, 2) FIELD(TLBENTRY, G, 6, 1) FIELD(TLBENTRY, HUGE, 6, 1) +FIELD(TLBENTRY, P, 7, 1) +FIELD(TLBENTRY, W, 8, 1) FIELD(TLBENTRY, HGLOBAL, 12, 1) FIELD(TLBENTRY, LEVEL, 13, 2) FIELD(TLBENTRY_32, PPN, 8, 24) diff --git a/target/loongarch/cpu-mmu.h b/target/loongarch/cpu-mmu.h index 0068d22efc..bc3700f93d 100644 --- a/target/loongarch/cpu-mmu.h +++ b/target/loongarch/cpu-mmu.h @@ -27,6 +27,37 @@ typedef struct MMUContext { int prot; } MMUContext; =20 +static inline bool cpu_has_ptw(CPULoongArchState *env) +{ + return !!FIELD_EX64(env->CSR_PWCH, CSR_PWCH, HPTW_EN); +} + +static inline bool pte_present(CPULoongArchState *env, uint64_t entry) +{ + uint8_t present; + + if (cpu_has_ptw(env)) { + present =3D FIELD_EX64(entry, TLBENTRY, P); + } else { + present =3D FIELD_EX64(entry, TLBENTRY, V); + } + + return !!present; +} + +static inline bool pte_write(CPULoongArchState *env, uint64_t entry) +{ + uint8_t writable; + + if (cpu_has_ptw(env)) { + writable =3D FIELD_EX64(entry, TLBENTRY, W); + } else { + writable =3D FIELD_EX64(entry, TLBENTRY, D); + } + + return !!writable; +} + bool check_ps(CPULoongArchState *ent, uint8_t ps); TLBRet loongarch_check_pte(CPULoongArchState *env, MMUContext *context, MMUAccessType access_type, int mmu_idx); diff --git a/target/loongarch/cpu_helper.c b/target/loongarch/cpu_helper.c index 4a9db3ea4c..05e7fd6f3f 100644 --- a/target/loongarch/cpu_helper.c +++ b/target/loongarch/cpu_helper.c @@ -49,12 +49,13 @@ TLBRet loongarch_check_pte(CPULoongArchState *env, MMUC= ontext *context, { uint64_t plv =3D mmu_idx; uint64_t tlb_entry, tlb_ppn; - uint8_t tlb_ps, tlb_v, tlb_d, tlb_plv, tlb_nx, tlb_nr, tlb_rplv; + uint8_t tlb_ps, tlb_plv, tlb_nx, tlb_nr, tlb_rplv; + bool tlb_v, tlb_d; =20 tlb_entry =3D context->pte; tlb_ps =3D context->ps; - tlb_v =3D FIELD_EX64(tlb_entry, TLBENTRY, V); - tlb_d =3D FIELD_EX64(tlb_entry, TLBENTRY, D); + tlb_v =3D pte_present(env, tlb_entry); + tlb_d =3D pte_write(env, tlb_entry); tlb_plv =3D FIELD_EX64(tlb_entry, TLBENTRY, PLV); if (is_la64(env)) { tlb_ppn =3D FIELD_EX64(tlb_entry, TLBENTRY_64, PPN); diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_h= elper.c index 8cfce48a29..b1092d3aff 100644 --- a/target/loongarch/tcg/tlb_helper.c +++ b/target/loongarch/tcg/tlb_helper.c @@ -114,10 +114,9 @@ static void invalidate_tlb_entry(CPULoongArchState *en= v, int index) uint8_t tlb_ps; LoongArchTLB *tlb =3D &env->tlb[index]; int idxmap =3D BIT(MMU_KERNEL_IDX) | BIT(MMU_USER_IDX); - uint8_t tlb_v0 =3D FIELD_EX64(tlb->tlb_entry0, TLBENTRY, V); - uint8_t tlb_v1 =3D FIELD_EX64(tlb->tlb_entry1, TLBENTRY, V); uint64_t tlb_vppn =3D FIELD_EX64(tlb->tlb_misc, TLB_MISC, VPPN); uint8_t tlb_e =3D FIELD_EX64(tlb->tlb_misc, TLB_MISC, E); + bool tlb_v; =20 if (!tlb_e) { return; @@ -130,12 +129,14 @@ static void invalidate_tlb_entry(CPULoongArchState *e= nv, int index) addr =3D (tlb_vppn << R_TLB_MISC_VPPN_SHIFT) & ~mask; addr =3D sextract64(addr, 0, TARGET_VIRT_ADDR_SPACE_BITS); =20 - if (tlb_v0) { + tlb_v =3D pte_present(env, tlb->tlb_entry0); + if (tlb_v) { tlb_flush_range_by_mmuidx(env_cpu(env), addr, pagesize, idxmap, TARGET_LONG_BITS); } =20 - if (tlb_v1) { + tlb_v =3D pte_present(env, tlb->tlb_entry1); + if (tlb_v) { tlb_flush_range_by_mmuidx(env_cpu(env), addr + pagesize, pagesize, idxmap, TARGET_LONG_BITS); } @@ -333,8 +334,7 @@ void helper_tlbwr(CPULoongArchState *env) { int index =3D FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, INDEX); LoongArchTLB *old, new =3D {}; - bool skip_inv =3D false; - uint8_t tlb_v0, tlb_v1; + bool skip_inv =3D false, tlb_v0, tlb_v1; =20 old =3D env->tlb + index; if (FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, NE)) { @@ -346,8 +346,8 @@ void helper_tlbwr(CPULoongArchState *env) /* Check whether ASID/VPPN is the same */ if (old->tlb_misc =3D=3D new.tlb_misc) { /* Check whether both even/odd pages is the same or invalid */ - tlb_v0 =3D FIELD_EX64(old->tlb_entry0, TLBENTRY, V); - tlb_v1 =3D FIELD_EX64(old->tlb_entry1, TLBENTRY, V); + tlb_v0 =3D pte_present(env, old->tlb_entry0); + tlb_v1 =3D pte_present(env, old->tlb_entry1); if ((!tlb_v0 || new.tlb_entry0 =3D=3D old->tlb_entry0) && (!tlb_v1 || new.tlb_entry1 =3D=3D old->tlb_entry1)) { skip_inv =3D true; --=20 2.39.3 From nobody Fri Nov 14 23:31:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 175920461937863.86735985439975; Mon, 29 Sep 2025 20:56:59 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v3RR2-0000wk-RT; Mon, 29 Sep 2025 23:53:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v3RR0-0000w0-Qi for qemu-devel@nongnu.org; Mon, 29 Sep 2025 23:53:50 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v3RQr-0001ql-4S for qemu-devel@nongnu.org; Mon, 29 Sep 2025 23:53:50 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8Bx3tI_VNtoxGsQAA--.34469S3; Tue, 30 Sep 2025 11:53:35 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJBxC8E8VNtoak+_AA--.40492S6; Tue, 30 Sep 2025 11:53:34 +0800 (CST) From: Bibo Mao To: Song Gao , Richard Henderson Cc: Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH v4 04/13] target/loongarch: Add function sptw_prepare_tlb before adding tlb entry Date: Tue, 30 Sep 2025 11:53:23 +0800 Message-Id: <20250930035332.2609520-5-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250930035332.2609520-1-maobibo@loongson.cn> References: <20250930035332.2609520-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJBxC8E8VNtoak+_AA--.40492S6 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1759204620752116600 Content-Type: text/plain; charset="utf-8" With software page table walker, tlb entry comes from CSR registers. however with hardware page table walker, tlb entry comes from page table entry information directly, TLB CSR registers are not necessary. Here add function sptw_prepare_context(), get tlb entry information from TLB CSR registers. Signed-off-by: Bibo Mao --- target/loongarch/cpu-mmu.h | 1 + target/loongarch/tcg/tlb_helper.c | 23 +++++++++++++++++++++-- 2 files changed, 22 insertions(+), 2 deletions(-) diff --git a/target/loongarch/cpu-mmu.h b/target/loongarch/cpu-mmu.h index bc3700f93d..865800fc0a 100644 --- a/target/loongarch/cpu-mmu.h +++ b/target/loongarch/cpu-mmu.h @@ -25,6 +25,7 @@ typedef struct MMUContext { hwaddr physical; int ps; /* page size shift */ int prot; + uint64_t pte_buddy[2]; } MMUContext; =20 static inline bool cpu_has_ptw(CPULoongArchState *env) diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_h= elper.c index b1092d3aff..01ade068ab 100644 --- a/target/loongarch/tcg/tlb_helper.c +++ b/target/loongarch/tcg/tlb_helper.c @@ -157,10 +157,10 @@ static void invalidate_tlb(CPULoongArchState *env, in= t index) invalidate_tlb_entry(env, index); } =20 -static void fill_tlb_entry(CPULoongArchState *env, LoongArchTLB *tlb) +/* Prepare tlb entry information in software PTW mode */ +static void sptw_prepare_context(CPULoongArchState *env, MMUContext *conte= xt) { uint64_t lo0, lo1, csr_vppn; - uint16_t csr_asid; uint8_t csr_ps; =20 if (FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR)) { @@ -183,6 +183,25 @@ static void fill_tlb_entry(CPULoongArchState *env, Loo= ngArchTLB *tlb) lo1 =3D env->CSR_TLBELO1; } =20 + context->ps =3D csr_ps; + context->addr =3D csr_vppn << R_TLB_MISC_VPPN_SHIFT; + context->pte_buddy[0] =3D lo0; + context->pte_buddy[1] =3D lo1; +} + +static void fill_tlb_entry(CPULoongArchState *env, LoongArchTLB *tlb) +{ + uint64_t lo0, lo1, csr_vppn; + uint16_t csr_asid; + uint8_t csr_ps; + MMUContext context; + + sptw_prepare_context(env, &context); + csr_vppn =3D context.addr >> R_TLB_MISC_VPPN_SHIFT; + csr_ps =3D context.ps; + lo0 =3D context.pte_buddy[0]; + lo1 =3D context.pte_buddy[1]; + /* Store page size in field PS */ tlb->tlb_misc =3D FIELD_DP64(tlb->tlb_misc, TLB_MISC, PS, csr_ps); tlb->tlb_misc =3D FIELD_DP64(tlb->tlb_misc, TLB_MISC, VPPN, csr_vppn); --=20 2.39.3 From nobody Fri Nov 14 23:31:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1759204532020901.6136218306863; Mon, 29 Sep 2025 20:55:32 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v3RQy-0000vQ-UZ; Mon, 29 Sep 2025 23:53:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v3RQx-0000ui-Hw for qemu-devel@nongnu.org; Mon, 29 Sep 2025 23:53:47 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v3RQq-0001pd-Vd for qemu-devel@nongnu.org; Mon, 29 Sep 2025 23:53:47 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8Dx+tE_VNtoyGsQAA--.35130S3; Tue, 30 Sep 2025 11:53:35 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJBxC8E8VNtoak+_AA--.40492S7; Tue, 30 Sep 2025 11:53:35 +0800 (CST) From: Bibo Mao To: Song Gao , Richard Henderson Cc: Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH v4 05/13] target/loongarch: Add common function get_tlb_random_index() Date: Tue, 30 Sep 2025 11:53:24 +0800 Message-Id: <20250930035332.2609520-6-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250930035332.2609520-1-maobibo@loongson.cn> References: <20250930035332.2609520-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJBxC8E8VNtoak+_AA--.40492S7 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1759204534775116600 Content-Type: text/plain; charset="utf-8" With software PTW system, tlb index is calculated randomly when new TLB entry is added. For hardware PTW, it is the same logic to add new TLB entry. Here common function get_tlb_random_index() is added to get random tlb index when adding new TLB entry. Signed-off-by: Bibo Mao --- target/loongarch/tcg/tlb_helper.c | 38 +++++++++++++++++++------------ 1 file changed, 24 insertions(+), 14 deletions(-) diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_h= elper.c index 01ade068ab..c062efc7b8 100644 --- a/target/loongarch/tcg/tlb_helper.c +++ b/target/loongarch/tcg/tlb_helper.c @@ -381,31 +381,22 @@ void helper_tlbwr(CPULoongArchState *env) *old =3D new; } =20 -void helper_tlbfill(CPULoongArchState *env) +static int get_tlb_random_index(CPULoongArchState *env, vaddr addr, + int pagesize) { - uint64_t address, entryhi; + uint64_t address; int index, set, i, stlb_idx; - uint16_t pagesize, stlb_ps; + uint16_t stlb_ps; uint16_t asid, tlb_asid; LoongArchTLB *tlb; uint8_t tlb_e; =20 - if (FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR)) { - entryhi =3D env->CSR_TLBREHI; - /* Validity of pagesize is checked in helper_ldpte() */ - pagesize =3D FIELD_EX64(env->CSR_TLBREHI, CSR_TLBREHI, PS); - } else { - entryhi =3D env->CSR_TLBEHI; - /* Validity of pagesize is checked in helper_tlbrd() */ - pagesize =3D FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, PS); - } - /* Validity of stlb_ps is checked in helper_csrwr_stlbps() */ stlb_ps =3D FIELD_EX64(env->CSR_STLBPS, CSR_STLBPS, PS); asid =3D FIELD_EX64(env->CSR_ASID, CSR_ASID, ASID); if (pagesize =3D=3D stlb_ps) { /* Only write into STLB bits [47:13] */ - address =3D entryhi & ~MAKE_64BIT_MASK(0, R_CSR_TLBEHI_64_VPPN_SHI= FT); + address =3D addr & ~MAKE_64BIT_MASK(0, R_CSR_TLBEHI_64_VPPN_SHIFT); set =3D -1; stlb_idx =3D (address >> (stlb_ps + 1)) & 0xff; /* [0,255] */ for (i =3D 0; i < 8; ++i) { @@ -450,6 +441,25 @@ void helper_tlbfill(CPULoongArchState *env) } } =20 + return index; +} + +void helper_tlbfill(CPULoongArchState *env) +{ + vaddr entryhi; + int index, pagesize; + + if (FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR)) { + entryhi =3D env->CSR_TLBREHI; + /* Validity of pagesize is checked in helper_ldpte() */ + pagesize =3D FIELD_EX64(env->CSR_TLBREHI, CSR_TLBREHI, PS); + } else { + entryhi =3D env->CSR_TLBEHI; + /* Validity of pagesize is checked in helper_tlbrd() */ + pagesize =3D FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, PS); + } + + index =3D get_tlb_random_index(env, entryhi, pagesize); invalidate_tlb(env, index); fill_tlb_entry(env, env->tlb + index); } --=20 2.39.3 From nobody Fri Nov 14 23:31:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1759204620554545.9473126267766; Mon, 29 Sep 2025 20:57:00 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v3RT8-0003UE-Ui; Mon, 29 Sep 2025 23:56:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v3RT7-0003SY-Dp for qemu-devel@nongnu.org; Mon, 29 Sep 2025 23:56:01 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v3RSw-0002ps-Cn for qemu-devel@nongnu.org; Mon, 29 Sep 2025 23:56:01 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8Cx5tBAVNtoymsQAA--.34559S3; Tue, 30 Sep 2025 11:53:36 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJBxC8E8VNtoak+_AA--.40492S8; Tue, 30 Sep 2025 11:53:35 +0800 (CST) From: Bibo Mao To: Song Gao , Richard Henderson Cc: Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH v4 06/13] target/loongarch: Add MMUContext parameter in fill_tlb_entry() Date: Tue, 30 Sep 2025 11:53:25 +0800 Message-Id: <20250930035332.2609520-7-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250930035332.2609520-1-maobibo@loongson.cn> References: <20250930035332.2609520-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJBxC8E8VNtoak+_AA--.40492S8 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1759204622833116600 Content-Type: text/plain; charset="utf-8" Function fill_tlb_entry() can be used with hardware PTW in future, here add input parameter MMUContext in fill_tlb_entry(). Signed-off-by: Bibo Mao --- target/loongarch/tcg/tlb_helper.c | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_h= elper.c index c062efc7b8..465d2885e1 100644 --- a/target/loongarch/tcg/tlb_helper.c +++ b/target/loongarch/tcg/tlb_helper.c @@ -189,18 +189,17 @@ static void sptw_prepare_context(CPULoongArchState *e= nv, MMUContext *context) context->pte_buddy[1] =3D lo1; } =20 -static void fill_tlb_entry(CPULoongArchState *env, LoongArchTLB *tlb) +static void fill_tlb_entry(CPULoongArchState *env, LoongArchTLB *tlb, + MMUContext *context) { uint64_t lo0, lo1, csr_vppn; uint16_t csr_asid; uint8_t csr_ps; - MMUContext context; =20 - sptw_prepare_context(env, &context); - csr_vppn =3D context.addr >> R_TLB_MISC_VPPN_SHIFT; - csr_ps =3D context.ps; - lo0 =3D context.pte_buddy[0]; - lo1 =3D context.pte_buddy[1]; + csr_vppn =3D context->addr >> R_TLB_MISC_VPPN_SHIFT; + csr_ps =3D context->ps; + lo0 =3D context->pte_buddy[0]; + lo1 =3D context->pte_buddy[1]; =20 /* Store page size in field PS */ tlb->tlb_misc =3D FIELD_DP64(tlb->tlb_misc, TLB_MISC, PS, csr_ps); @@ -354,6 +353,7 @@ void helper_tlbwr(CPULoongArchState *env) int index =3D FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, INDEX); LoongArchTLB *old, new =3D {}; bool skip_inv =3D false, tlb_v0, tlb_v1; + MMUContext context; =20 old =3D env->tlb + index; if (FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, NE)) { @@ -361,7 +361,8 @@ void helper_tlbwr(CPULoongArchState *env) return; } =20 - fill_tlb_entry(env, &new); + sptw_prepare_context(env, &context); + fill_tlb_entry(env, &new, &context); /* Check whether ASID/VPPN is the same */ if (old->tlb_misc =3D=3D new.tlb_misc) { /* Check whether both even/odd pages is the same or invalid */ @@ -448,6 +449,7 @@ void helper_tlbfill(CPULoongArchState *env) { vaddr entryhi; int index, pagesize; + MMUContext context; =20 if (FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR)) { entryhi =3D env->CSR_TLBREHI; @@ -459,9 +461,10 @@ void helper_tlbfill(CPULoongArchState *env) pagesize =3D FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, PS); } =20 + sptw_prepare_context(env, &context); index =3D get_tlb_random_index(env, entryhi, pagesize); invalidate_tlb(env, index); - fill_tlb_entry(env, env->tlb + index); + fill_tlb_entry(env, env->tlb + index, &context); } =20 void helper_tlbclr(CPULoongArchState *env) --=20 2.39.3 From nobody Fri Nov 14 23:31:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1759204533255301.5780207801048; Mon, 29 Sep 2025 20:55:33 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v3RQz-0000vg-E3; Mon, 29 Sep 2025 23:53:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v3RQx-0000ub-7q for qemu-devel@nongnu.org; Mon, 29 Sep 2025 23:53:47 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v3RQq-0001qQ-Tp for qemu-devel@nongnu.org; Mon, 29 Sep 2025 23:53:46 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8AxidFAVNtozmsQAA--.34729S3; Tue, 30 Sep 2025 11:53:36 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJBxC8E8VNtoak+_AA--.40492S9; Tue, 30 Sep 2025 11:53:36 +0800 (CST) From: Bibo Mao To: Song Gao , Richard Henderson Cc: Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH v4 07/13] target/loongarch: Add debug parameter with loongarch_page_table_walker() Date: Tue, 30 Sep 2025 11:53:26 +0800 Message-Id: <20250930035332.2609520-8-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250930035332.2609520-1-maobibo@loongson.cn> References: <20250930035332.2609520-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJBxC8E8VNtoak+_AA--.40492S9 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1759204534759116600 Content-Type: text/plain; charset="utf-8" Add debug parameter with function loongarch_page_table_walker(), in debug mode it is only to get physical address. And It used in future HW PTW usage, bit dirty and access will be updated in HW PTW mode. Also function loongarch_page_table_walker() is renamed as loongarch_ptw() for short. Signed-off-by: Bibo Mao --- target/loongarch/cpu_helper.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/target/loongarch/cpu_helper.c b/target/loongarch/cpu_helper.c index 05e7fd6f3f..8fc596763d 100644 --- a/target/loongarch/cpu_helper.c +++ b/target/loongarch/cpu_helper.c @@ -106,9 +106,8 @@ TLBRet loongarch_check_pte(CPULoongArchState *env, MMUC= ontext *context, return TLBRET_MATCH; } =20 -static TLBRet loongarch_page_table_walker(CPULoongArchState *env, - MMUContext *context, - int access_type, int mmu_idx) +static TLBRet loongarch_ptw(CPULoongArchState *env, MMUContext *context, + int access_type, int mmu_idx, int debug) { CPUState *cs =3D env_cpu(env); target_ulong index, phys; @@ -184,7 +183,7 @@ static TLBRet loongarch_map_address(CPULoongArchState *= env, * legal mapping, even if the mapping is not yet in TLB. return 0 = if * there is a valid map, else none zero. */ - return loongarch_page_table_walker(env, context, access_type, mmu_= idx); + return loongarch_ptw(env, context, access_type, mmu_idx, is_debug); } =20 return TLBRET_NOMATCH; --=20 2.39.3 From nobody Fri Nov 14 23:31:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1759204578466157.1236619671463; Mon, 29 Sep 2025 20:56:18 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v3RR3-0000wp-R7; Mon, 29 Sep 2025 23:53:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v3RR1-0000wM-G8 for qemu-devel@nongnu.org; Mon, 29 Sep 2025 23:53:51 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v3RQs-0001qU-0m for qemu-devel@nongnu.org; Mon, 29 Sep 2025 23:53:51 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8CxHvBAVNto0WsQAA--.34600S3; Tue, 30 Sep 2025 11:53:36 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJBxC8E8VNtoak+_AA--.40492S10; Tue, 30 Sep 2025 11:53:36 +0800 (CST) From: Bibo Mao To: Song Gao , Richard Henderson Cc: Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH v4 08/13] target/loongarch: Reserve higher 48 bit PTE attribute with huge page Date: Tue, 30 Sep 2025 11:53:27 +0800 Message-Id: <20250930035332.2609520-9-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250930035332.2609520-1-maobibo@loongson.cn> References: <20250930035332.2609520-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJBxC8E8VNtoak+_AA--.40492S10 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1759204580239116600 Content-Type: text/plain; charset="utf-8" With PTE entry, high bit 48-63 is valid HW bit for PTE attribute, for example bit 63 is RPLV and bit 62 is NX. With page directory table, it is physical address of page table from view of HW, so high bit 48-63 need be discarded. Here reverve high bit 48-63 with huge page since it is PTE entry, and only discard it with page directory table. Signed-off-by: Bibo Mao --- target/loongarch/cpu_helper.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/target/loongarch/cpu_helper.c b/target/loongarch/cpu_helper.c index 8fc596763d..07087c68b8 100644 --- a/target/loongarch/cpu_helper.c +++ b/target/loongarch/cpu_helper.c @@ -134,10 +134,13 @@ static TLBRet loongarch_ptw(CPULoongArchState *env, M= MUContext *context, /* get next level page directory */ index =3D (address >> dir_base) & ((1 << dir_width) - 1); phys =3D base | index << 3; - base =3D ldq_phys(cs->as, phys) & TARGET_PHYS_MASK; + base =3D ldq_phys(cs->as, phys); if (FIELD_EX64(base, TLBENTRY, HUGE)) { /* base is a huge pte */ break; + } else { + /* Discard high bits with page directory table */ + base &=3D TARGET_PHYS_MASK; } } =20 --=20 2.39.3 From nobody Fri Nov 14 23:31:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1759204577677726.9458683555412; Mon, 29 Sep 2025 20:56:17 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v3RS2-00017Y-S9; Mon, 29 Sep 2025 23:54:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v3RS0-00017F-Jg for qemu-devel@nongnu.org; Mon, 29 Sep 2025 23:54:52 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v3RRt-0002NI-8X for qemu-devel@nongnu.org; Mon, 29 Sep 2025 23:54:52 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8Axjr9AVNto1GsQAA--.33149S3; Tue, 30 Sep 2025 11:53:36 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJBxC8E8VNtoak+_AA--.40492S11; Tue, 30 Sep 2025 11:53:36 +0800 (CST) From: Bibo Mao To: Song Gao , Richard Henderson Cc: Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH v4 09/13] target/loongarch: Move last PTE lookup into page table walker loop Date: Tue, 30 Sep 2025 11:53:28 +0800 Message-Id: <20250930035332.2609520-10-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250930035332.2609520-1-maobibo@loongson.cn> References: <20250930035332.2609520-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJBxC8E8VNtoak+_AA--.40492S11 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1759204578226116600 Content-Type: text/plain; charset="utf-8" The last PTE lookup sentence is much similiar with the whole page table walker loop, move it into the whole loop. Signed-off-by: Bibo Mao --- target/loongarch/cpu_helper.c | 24 ++++++++++-------------- 1 file changed, 10 insertions(+), 14 deletions(-) diff --git a/target/loongarch/cpu_helper.c b/target/loongarch/cpu_helper.c index 07087c68b8..09fb1e46d4 100644 --- a/target/loongarch/cpu_helper.c +++ b/target/loongarch/cpu_helper.c @@ -124,7 +124,7 @@ static TLBRet loongarch_ptw(CPULoongArchState *env, MMU= Context *context, } base &=3D TARGET_PHYS_MASK; =20 - for (level =3D 4; level > 0; level--) { + for (level =3D 4; level >=3D 0; level--) { get_dir_base_width(env, &dir_base, &dir_width, level); =20 if (dir_width =3D=3D 0) { @@ -135,17 +135,19 @@ static TLBRet loongarch_ptw(CPULoongArchState *env, M= MUContext *context, index =3D (address >> dir_base) & ((1 << dir_width) - 1); phys =3D base | index << 3; base =3D ldq_phys(cs->as, phys); - if (FIELD_EX64(base, TLBENTRY, HUGE)) { - /* base is a huge pte */ - break; - } else { - /* Discard high bits with page directory table */ - base &=3D TARGET_PHYS_MASK; + if (level) { + if (FIELD_EX64(base, TLBENTRY, HUGE)) { + /* base is a huge pte */ + break; + } else { + /* Discard high bits with page directory table */ + base &=3D TARGET_PHYS_MASK; + } } } =20 /* pte */ - if (FIELD_EX64(base, TLBENTRY, HUGE)) { + if (level > 0) { /* Huge Page. base is pte */ base =3D FIELD_DP64(base, TLBENTRY, LEVEL, 0); base =3D FIELD_DP64(base, TLBENTRY, HUGE, 0); @@ -153,12 +155,6 @@ static TLBRet loongarch_ptw(CPULoongArchState *env, MM= UContext *context, base =3D FIELD_DP64(base, TLBENTRY, HGLOBAL, 0); base =3D FIELD_DP64(base, TLBENTRY, G, 1); } - } else { - /* Normal Page. base points to pte */ - get_dir_base_width(env, &dir_base, &dir_width, 0); - index =3D (address >> dir_base) & ((1 << dir_width) - 1); - phys =3D base | index << 3; - base =3D ldq_phys(cs->as, phys); } =20 context->ps =3D dir_base; --=20 2.39.3 From nobody Fri Nov 14 23:31:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17592046054031016.7215251834627; Mon, 29 Sep 2025 20:56:45 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v3RRI-00010b-5R; Mon, 29 Sep 2025 23:54:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v3RRF-00010Q-PS for qemu-devel@nongnu.org; Mon, 29 Sep 2025 23:54:05 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v3RR9-0001rc-Tk for qemu-devel@nongnu.org; Mon, 29 Sep 2025 23:54:05 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8BxXNJBVNto12sQAA--.34770S3; Tue, 30 Sep 2025 11:53:37 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJBxC8E8VNtoak+_AA--.40492S12; Tue, 30 Sep 2025 11:53:36 +0800 (CST) From: Bibo Mao To: Song Gao , Richard Henderson Cc: Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH v4 10/13] target/loongarch: Add field tlb_index to record TLB search info Date: Tue, 30 Sep 2025 11:53:29 +0800 Message-Id: <20250930035332.2609520-11-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250930035332.2609520-1-maobibo@loongson.cn> References: <20250930035332.2609520-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJBxC8E8VNtoak+_AA--.40492S12 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1759204606718116600 Content-Type: text/plain; charset="utf-8" With hardware PTW function, TLB entry will be searched at first. If there is odd/even page on one TLB entry, and odd page is valid and even page is none. When software access memory with address in even page, hardware PTW will happen and fill new entry in the same TLB entry. Here add field tlb_index to record TLB index when search TLB tables. Signed-off-by: Bibo Mao --- target/loongarch/cpu-mmu.h | 2 ++ target/loongarch/cpu_helper.c | 3 +++ target/loongarch/tcg/tlb_helper.c | 1 + 3 files changed, 6 insertions(+) diff --git a/target/loongarch/cpu-mmu.h b/target/loongarch/cpu-mmu.h index 865800fc0a..c3e869234a 100644 --- a/target/loongarch/cpu-mmu.h +++ b/target/loongarch/cpu-mmu.h @@ -25,6 +25,8 @@ typedef struct MMUContext { hwaddr physical; int ps; /* page size shift */ int prot; + int tlb_index; + int mmu_index; uint64_t pte_buddy[2]; } MMUContext; =20 diff --git a/target/loongarch/cpu_helper.c b/target/loongarch/cpu_helper.c index 09fb1e46d4..e2d66f4c86 100644 --- a/target/loongarch/cpu_helper.c +++ b/target/loongarch/cpu_helper.c @@ -97,6 +97,7 @@ TLBRet loongarch_check_pte(CPULoongArchState *env, MMUCon= text *context, context->physical =3D (tlb_ppn << R_TLBENTRY_64_PPN_SHIFT) | (context->addr & MAKE_64BIT_MASK(0, tlb_ps)); context->prot =3D PAGE_READ; + context->mmu_index =3D tlb_plv; if (tlb_d) { context->prot |=3D PAGE_WRITE; } @@ -216,6 +217,7 @@ TLBRet get_physical_address(CPULoongArchState *env, MMU= Context *context, if (da & !pg) { context->physical =3D address & TARGET_PHYS_MASK; context->prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; + context->mmu_index =3D MMU_DA_IDX; return TLBRET_MATCH; } =20 @@ -235,6 +237,7 @@ TLBRet get_physical_address(CPULoongArchState *env, MMU= Context *context, if ((plv & env->CSR_DMW[i]) && (base_c =3D=3D base_v)) { context->physical =3D dmw_va2pa(env, address, env->CSR_DMW[i]); context->prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; + context->mmu_index =3D MMU_DA_IDX; return TLBRET_MATCH; } } diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_h= elper.c index 465d2885e1..e5ed46bfd6 100644 --- a/target/loongarch/tcg/tlb_helper.c +++ b/target/loongarch/tcg/tlb_helper.c @@ -743,6 +743,7 @@ static TLBRet loongarch_map_tlb_entry(CPULoongArchState= *env, n =3D (context->addr >> tlb_ps) & 0x1;/* Odd or even */ context->pte =3D n ? tlb->tlb_entry1 : tlb->tlb_entry0; context->ps =3D tlb_ps; + context->tlb_index =3D index; return loongarch_check_pte(env, context, access_type, mmu_idx); } =20 --=20 2.39.3 From nobody Fri Nov 14 23:31:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1759204558384737.370287263527; Mon, 29 Sep 2025 20:55:58 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v3RRA-0000za-HM; Mon, 29 Sep 2025 23:54:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v3RR6-0000xx-7m for qemu-devel@nongnu.org; Mon, 29 Sep 2025 23:53:57 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v3RQw-0001s5-1V for qemu-devel@nongnu.org; Mon, 29 Sep 2025 23:53:55 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8Dxvr9BVNto2msQAA--.33114S3; Tue, 30 Sep 2025 11:53:37 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJBxC8E8VNtoak+_AA--.40492S13; Tue, 30 Sep 2025 11:53:37 +0800 (CST) From: Bibo Mao To: Song Gao , Richard Henderson Cc: Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH v4 11/13] target/loongarch: Add basic hardware PTW support Date: Tue, 30 Sep 2025 11:53:30 +0800 Message-Id: <20250930035332.2609520-12-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250930035332.2609520-1-maobibo@loongson.cn> References: <20250930035332.2609520-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJBxC8E8VNtoak+_AA--.40492S13 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1759204560441116600 Content-Type: text/plain; charset="utf-8" However with hardware PTW supported, hardware will search page table with TLB miss. Also if there is no TLB miss however bit Present is not set, hardware PTW will happen also. Because there is odd/even page in one TLB entry on LoongArch system, for example in the first time odd TLB entry is valid and even TLB entry is 0. When software accesses with address within even page, there is no TLB miss only that TLB entry is 0. In this condition, hardwre PTW will happen also. Signed-off-by: Bibo Mao --- target/loongarch/cpu-mmu.h | 2 ++ target/loongarch/cpu_helper.c | 17 ++++++++++++++--- target/loongarch/tcg/tlb_helper.c | 26 ++++++++++++++++++++++++++ 3 files changed, 42 insertions(+), 3 deletions(-) diff --git a/target/loongarch/cpu-mmu.h b/target/loongarch/cpu-mmu.h index c3e869234a..4c227d4ef3 100644 --- a/target/loongarch/cpu-mmu.h +++ b/target/loongarch/cpu-mmu.h @@ -67,6 +67,8 @@ TLBRet loongarch_check_pte(CPULoongArchState *env, MMUCon= text *context, TLBRet get_physical_address(CPULoongArchState *env, MMUContext *context, MMUAccessType access_type, int mmu_idx, int is_debug); +TLBRet loongarch_ptw(CPULoongArchState *env, MMUContext *context, + int access_type, int mmu_idx, int debug); void get_dir_base_width(CPULoongArchState *env, uint64_t *dir_base, uint64_t *dir_width, target_ulong level); hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); diff --git a/target/loongarch/cpu_helper.c b/target/loongarch/cpu_helper.c index e2d66f4c86..3fd0f574b4 100644 --- a/target/loongarch/cpu_helper.c +++ b/target/loongarch/cpu_helper.c @@ -107,11 +107,11 @@ TLBRet loongarch_check_pte(CPULoongArchState *env, MM= UContext *context, return TLBRET_MATCH; } =20 -static TLBRet loongarch_ptw(CPULoongArchState *env, MMUContext *context, - int access_type, int mmu_idx, int debug) +TLBRet loongarch_ptw(CPULoongArchState *env, MMUContext *context, + int access_type, int mmu_idx, int debug) { CPUState *cs =3D env_cpu(env); - target_ulong index, phys; + target_ulong index =3D 0, phys =3D 0; uint64_t dir_base, dir_width; uint64_t base; int level; @@ -139,6 +139,8 @@ static TLBRet loongarch_ptw(CPULoongArchState *env, MMU= Context *context, if (level) { if (FIELD_EX64(base, TLBENTRY, HUGE)) { /* base is a huge pte */ + index =3D 0; + dir_base -=3D 1; break; } else { /* Discard high bits with page directory table */ @@ -156,6 +158,15 @@ static TLBRet loongarch_ptw(CPULoongArchState *env, MM= UContext *context, base =3D FIELD_DP64(base, TLBENTRY, HGLOBAL, 0); base =3D FIELD_DP64(base, TLBENTRY, G, 1); } + + context->pte_buddy[index] =3D base; + context->pte_buddy[1 - index] =3D base + BIT_ULL(dir_base); + base +=3D (BIT_ULL(dir_base) & address); + } else if (cpu_has_ptw(env)) { + index &=3D 1; + context->pte_buddy[index] =3D base; + context->pte_buddy[1 - index] =3D ldq_phys(cs->as, + phys + 8 * (1 - 2 * index)); } =20 context->ps =3D dir_base; diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_h= elper.c index e5ed46bfd6..f3596a5154 100644 --- a/target/loongarch/tcg/tlb_helper.c +++ b/target/loongarch/tcg/tlb_helper.c @@ -591,6 +591,20 @@ void helper_invtlb_page_asid_or_g(CPULoongArchState *e= nv, } } =20 +static void ptw_update_tlb(CPULoongArchState *env, MMUContext *context) +{ + int index; + bool match; + + match =3D loongarch_tlb_search(env, context->addr, &index); + if (!match) { + index =3D get_tlb_random_index(env, context->addr, context->ps); + } + + invalidate_tlb(env, index); + fill_tlb_entry(env, env->tlb + index, context); +} + bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) @@ -604,6 +618,18 @@ bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr addres= s, int size, /* Data access */ context.addr =3D address; ret =3D get_physical_address(env, &context, access_type, mmu_idx, 0); + if (ret !=3D TLBRET_MATCH && cpu_has_ptw(env)) { + /* Take HW PTW if TLB missed or bit P is zero */ + if (ret =3D=3D TLBRET_NOMATCH || ret =3D=3D TLBRET_INVALID) { + ret =3D loongarch_ptw(env, &context, access_type, mmu_idx, 0); + if (ret =3D=3D TLBRET_MATCH) { + ptw_update_tlb(env, &context); + } + } else { + invalidate_tlb(env, context.tlb_index); + } + } + if (ret =3D=3D TLBRET_MATCH) { physical =3D context.physical; prot =3D context.prot; --=20 2.39.3 From nobody Fri Nov 14 23:31:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1759204531081475.2114624635683; Mon, 29 Sep 2025 20:55:31 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v3RR5-0000xi-Ax; Mon, 29 Sep 2025 23:53:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v3RR3-0000wq-I6 for qemu-devel@nongnu.org; Mon, 29 Sep 2025 23:53:53 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v3RQs-0001re-4L for qemu-devel@nongnu.org; Mon, 29 Sep 2025 23:53:53 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8Bxnr9BVNto3WsQAA--.33244S3; Tue, 30 Sep 2025 11:53:37 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJBxC8E8VNtoak+_AA--.40492S14; Tue, 30 Sep 2025 11:53:37 +0800 (CST) From: Bibo Mao To: Song Gao , Richard Henderson Cc: Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH v4 12/13] target/loongarch: Update matched ptw bit A/D with PTW supported Date: Tue, 30 Sep 2025 11:53:31 +0800 Message-Id: <20250930035332.2609520-13-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250930035332.2609520-1-maobibo@loongson.cn> References: <20250930035332.2609520-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJBxC8E8VNtoak+_AA--.40492S14 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1759204534707116600 Content-Type: text/plain; charset="utf-8" With hardware PTE supported, bit A will be set if there is read access or instruction fetch, and bit D will be set with write access. Signed-off-by: Bibo Mao --- target/loongarch/cpu-mmu.h | 26 ++++++++++ target/loongarch/cpu_helper.c | 93 ++++++++++++++++++++++++++++++++++- 2 files changed, 117 insertions(+), 2 deletions(-) diff --git a/target/loongarch/cpu-mmu.h b/target/loongarch/cpu-mmu.h index 4c227d4ef3..85d01e1bbe 100644 --- a/target/loongarch/cpu-mmu.h +++ b/target/loongarch/cpu-mmu.h @@ -61,6 +61,32 @@ static inline bool pte_write(CPULoongArchState *env, uin= t64_t entry) return !!writable; } =20 +/* + * The folloing functions should be called with PTW enable checked + * With hardware PTW enabled + * Bit D will be set by hardware with write access + * Bit A will be set by hardware with read/intruction fetch access + */ +static inline uint64_t pte_mkaccess(uint64_t entry) +{ + return FIELD_DP64(entry, TLBENTRY, V, 1); +} + +static inline uint64_t pte_mkdirty(uint64_t entry) +{ + return FIELD_DP64(entry, TLBENTRY, D, 1); +} + +static inline bool pte_access(uint64_t entry) +{ + return !!FIELD_EX64(entry, TLBENTRY, V); +} + +static inline bool pte_dirty(uint64_t entry) +{ + return !!FIELD_EX64(entry, TLBENTRY, D); +} + bool check_ps(CPULoongArchState *ent, uint8_t ps); TLBRet loongarch_check_pte(CPULoongArchState *env, MMUContext *context, MMUAccessType access_type, int mmu_idx); diff --git a/target/loongarch/cpu_helper.c b/target/loongarch/cpu_helper.c index 3fd0f574b4..7419847f95 100644 --- a/target/loongarch/cpu_helper.c +++ b/target/loongarch/cpu_helper.c @@ -107,15 +107,52 @@ TLBRet loongarch_check_pte(CPULoongArchState *env, MM= UContext *context, return TLBRET_MATCH; } =20 +static MemTxResult loongarch_cmpxchg_phys(CPUState *cs, hwaddr phys, + uint64_t old, uint64_t new) +{ + hwaddr addr1, l =3D 8; + MemoryRegion *mr; + uint8_t *ram_ptr; + uint64_t old1; + MemTxResult ret; + + rcu_read_lock(); + mr =3D address_space_translate(cs->as, phys, &addr1, &l, + false, MEMTXATTRS_UNSPECIFIED); + if (!memory_region_is_ram(mr)) { + /* + * Misconfigured PTE in ROM (AD bits are not preset) or + * PTE is in IO space and can't be updated atomically. + */ + rcu_read_unlock(); + return MEMTX_ACCESS_ERROR; + } + + ram_ptr =3D qemu_map_ram_ptr(mr->ram_block, addr1); + old1 =3D qatomic_cmpxchg((uint64_t *)ram_ptr, cpu_to_le64(old), + cpu_to_le64(new)); + old1 =3D le64_to_cpu(old1); + if (old1 =3D=3D old) { + ret =3D MEMTX_OK; + } else { + ret =3D MEMTX_DECODE_ERROR; + } + rcu_read_unlock(); + + return ret; +} + TLBRet loongarch_ptw(CPULoongArchState *env, MMUContext *context, int access_type, int mmu_idx, int debug) { CPUState *cs =3D env_cpu(env); target_ulong index =3D 0, phys =3D 0; uint64_t dir_base, dir_width; - uint64_t base; + uint64_t base, pte; int level; vaddr address; + TLBRet ret; + MemTxResult ret1; =20 address =3D context->addr; if ((address >> 63) & 0x1) { @@ -149,7 +186,9 @@ TLBRet loongarch_ptw(CPULoongArchState *env, MMUContext= *context, } } =20 +restart: /* pte */ + pte =3D base; if (level > 0) { /* Huge Page. base is pte */ base =3D FIELD_DP64(base, TLBENTRY, LEVEL, 0); @@ -171,7 +210,57 @@ TLBRet loongarch_ptw(CPULoongArchState *env, MMUContex= t *context, =20 context->ps =3D dir_base; context->pte =3D base; - return loongarch_check_pte(env, context, access_type, mmu_idx); + ret =3D loongarch_check_pte(env, context, access_type, mmu_idx); + if (debug) { + return ret; + } + + /* + * Update bit A/D with hardware PTW supported + * + * Need atomic compchxg operation with pte update, other vCPUs may + * update pte at the same time. + */ + if (ret =3D=3D TLBRET_MATCH && cpu_has_ptw(env)) { + if (access_type =3D=3D MMU_DATA_STORE && pte_dirty(base)) { + return ret; + } + + if (access_type !=3D MMU_DATA_STORE && pte_access(base)) { + return ret; + } + + base =3D pte_mkaccess(pte); + if (access_type =3D=3D MMU_DATA_STORE) { + base =3D pte_mkdirty(base); + } + ret1 =3D loongarch_cmpxchg_phys(cs, phys, pte, base); + /* PTE updated by other CPU, reload PTE entry */ + if (ret1 =3D=3D MEMTX_DECODE_ERROR) { + base =3D ldq_phys(cs->as, phys); + goto restart; + } + + base =3D context->pte_buddy[index]; + base =3D pte_mkaccess(base); + if (access_type =3D=3D MMU_DATA_STORE) { + base =3D pte_mkdirty(base); + } + context->pte_buddy[index] =3D base; + + /* Bit A/D need be updated with both Even/Odd page with huge pte */ + if (level > 0) { + index =3D 1 - index; + base =3D context->pte_buddy[index]; + base =3D pte_mkaccess(base); + if (access_type =3D=3D MMU_DATA_STORE) { + base =3D pte_mkdirty(base); + } + context->pte_buddy[index] =3D base; + } + } + + return ret; } =20 static TLBRet loongarch_map_address(CPULoongArchState *env, --=20 2.39.3 From nobody Fri Nov 14 23:31:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 175920473187890.93509260528833; Mon, 29 Sep 2025 20:58:51 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v3RVP-00073V-NP; Mon, 29 Sep 2025 23:58:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v3RVO-00073N-Gk for qemu-devel@nongnu.org; Mon, 29 Sep 2025 23:58:22 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v3RVL-0003WQ-C1 for qemu-devel@nongnu.org; Mon, 29 Sep 2025 23:58:21 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8Axjr9XVdtoj2wQAA--.33158S3; Tue, 30 Sep 2025 11:58:15 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJBxzsFXVdtoaFG_AA--.50748S2; Tue, 30 Sep 2025 11:58:15 +0800 (CST) From: Bibo Mao To: Song Gao , Richard Henderson Cc: Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH v4 13/13] target/loongarch: Add bit A/D checking in TLB entry with PTW supported Date: Tue, 30 Sep 2025 11:58:15 +0800 Message-Id: <20250930035815.2609613-1-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250930035332.2609520-1-maobibo@loongson.cn> References: <20250930035332.2609520-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJBxzsFXVdtoaFG_AA--.50748S2 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1759204734138116601 Content-Type: text/plain; charset="utf-8" With read/write access, add bit A/D checking if hardware PTW is supported. If no matched, hardware page table walk is called. And then bit A/D is updated in PTE entry and TLB entry is updated also. Signed-off-by: Bibo Mao --- target/loongarch/tcg/tlb_helper.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_h= elper.c index f3596a5154..fabbca6164 100644 --- a/target/loongarch/tcg/tlb_helper.c +++ b/target/loongarch/tcg/tlb_helper.c @@ -618,6 +618,22 @@ bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr addres= s, int size, /* Data access */ context.addr =3D address; ret =3D get_physical_address(env, &context, access_type, mmu_idx, 0); + if (ret =3D=3D TLBRET_MATCH && context.mmu_index !=3D MMU_DA_IDX + && cpu_has_ptw(env)) { + bool need_update =3D true; + + if (access_type =3D=3D MMU_DATA_STORE && pte_dirty(context.pte)) { + need_update =3D false; + } else if (access_type !=3D MMU_DATA_STORE && pte_access(context.p= te)) { + need_update =3D false; + } + + if (need_update) { + /* Need update bit A/D in PTE entry, take PTW again */ + ret =3D TLBRET_NOMATCH; + } + } + if (ret !=3D TLBRET_MATCH && cpu_has_ptw(env)) { /* Take HW PTW if TLB missed or bit P is zero */ if (ret =3D=3D TLBRET_NOMATCH || ret =3D=3D TLBRET_INVALID) { --=20 2.39.3