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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1759164808; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=fRGfIADnbxQLASkEsNkxa8b+HPhV/U2wqvMv6xwGtHw=; b=cq73+htIGGFy4LjXWEecxEN5rN3tuptlo1+OgDuq2GM/Qj/qzQKG6EycstsVj3mVWae8SS pQ3imrMHpVEslGg73+qYv50kXNZVjZzD3698DQjK5zLASnAFa4IkLBtIz0QRyzguoWjIWq 6vFJxEyTYgh0rW3wDvb/kKebxpSIpdk= X-MC-Unique: kpdFrozxNYmtAz2g1iLIXw-1 X-Mimecast-MFC-AGG-ID: kpdFrozxNYmtAz2g1iLIXw_1759164806 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 22/32] hw/pci-host/aspeed: Add AST2700 PCIe PHY Date: Mon, 29 Sep 2025 18:52:20 +0200 Message-ID: <20250929165230.797471-23-clg@redhat.com> In-Reply-To: <20250929165230.797471-1-clg@redhat.com> References: <20250929165230.797471-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.513, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1759165190215116600 From: Jamin Lin Introduce a PCIe Host Controller PHY model for AST2700. This adds an AST2700 specific PHY type (TYPE_ASPEED_2700_PCIE_PHY) with a 0x800 byte register space and link-status bits compatible with the firmware=E2=80=99s expectations. AST2700 provides three PCIe RCs; PCIe0 and PCIe1 are GEN4, PCIe2 is GEN2. The PHY exposes: PEHR_2700_LINK_GEN2 at 0x344, bit 18 indicates GEN2 link up PEHR_2700_LINK_GEN4 at 0x358, bit 8 indicates GEN4 link up In real hardware these GEN2/GEN4 link bits are mutually exclusive. QEMU does not model GEN2 vs GEN4 signaling differences, so the reset handler sets both bits to 1. This keeps the model simple and lets firmware see the link as up; firmware will read the appropriate register per RC port to infer the intended mode. The header gains TYPE_ASPEED_2700_PCIE_PHY; the new class derives from TYPE_ASPEED_PCIE_PHY, sets nr_regs to 0x800 >> 2, and installs an AST2700 reset routine that programs the class code (0x06040011) and the GEN2/GEN4 status bits. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20250919093017.338309-10-jamin_lin= @aspeedtech.com Signed-off-by: C=C3=A9dric Le Goater --- include/hw/pci-host/aspeed_pcie.h | 1 + hw/pci-host/aspeed_pcie.c | 39 +++++++++++++++++++++++++++++++ 2 files changed, 40 insertions(+) diff --git a/include/hw/pci-host/aspeed_pcie.h b/include/hw/pci-host/aspeed= _pcie.h index 5e60cba07b66..5806505f30ef 100644 --- a/include/hw/pci-host/aspeed_pcie.h +++ b/include/hw/pci-host/aspeed_pcie.h @@ -114,6 +114,7 @@ struct AspeedPCIECfgClass { }; =20 #define TYPE_ASPEED_PCIE_PHY "aspeed.pcie-phy" +#define TYPE_ASPEED_2700_PCIE_PHY TYPE_ASPEED_PCIE_PHY "-ast2700" OBJECT_DECLARE_TYPE(AspeedPCIEPhyState, AspeedPCIEPhyClass, ASPEED_PCIE_PH= Y); =20 struct AspeedPCIEPhyState { diff --git a/hw/pci-host/aspeed_pcie.c b/hw/pci-host/aspeed_pcie.c index 8be55b962fc7..788160d5325c 100644 --- a/hw/pci-host/aspeed_pcie.c +++ b/hw/pci-host/aspeed_pcie.c @@ -696,6 +696,12 @@ REG32(PEHR_PROTECT, 0x7C) REG32(PEHR_LINK, 0xC0) FIELD(PEHR_LINK, STS, 5, 1) =20 +/* AST2700 */ +REG32(PEHR_2700_LINK_GEN2, 0x344) + FIELD(PEHR_2700_LINK_GEN2, STS, 18, 1) +REG32(PEHR_2700_LINK_GEN4, 0x358) + FIELD(PEHR_2700_LINK_GEN4, STS, 8, 1) + #define ASPEED_PCIE_PHY_UNLOCK 0xA8 =20 static uint64_t aspeed_pcie_phy_read(void *opaque, hwaddr addr, @@ -803,6 +809,38 @@ static const TypeInfo aspeed_pcie_phy_info =3D { .class_size =3D sizeof(AspeedPCIEPhyClass), }; =20 +static void aspeed_2700_pcie_phy_reset(DeviceState *dev) +{ + AspeedPCIEPhyState *s =3D ASPEED_PCIE_PHY(dev); + AspeedPCIEPhyClass *apc =3D ASPEED_PCIE_PHY_GET_CLASS(s); + + memset(s->regs, 0, apc->nr_regs << 2); + + s->regs[R_PEHR_ID] =3D + (0x1150 << R_PEHR_ID_DEV_SHIFT) | PCI_VENDOR_ID_ASPEED; + s->regs[R_PEHR_CLASS_CODE] =3D 0x06040011; + s->regs[R_PEHR_2700_LINK_GEN2] =3D R_PEHR_2700_LINK_GEN2_STS_MASK; + s->regs[R_PEHR_2700_LINK_GEN4] =3D R_PEHR_2700_LINK_GEN4_STS_MASK; +} + +static void aspeed_2700_pcie_phy_class_init(ObjectClass *klass, + const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + AspeedPCIEPhyClass *apc =3D ASPEED_PCIE_PHY_CLASS(klass); + + dc->desc =3D "ASPEED AST2700 PCIe Phy"; + device_class_set_legacy_reset(dc, aspeed_2700_pcie_phy_reset); + + apc->nr_regs =3D 0x800 >> 2; +} + +static const TypeInfo aspeed_2700_pcie_phy_info =3D { + .name =3D TYPE_ASPEED_2700_PCIE_PHY, + .parent =3D TYPE_ASPEED_PCIE_PHY, + .class_init =3D aspeed_2700_pcie_phy_class_init, +}; + static void aspeed_pcie_register_types(void) { type_register_static(&aspeed_pcie_rc_info); @@ -810,6 +848,7 @@ static void aspeed_pcie_register_types(void) type_register_static(&aspeed_pcie_root_port_info); type_register_static(&aspeed_pcie_cfg_info); type_register_static(&aspeed_pcie_phy_info); + type_register_static(&aspeed_2700_pcie_phy_info); } =20 type_init(aspeed_pcie_register_types); --=20 2.51.0