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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1759164802; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=9Vn6nVn2grX6v9kVJ/qtx8Oz9nupBzYh0oWeeiOEkg0=; b=IRORjZnVvj98qYf6z3WbOOEWLlCKBG2qjZs6NOm6Nz7e9qiuLjaWvC6GgUsMRXImMmRD/r DbDOhZUEKV7oTtQmJICPscrlATJFdutPlLA+fDiQEIsjbyhr/TNnw01lmTaj6A72DiSuCo Jh6teiXi1k0HRAAj4PvfKuGGrSs3+FU= X-MC-Unique: 8jg3zkipNoqkanZoRXKmsg-1 X-Mimecast-MFC-AGG-ID: 8jg3zkipNoqkanZoRXKmsg_1759164797 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 18/32] hw/pci-host/aspeed: Add AST2600 PCIe Root Port and make address configurable Date: Mon, 29 Sep 2025 18:52:16 +0200 Message-ID: <20250929165230.797471-19-clg@redhat.com> In-Reply-To: <20250929165230.797471-1-clg@redhat.com> References: <20250929165230.797471-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.513, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1759165086664116600 From: Jamin Lin Introduce an ASPEED PCIe Root Port and wire it under the RC. The root port is modeled as TYPE_ASPEED_PCIE_ROOT_PORT (subclass of TYPE_PCIE_ROOT_PORT). Key changes: - Add TYPE_ASPEED_PCIE_ROOT_PORT (PCIESlot-based) with vendor/device IDs and AER capability offset. - Extend AspeedPCIERcState to embed a root_port instance and a configurable rp_addr. - Add "rp-addr" property to the RC to place the root port at a specific devfn on the root bus. - Set the root port's "chassis" property to ensure a unique chassis per RC. - Extend AspeedPCIECfgClass with rc_rp_addr defaulting to PCI_DEVFN(8,0). Rationale: - AST2600 places the root port at 80:08.0 (bus 0x80, dev 8, fn 0). - AST2700 must place the root port at 00:00.0, and it supports three RCs. Each root port must therefore be uniquely identifiable; uses the PCIe "chassis" ID for that. - Providing a configurable "rp-addr" lets platforms select the correct devfn per SoC family, while the "chassis" property ensures uniqueness across multiple RC instances on AST2700. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20250919093017.338309-6-jamin_lin@= aspeedtech.com Signed-off-by: C=C3=A9dric Le Goater --- include/hw/pci-host/aspeed_pcie.h | 11 +++++++ hw/pci-host/aspeed_pcie.c | 50 +++++++++++++++++++++++++++++++ 2 files changed, 61 insertions(+) diff --git a/include/hw/pci-host/aspeed_pcie.h b/include/hw/pci-host/aspeed= _pcie.h index fe30ac02aeee..5346c15c8101 100644 --- a/include/hw/pci-host/aspeed_pcie.h +++ b/include/hw/pci-host/aspeed_pcie.h @@ -20,6 +20,7 @@ #include "hw/sysbus.h" #include "hw/pci/pci_bridge.h" #include "hw/pci/pcie_host.h" +#include "hw/pci/pcie_port.h" #include "qom/object.h" =20 typedef struct AspeedPCIECfgTxDesc { @@ -40,6 +41,13 @@ typedef struct AspeedPCIERegMap { AspeedPCIERcRegs rc; } AspeedPCIERegMap; =20 +#define TYPE_ASPEED_PCIE_ROOT_PORT "aspeed.pcie-root-port" +OBJECT_DECLARE_SIMPLE_TYPE(AspeedPCIERootPortState, ASPEED_PCIE_ROOT_PORT) + +typedef struct AspeedPCIERootPortState { + PCIESlot parent_obj; +} AspeedPCIERootPortState; + #define TYPE_ASPEED_PCIE_ROOT_DEVICE "aspeed.pcie-root-device" OBJECT_DECLARE_SIMPLE_TYPE(AspeedPCIERootDeviceState, ASPEED_PCIE_ROOT_DEV= ICE); =20 @@ -58,12 +66,14 @@ struct AspeedPCIERcState { MemoryRegion mmio; MemoryRegion io; =20 + uint32_t rp_addr; uint32_t bus_nr; char name[16]; bool has_rd; qemu_irq irq; =20 AspeedPCIERootDeviceState root_device; + AspeedPCIERootPortState root_port; }; =20 /* Bridge between AHB bus and PCIe RC. */ @@ -87,6 +97,7 @@ struct AspeedPCIECfgClass { const AspeedPCIERegMap *reg_map; const MemoryRegionOps *reg_ops; =20 + uint32_t rc_rp_addr; uint64_t rc_bus_nr; uint64_t nr_regs; bool rc_has_rd; diff --git a/hw/pci-host/aspeed_pcie.c b/hw/pci-host/aspeed_pcie.c index 6e563a07a3f2..dafffbde61b9 100644 --- a/hw/pci-host/aspeed_pcie.c +++ b/hw/pci-host/aspeed_pcie.c @@ -21,6 +21,7 @@ #include "hw/registerfields.h" #include "hw/irq.h" #include "hw/pci/pci_host.h" +#include "hw/pci/pcie_port.h" #include "hw/pci-host/aspeed_pcie.h" #include "hw/pci/msi.h" #include "trace.h" @@ -63,6 +64,32 @@ static const TypeInfo aspeed_pcie_root_device_info =3D { }, }; =20 +/* + * PCIe Root Port + */ + +static void aspeed_pcie_root_port_class_init(ObjectClass *klass, + const void *data) +{ + PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); + DeviceClass *dc =3D DEVICE_CLASS(klass); + PCIERootPortClass *rpc =3D PCIE_ROOT_PORT_CLASS(klass); + + dc->desc =3D "ASPEED PCIe Root Port"; + k->vendor_id =3D PCI_VENDOR_ID_ASPEED; + k->device_id =3D 0x1150; + dc->user_creatable =3D true; + + rpc->aer_offset =3D 0x100; +} + +static const TypeInfo aspeed_pcie_root_port_info =3D { + .name =3D TYPE_ASPEED_PCIE_ROOT_PORT, + .parent =3D TYPE_PCIE_ROOT_PORT, + .instance_size =3D sizeof(AspeedPCIERootPortState), + .class_init =3D aspeed_pcie_root_port_class_init, +}; + /* * PCIe Root Complex (RC) */ @@ -144,6 +171,13 @@ static void aspeed_pcie_rc_realize(DeviceState *dev, E= rror **errp) return; } } + + /* setup root port */ + qdev_prop_set_int32(DEVICE(&rc->root_port), "addr", rc->rp_addr); + qdev_prop_set_uint16(DEVICE(&rc->root_port), "chassis", cfg->id); + if (!qdev_realize(DEVICE(&rc->root_port), BUS(pci->bus), errp)) { + return; + } } =20 static const char *aspeed_pcie_rc_root_bus_path(PCIHostState *host_bridge, @@ -158,9 +192,19 @@ static const char *aspeed_pcie_rc_root_bus_path(PCIHos= tState *host_bridge, return rc->name; } =20 +static void aspeed_pcie_rc_instance_init(Object *obj) +{ + AspeedPCIERcState *rc =3D ASPEED_PCIE_RC(obj); + AspeedPCIERootPortState *root_port =3D &rc->root_port; + + object_initialize_child(obj, "root_port", root_port, + TYPE_ASPEED_PCIE_ROOT_PORT); +} + static const Property aspeed_pcie_rc_props[] =3D { DEFINE_PROP_UINT32("bus-nr", AspeedPCIERcState, bus_nr, 0), DEFINE_PROP_BOOL("has-rd", AspeedPCIERcState, has_rd, 0), + DEFINE_PROP_UINT32("rp-addr", AspeedPCIERcState, rp_addr, 0), }; =20 static void aspeed_pcie_rc_class_init(ObjectClass *klass, const void *data) @@ -183,6 +227,7 @@ static const TypeInfo aspeed_pcie_rc_info =3D { .name =3D TYPE_ASPEED_PCIE_RC, .parent =3D TYPE_PCIE_HOST_BRIDGE, .instance_size =3D sizeof(AspeedPCIERcState), + .instance_init =3D aspeed_pcie_rc_instance_init, .class_init =3D aspeed_pcie_rc_class_init, }; =20 @@ -455,6 +500,9 @@ static void aspeed_pcie_cfg_realize(DeviceState *dev, E= rror **errp) object_property_set_bool(OBJECT(&s->rc), "has-rd", apc->rc_has_rd, &error_abort); + object_property_set_int(OBJECT(&s->rc), "rp-addr", + apc->rc_rp_addr, + &error_abort); if (!sysbus_realize(SYS_BUS_DEVICE(&s->rc), errp)) { return; } @@ -488,6 +536,7 @@ static void aspeed_pcie_cfg_class_init(ObjectClass *kla= ss, const void *data) apc->nr_regs =3D 0x100 >> 2; apc->rc_bus_nr =3D 0x80; apc->rc_has_rd =3D true; + apc->rc_rp_addr =3D PCI_DEVFN(8, 0); } =20 static const TypeInfo aspeed_pcie_cfg_info =3D { @@ -626,6 +675,7 @@ static void aspeed_pcie_register_types(void) { type_register_static(&aspeed_pcie_rc_info); type_register_static(&aspeed_pcie_root_device_info); + type_register_static(&aspeed_pcie_root_port_info); type_register_static(&aspeed_pcie_cfg_info); type_register_static(&aspeed_pcie_phy_info); } --=20 2.51.0