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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1759164799; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=LMQ09e9vXh5/byIKtF+KkYbM5QrTWVZAKyzfEhkyjlU=; b=bWfrQ6ACDnrv6HFffbgcoUEBrAmtX3ESjy8ai3jxDMPfMW7V0D6OY4WdLbzDYmAZ2XHSTv uJs+wPzIWkGAJoPCM4EqK0TXjU9hY0+Zh5++XweDuVNhYkffSg4Zgs2VdoWVI1Ko0GCKJv r+C1HaarMDGNbRYsH/RZifPIQ3md9cA= X-MC-Unique: Fwu6cq77PbWCGStKNblhiw-1 X-Mimecast-MFC-AGG-ID: Fwu6cq77PbWCGStKNblhiw_1759164795 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 17/32] hw/pci-host/aspeed: Add AST2600 PCIe Root Device support Date: Mon, 29 Sep 2025 18:52:15 +0200 Message-ID: <20250929165230.797471-18-clg@redhat.com> In-Reply-To: <20250929165230.797471-1-clg@redhat.com> References: <20250929165230.797471-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.513, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1759165395258116600 From: Jamin Lin Introduce a PCIe Root Device for AST2600 platform. The AST2600 root complex exposes a PCIe root device at bus 80, devfn 0. This root device is implemented as a child of the PCIe RC and modeled as a host bridge PCI function (class_id =3D PCI_CLASS_BRIDGE_HOST). Key changes: - Add a new device type "aspeed.pcie-root-device". - Instantiate the root device as part of AspeedPCIERcState. - Initialize it during RC realize() and attach it to the root bus. - Mark the root device as non-user-creatable. - Add RC boolean property "has-rd" to control whether the Root Device is created (platforms can enable/disable it as needed). Note: Only AST2600 implements this PCIe root device. AST2700 does not provide one. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20250919093017.338309-5-jamin_lin@= aspeedtech.com Signed-off-by: C=C3=A9dric Le Goater --- include/hw/pci-host/aspeed_pcie.h | 11 ++++++ hw/pci-host/aspeed_pcie.c | 56 +++++++++++++++++++++++++++++++ 2 files changed, 67 insertions(+) diff --git a/include/hw/pci-host/aspeed_pcie.h b/include/hw/pci-host/aspeed= _pcie.h index 850d579189eb..fe30ac02aeee 100644 --- a/include/hw/pci-host/aspeed_pcie.h +++ b/include/hw/pci-host/aspeed_pcie.h @@ -40,6 +40,13 @@ typedef struct AspeedPCIERegMap { AspeedPCIERcRegs rc; } AspeedPCIERegMap; =20 +#define TYPE_ASPEED_PCIE_ROOT_DEVICE "aspeed.pcie-root-device" +OBJECT_DECLARE_SIMPLE_TYPE(AspeedPCIERootDeviceState, ASPEED_PCIE_ROOT_DEV= ICE); + +struct AspeedPCIERootDeviceState { + PCIBridge parent_obj; +}; + #define TYPE_ASPEED_PCIE_RC "aspeed.pcie-rc" OBJECT_DECLARE_SIMPLE_TYPE(AspeedPCIERcState, ASPEED_PCIE_RC); =20 @@ -53,7 +60,10 @@ struct AspeedPCIERcState { =20 uint32_t bus_nr; char name[16]; + bool has_rd; qemu_irq irq; + + AspeedPCIERootDeviceState root_device; }; =20 /* Bridge between AHB bus and PCIe RC. */ @@ -79,6 +89,7 @@ struct AspeedPCIECfgClass { =20 uint64_t rc_bus_nr; uint64_t nr_regs; + bool rc_has_rd; }; =20 #define TYPE_ASPEED_PCIE_PHY "aspeed.pcie-phy" diff --git a/hw/pci-host/aspeed_pcie.c b/hw/pci-host/aspeed_pcie.c index c3e92ee44926..6e563a07a3f2 100644 --- a/hw/pci-host/aspeed_pcie.c +++ b/hw/pci-host/aspeed_pcie.c @@ -25,6 +25,44 @@ #include "hw/pci/msi.h" #include "trace.h" =20 +/* + * PCIe Root Device + * This device exists only on AST2600. + */ + +static void aspeed_pcie_root_device_class_init(ObjectClass *klass, + const void *data) +{ + PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); + DeviceClass *dc =3D DEVICE_CLASS(klass); + + set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); + dc->desc =3D "ASPEED PCIe Root Device"; + k->vendor_id =3D PCI_VENDOR_ID_ASPEED; + k->device_id =3D 0x2600; + k->class_id =3D PCI_CLASS_BRIDGE_HOST; + k->subsystem_vendor_id =3D k->vendor_id; + k->subsystem_id =3D k->device_id; + k->revision =3D 0; + + /* + * PCI-facing part of the host bridge, + * not usable without the host-facing part + */ + dc->user_creatable =3D false; +} + +static const TypeInfo aspeed_pcie_root_device_info =3D { + .name =3D TYPE_ASPEED_PCIE_ROOT_DEVICE, + .parent =3D TYPE_PCI_DEVICE, + .instance_size =3D sizeof(AspeedPCIERootDeviceState), + .class_init =3D aspeed_pcie_root_device_class_init, + .interfaces =3D (const InterfaceInfo[]) { + { INTERFACE_CONVENTIONAL_PCI_DEVICE }, + { }, + }, +}; + /* * PCIe Root Complex (RC) */ @@ -94,6 +132,18 @@ static void aspeed_pcie_rc_realize(DeviceState *dev, Er= ror **errp) aspeed_pcie_rc_map_irq, rc, &rc->mmio, &rc->io, 0, 4, TYPE_PCIE_BUS); pci->bus->flags |=3D PCI_BUS_EXTENDED_CONFIG_SPACE; + + /* setup root device */ + if (rc->has_rd) { + object_initialize_child(OBJECT(rc), "root_device", &rc->root_devic= e, + TYPE_ASPEED_PCIE_ROOT_DEVICE); + qdev_prop_set_int32(DEVICE(&rc->root_device), "addr", + PCI_DEVFN(0, 0)); + qdev_prop_set_bit(DEVICE(&rc->root_device), "multifunction", false= ); + if (!qdev_realize(DEVICE(&rc->root_device), BUS(pci->bus), errp)) { + return; + } + } } =20 static const char *aspeed_pcie_rc_root_bus_path(PCIHostState *host_bridge, @@ -110,6 +160,7 @@ static const char *aspeed_pcie_rc_root_bus_path(PCIHost= State *host_bridge, =20 static const Property aspeed_pcie_rc_props[] =3D { DEFINE_PROP_UINT32("bus-nr", AspeedPCIERcState, bus_nr, 0), + DEFINE_PROP_BOOL("has-rd", AspeedPCIERcState, has_rd, 0), }; =20 static void aspeed_pcie_rc_class_init(ObjectClass *klass, const void *data) @@ -401,6 +452,9 @@ static void aspeed_pcie_cfg_realize(DeviceState *dev, E= rror **errp) object_property_set_int(OBJECT(&s->rc), "bus-nr", apc->rc_bus_nr, &error_abort); + object_property_set_bool(OBJECT(&s->rc), "has-rd", + apc->rc_has_rd, + &error_abort); if (!sysbus_realize(SYS_BUS_DEVICE(&s->rc), errp)) { return; } @@ -433,6 +487,7 @@ static void aspeed_pcie_cfg_class_init(ObjectClass *kla= ss, const void *data) apc->reg_map =3D &aspeed_regmap; apc->nr_regs =3D 0x100 >> 2; apc->rc_bus_nr =3D 0x80; + apc->rc_has_rd =3D true; } =20 static const TypeInfo aspeed_pcie_cfg_info =3D { @@ -570,6 +625,7 @@ static const TypeInfo aspeed_pcie_phy_info =3D { static void aspeed_pcie_register_types(void) { type_register_static(&aspeed_pcie_rc_info); + type_register_static(&aspeed_pcie_root_device_info); type_register_static(&aspeed_pcie_cfg_info); type_register_static(&aspeed_pcie_phy_info); } --=20 2.51.0