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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(1800799024)(82310400026)(36860700013)(376014)(7416014); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Sep 2025 13:39:52.8790 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 509fbfd8-dcc8-4c6e-aff6-08ddff5dab75 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000009A.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV3PR12MB9354 Received-SPF: permerror client-ip=2a01:111:f403:c105::1; envelope-from=skolothumtho@nvidia.com; helo=CH1PR05CU001.outbound.protection.outlook.com X-Spam_score_int: -15 X-Spam_score: -1.6 X-Spam_bar: - X-Spam_report: (-1.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.513, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, SPF_HELO_PASS=-0.001, T_SPF_TEMPERROR=0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1759153610498116600 From: Nicolin Chen Implement a set_iommu_device callback: -If found an existing viommu reuse that. -Else, Allocate a vIOMMU with the nested parent S2 hwpt allocated by VFIO. Though, iommufd=E2=80=99s vIOMMU model supports nested translation by encapsulating a S2 nesting parent HWPT, devices cannot attach to this parent HWPT directly. So two proxy nested HWPTs (bypass and abort) are allocated to handle device attachments. -And add the dev to viommu device list Also add an unset_iommu_device to unwind/cleanup above. Signed-off-by: Nicolin Chen Signed-off-by: Shameer Kolothum Reviewed-by: Jonathan Cameron --- hw/arm/smmuv3-accel.c | 150 ++++++++++++++++++++++++++++++++++++++++ hw/arm/smmuv3-accel.h | 17 +++++ hw/arm/trace-events | 4 ++ include/hw/arm/smmuv3.h | 1 + 4 files changed, 172 insertions(+) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 6b0e512d86..81fa738f6f 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -8,6 +8,7 @@ =20 #include "qemu/osdep.h" #include "qemu/error-report.h" +#include "trace.h" =20 #include "hw/arm/smmuv3.h" #include "hw/iommu.h" @@ -17,6 +18,9 @@ =20 #include "smmuv3-accel.h" =20 +#define SMMU_STE_VALID (1ULL << 0) +#define SMMU_STE_CFG_BYPASS (1ULL << 3) + static SMMUv3AccelDevice *smmuv3_accel_get_dev(SMMUState *bs, SMMUPciBus *= sbus, PCIBus *bus, int devfn) { @@ -35,6 +39,149 @@ static SMMUv3AccelDevice *smmuv3_accel_get_dev(SMMUStat= e *bs, SMMUPciBus *sbus, return accel_dev; } =20 +static bool +smmuv3_accel_dev_alloc_viommu(SMMUv3AccelDevice *accel_dev, + HostIOMMUDeviceIOMMUFD *idev, Error **errp) +{ + struct iommu_hwpt_arm_smmuv3 bypass_data =3D { + .ste =3D { SMMU_STE_CFG_BYPASS | SMMU_STE_VALID, 0x0ULL }, + }; + struct iommu_hwpt_arm_smmuv3 abort_data =3D { + .ste =3D { SMMU_STE_VALID, 0x0ULL }, + }; + SMMUDevice *sdev =3D &accel_dev->sdev; + SMMUState *bs =3D sdev->smmu; + SMMUv3State *s =3D ARM_SMMUV3(bs); + SMMUv3AccelState *s_accel =3D s->s_accel; + uint32_t s2_hwpt_id =3D idev->hwpt_id; + SMMUViommu *viommu; + uint32_t viommu_id; + + if (s_accel->viommu) { + accel_dev->viommu =3D s_accel->viommu; + return true; + } + + if (!iommufd_backend_alloc_viommu(idev->iommufd, idev->devid, + IOMMU_VIOMMU_TYPE_ARM_SMMUV3, + s2_hwpt_id, &viommu_id, errp)) { + return false; + } + + viommu =3D g_new0(SMMUViommu, 1); + viommu->core.viommu_id =3D viommu_id; + viommu->core.s2_hwpt_id =3D s2_hwpt_id; + viommu->core.iommufd =3D idev->iommufd; + + if (!iommufd_backend_alloc_hwpt(idev->iommufd, idev->devid, + viommu->core.viommu_id, 0, + IOMMU_HWPT_DATA_ARM_SMMUV3, + sizeof(abort_data), &abort_data, + &viommu->abort_hwpt_id, errp)) { + goto free_viommu; + } + + if (!iommufd_backend_alloc_hwpt(idev->iommufd, idev->devid, + viommu->core.viommu_id, 0, + IOMMU_HWPT_DATA_ARM_SMMUV3, + sizeof(bypass_data), &bypass_data, + &viommu->bypass_hwpt_id, errp)) { + goto free_abort_hwpt; + } + + viommu->iommufd =3D idev->iommufd; + + s_accel->viommu =3D viommu; + accel_dev->viommu =3D viommu; + return true; + +free_abort_hwpt: + iommufd_backend_free_id(idev->iommufd, viommu->abort_hwpt_id); +free_viommu: + iommufd_backend_free_id(idev->iommufd, viommu->core.viommu_id); + g_free(viommu); + return false; +} + +static bool smmuv3_accel_set_iommu_device(PCIBus *bus, void *opaque, int d= evfn, + HostIOMMUDevice *hiod, Error **e= rrp) +{ + HostIOMMUDeviceIOMMUFD *idev =3D HOST_IOMMU_DEVICE_IOMMUFD(hiod); + SMMUState *bs =3D opaque; + SMMUv3State *s =3D ARM_SMMUV3(bs); + SMMUv3AccelState *s_accel =3D s->s_accel; + SMMUPciBus *sbus =3D smmu_get_sbus(bs, bus); + SMMUv3AccelDevice *accel_dev =3D smmuv3_accel_get_dev(bs, sbus, bus, d= evfn); + SMMUDevice *sdev =3D &accel_dev->sdev; + uint16_t sid =3D smmu_get_sid(sdev); + + if (!idev) { + return true; + } + + if (accel_dev->idev) { + if (accel_dev->idev !=3D idev) { + error_setg(errp, "Device 0x%x already has an associated IOMMU = dev", + sid); + return false; + } + return true; + } + + if (!smmuv3_accel_dev_alloc_viommu(accel_dev, idev, errp)) { + error_setg(errp, "Device 0x%x: Unable to alloc viommu", sid); + return false; + } + + accel_dev->idev =3D idev; + QLIST_INSERT_HEAD(&s_accel->viommu->device_list, accel_dev, next); + trace_smmuv3_accel_set_iommu_device(devfn, sid); + return true; +} + +static void smmuv3_accel_unset_iommu_device(PCIBus *bus, void *opaque, + int devfn) +{ + SMMUState *bs =3D opaque; + SMMUv3State *s =3D ARM_SMMUV3(bs); + SMMUPciBus *sbus =3D g_hash_table_lookup(bs->smmu_pcibus_by_busptr, bu= s); + SMMUv3AccelDevice *accel_dev; + SMMUViommu *viommu; + SMMUDevice *sdev; + uint16_t sid; + + if (!sbus) { + return; + } + + sdev =3D sbus->pbdev[devfn]; + if (!sdev) { + return; + } + + sid =3D smmu_get_sid(sdev); + accel_dev =3D container_of(sdev, SMMUv3AccelDevice, sdev); + if (!host_iommu_device_iommufd_attach_hwpt(accel_dev->idev, + accel_dev->idev->hwpt_id, + NULL)) { + error_report("Unable to attach dev 0x%x to the default HW pagetabl= e", + sid); + } + + accel_dev->idev =3D NULL; + QLIST_REMOVE(accel_dev, next); + trace_smmuv3_accel_unset_iommu_device(devfn, sid); + + viommu =3D s->s_accel->viommu; + if (QLIST_EMPTY(&viommu->device_list)) { + iommufd_backend_free_id(viommu->iommufd, viommu->bypass_hwpt_id); + iommufd_backend_free_id(viommu->iommufd, viommu->abort_hwpt_id); + iommufd_backend_free_id(viommu->iommufd, viommu->core.viommu_id); + g_free(viommu); + s->s_accel->viommu =3D NULL; + } +} + static bool smmuv3_accel_pdev_allowed(PCIDevice *pdev, bool *vfio_pci) { =20 @@ -121,6 +268,8 @@ static uint64_t smmuv3_accel_get_viommu_flags(void *opa= que) static const PCIIOMMUOps smmuv3_accel_ops =3D { .get_address_space =3D smmuv3_accel_find_add_as, .get_viommu_flags =3D smmuv3_accel_get_viommu_flags, + .set_iommu_device =3D smmuv3_accel_set_iommu_device, + .unset_iommu_device =3D smmuv3_accel_unset_iommu_device, }; =20 void smmuv3_accel_init(SMMUv3State *s) @@ -128,4 +277,5 @@ void smmuv3_accel_init(SMMUv3State *s) SMMUState *bs =3D ARM_SMMU(s); =20 bs->iommu_ops =3D &smmuv3_accel_ops; + s->s_accel =3D g_new0(SMMUv3AccelState, 1); } diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h index 70da16960f..3c8506d1e6 100644 --- a/hw/arm/smmuv3-accel.h +++ b/hw/arm/smmuv3-accel.h @@ -10,12 +10,29 @@ #define HW_ARM_SMMUV3_ACCEL_H =20 #include "hw/arm/smmu-common.h" +#include "system/iommufd.h" +#include #include CONFIG_DEVICES =20 +typedef struct SMMUViommu { + IOMMUFDBackend *iommufd; + IOMMUFDViommu core; + uint32_t bypass_hwpt_id; + uint32_t abort_hwpt_id; + QLIST_HEAD(, SMMUv3AccelDevice) device_list; +} SMMUViommu; + typedef struct SMMUv3AccelDevice { SMMUDevice sdev; + HostIOMMUDeviceIOMMUFD *idev; + SMMUViommu *viommu; + QLIST_ENTRY(SMMUv3AccelDevice) next; } SMMUv3AccelDevice; =20 +typedef struct SMMUv3AccelState { + SMMUViommu *viommu; +} SMMUv3AccelState; + #ifdef CONFIG_ARM_SMMUV3_ACCEL void smmuv3_accel_init(SMMUv3State *s); #else diff --git a/hw/arm/trace-events b/hw/arm/trace-events index f3386bd7ae..86370d448a 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -66,6 +66,10 @@ smmuv3_notify_flag_del(const char *iommu) "DEL SMMUNotif= ier node for iommu mr=3D%s smmuv3_inv_notifiers_iova(const char *name, int asid, int vmid, uint64_t i= ova, uint8_t tg, uint64_t num_pages, int stage) "iommu mr=3D%s asid=3D%d vm= id=3D%d iova=3D0x%"PRIx64" tg=3D%d num_pages=3D0x%"PRIx64" stage=3D%d" smmu_reset_exit(void) "" =20 +#smmuv3-accel.c +smmuv3_accel_set_iommu_device(int devfn, uint32_t sid) "devfn=3D0x%x (sid= =3D0x%x)" +smmuv3_accel_unset_iommu_device(int devfn, uint32_t sid) "devfn=3D0x%x (si= d=3D0x%x)" + # strongarm.c strongarm_uart_update_parameters(const char *label, int speed, char parity= , int data_bits, int stop_bits) "%s speed=3D%d parity=3D%c data=3D%d stop= =3D%d" strongarm_ssp_read_underrun(void) "SSP rx underrun" diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index bb7076286b..5f3e9089a7 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -66,6 +66,7 @@ struct SMMUv3State { =20 /* SMMU has HW accelerator support for nested S1 + s2 */ bool accel; + struct SMMUv3AccelState *s_accel; }; =20 typedef enum { --=20 2.43.0