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charset="utf-8" From: Eric Auger To handle SMMUv3 nested stage support it is practical to expose the guest with reserved memory regions (RMRs) covering the IOVAs used by the host kernel to map physical MSI doorbells. Those IOVAs belong to [0x8000000, 0x8100000] matching MSI_IOVA_BASE and MSI_IOVA_LENGTH definitions in kernel arm-smmu-v3 driver. This is the window used to allocate IOVAs matching physical MSI doorbells. With those RMRs, the guest is forced to use a flat mapping for this range. Hence the assigned device is programmed with one IOVA from this range. Stage 1, owned by the guest has a flat mapping for this IOVA. Stage2, owned by the VMM then enforces a mapping from this IOVA to the physical MSI doorbell. The creation of those RMR nodes is only relevant if nested stage SMMU is in use, along with VFIO. As VFIO devices can be hotplugged, all RMRs need to be created in advance. Signed-off-by: Eric Auger Suggested-by: Jean-Philippe Brucker Signed-off-by: Nicolin Chen Signed-off-by: Shameer Kolothum Signed-off-by: Shameer Kolothum --- hw/arm/virt-acpi-build.c | 75 ++++++++++++++++++++++++++++++++++++---- 1 file changed, 68 insertions(+), 7 deletions(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index fd03b7f6a9..d0c1e10019 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -264,7 +264,8 @@ static void acpi_dsdt_add_tpm(Aml *scope, VirtMachineSt= ate *vms) * Note that @id_count gets internally subtracted by one, following the sp= ec. */ static void build_iort_id_mapping(GArray *table_data, uint32_t input_base, - uint32_t id_count, uint32_t out_ref) + uint32_t id_count, uint32_t out_ref, + uint32_t flags) { build_append_int_noprefix(table_data, input_base, 4); /* Input base */ /* Number of IDs - The number of IDs in the range minus one */ @@ -272,7 +273,7 @@ static void build_iort_id_mapping(GArray *table_data, u= int32_t input_base, build_append_int_noprefix(table_data, input_base, 4); /* Output base */ build_append_int_noprefix(table_data, out_ref, 4); /* Output Reference= */ /* Flags */ - build_append_int_noprefix(table_data, 0 /* Single mapping (disabled) *= /, 4); + build_append_int_noprefix(table_data, flags, 4); } =20 struct AcpiIortIdMapping { @@ -320,6 +321,7 @@ typedef struct AcpiIortSMMUv3Dev { GArray *rc_smmu_idmaps; /* Offset of the SMMUv3 IORT Node relative to the start of the IORT */ size_t offset; + bool accel; } AcpiIortSMMUv3Dev; =20 /* @@ -374,6 +376,7 @@ static int iort_smmuv3_devices(Object *obj, void *opaqu= e) } =20 bus =3D PCI_BUS(object_property_get_link(obj, "primary-bus", &error_ab= ort)); + sdev.accel =3D object_property_get_bool(obj, "accel", &error_abort); pbus =3D PLATFORM_BUS_DEVICE(vms->platform_bus_dev); sbdev =3D SYS_BUS_DEVICE(obj); sdev.base =3D platform_bus_get_mmio_addr(pbus, sbdev, 0); @@ -447,6 +450,56 @@ static void create_rc_its_idmaps(GArray *its_idmaps, G= Array *smmuv3_devs) } } =20 +static void +build_iort_rmr_nodes(GArray *table_data, GArray *smmuv3_devices, uint32_t = *id) +{ + AcpiIortSMMUv3Dev *sdev; + AcpiIortIdMapping *idmap; + int i; + + for (i =3D 0; i < smmuv3_devices->len; i++) { + sdev =3D &g_array_index(smmuv3_devices, AcpiIortSMMUv3Dev, i); + idmap =3D &g_array_index(sdev->rc_smmu_idmaps, AcpiIortIdMapping, = 0); + int bdf =3D idmap->input_base; + + if (!sdev->accel) { + continue; + } + + /* Table 18 Reserved Memory Range Node */ + build_append_int_noprefix(table_data, 6 /* RMR */, 1); /* Type */ + /* Length */ + build_append_int_noprefix(table_data, 28 + ID_MAPPING_ENTRY_SIZE += 20, + 2); + build_append_int_noprefix(table_data, 3, 1); /* Revision */ + build_append_int_noprefix(table_data, *id, 4); /* Identifier */ + /* Number of ID mappings */ + build_append_int_noprefix(table_data, 1, 4); + /* Reference to ID Array */ + build_append_int_noprefix(table_data, 28, 4); + + /* RMR specific data */ + + /* Flags */ + build_append_int_noprefix(table_data, 0 /* Disallow remapping */, = 4); + /* Number of Memory Range Descriptors */ + build_append_int_noprefix(table_data, 1 , 4); + /* Reference to Memory Range Descriptors */ + build_append_int_noprefix(table_data, 28 + ID_MAPPING_ENTRY_SIZE, = 4); + build_iort_id_mapping(table_data, bdf, idmap->id_count, sdev->offs= et, + 1); + + /* Table 19 Memory Range Descriptor */ + + /* Physical Range offset */ + build_append_int_noprefix(table_data, 0x8000000, 8); + /* Physical Range length */ + build_append_int_noprefix(table_data, 0x100000, 8); + build_append_int_noprefix(table_data, 0, 4); /* Reserved */ + *id +=3D 1; + } +} + /* * Input Output Remapping Table (IORT) * Conforms to "IO Remapping Table System Software on ARM Platforms", @@ -464,7 +517,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) GArray *smmuv3_devs =3D g_array_new(false, true, sizeof(AcpiIortSMMUv3= Dev)); GArray *rc_its_idmaps =3D g_array_new(false, true, sizeof(AcpiIortIdMa= pping)); =20 - AcpiTable table =3D { .sig =3D "IORT", .rev =3D 3, .oem_id =3D vms->oe= m_id, + AcpiTable table =3D { .sig =3D "IORT", .rev =3D 5, .oem_id =3D vms->oe= m_id, .oem_table_id =3D vms->oem_table_id }; /* Table 2 The IORT */ acpi_table_begin(&table, table_data); @@ -490,6 +543,13 @@ build_iort(GArray *table_data, BIOSLinker *linker, Vir= tMachineState *vms) nb_nodes++; /* ITS */ rc_mapping_count +=3D rc_its_idmaps->len; } + /* Calculate RMR nodes required. One per SMMUv3 with accelerated m= ode */ + for (i =3D 0; i < num_smmus; i++) { + sdev =3D &g_array_index(smmuv3_devs, AcpiIortSMMUv3Dev, i); + if (sdev->accel) { + nb_nodes++; + } + } } else { if (vms->its) { nb_nodes =3D 2; /* RC and ITS */ @@ -562,7 +622,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) /* Array of ID mappings */ if (smmu_mapping_count) { /* Output IORT node is the ITS Group node (the first node). */ - build_iort_id_mapping(table_data, 0, 0x10000, IORT_NODE_OFFSET= ); + build_iort_id_mapping(table_data, 0, 0x10000, IORT_NODE_OFFSET= , 0); } } =20 @@ -614,7 +674,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) AcpiIortIdMapping, j); /* Output IORT node is the SMMUv3 node. */ build_iort_id_mapping(table_data, range->input_base, - range->id_count, sdev->offset); + range->id_count, sdev->offset, 0); } } =20 @@ -627,7 +687,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) range =3D &g_array_index(rc_its_idmaps, AcpiIortIdMapping,= i); /* Output IORT node is the ITS Group node (the first node)= . */ build_iort_id_mapping(table_data, range->input_base, - range->id_count, IORT_NODE_OFFSET); + range->id_count, IORT_NODE_OFFSET, 0= ); } } } else { @@ -636,9 +696,10 @@ build_iort(GArray *table_data, BIOSLinker *linker, Vir= tMachineState *vms) * SMMU: RC -> ITS. * Output IORT node is the ITS Group node (the first node). */ - build_iort_id_mapping(table_data, 0, 0x10000, IORT_NODE_OFFSET); + build_iort_id_mapping(table_data, 0, 0x10000, IORT_NODE_OFFSET, 0); } =20 + build_iort_rmr_nodes(table_data, smmuv3_devs, &id); acpi_table_end(linker, &table); g_array_free(rc_its_idmaps, true); for (i =3D 0; i < num_smmus; i++) { --=20 2.43.0