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charset="utf-8" From: Nicolin Chen Add a helper to allocate a viommu object. Also introduce a struct IOMMUFDViommu that can be used later by vendor IOMMU implementations. Signed-off-by: Nicolin Chen Reviewed-by: Eric Auger Signed-off-by: Shameer Kolothum Signed-off-by: Shameer Kolothum Reviewed-by: Jonathan Cameron Tested-by: Zhangfei Gao --- backends/iommufd.c | 26 ++++++++++++++++++++++++++ backends/trace-events | 1 + include/system/iommufd.h | 14 ++++++++++++++ 3 files changed, 41 insertions(+) diff --git a/backends/iommufd.c b/backends/iommufd.c index 2a33c7ab0b..7b2e5ace2d 100644 --- a/backends/iommufd.c +++ b/backends/iommufd.c @@ -446,6 +446,32 @@ bool iommufd_backend_invalidate_cache(IOMMUFDBackend *= be, uint32_t id, return !ret; } =20 +bool iommufd_backend_alloc_viommu(IOMMUFDBackend *be, uint32_t dev_id, + uint32_t viommu_type, uint32_t hwpt_id, + uint32_t *out_viommu_id, Error **errp) +{ + int ret; + struct iommu_viommu_alloc alloc_viommu =3D { + .size =3D sizeof(alloc_viommu), + .type =3D viommu_type, + .dev_id =3D dev_id, + .hwpt_id =3D hwpt_id, + }; + + ret =3D ioctl(be->fd, IOMMU_VIOMMU_ALLOC, &alloc_viommu); + + trace_iommufd_backend_alloc_viommu(be->fd, dev_id, viommu_type, hwpt_i= d, + alloc_viommu.out_viommu_id, ret); + if (ret) { + error_setg_errno(errp, errno, "IOMMU_VIOMMU_ALLOC failed"); + return false; + } + + g_assert(out_viommu_id); + *out_viommu_id =3D alloc_viommu.out_viommu_id; + return true; +} + bool host_iommu_device_iommufd_attach_hwpt(HostIOMMUDeviceIOMMUFD *idev, uint32_t hwpt_id, Error **errp) { diff --git a/backends/trace-events b/backends/trace-events index 56132d3fd2..01c2d9bde9 100644 --- a/backends/trace-events +++ b/backends/trace-events @@ -21,3 +21,4 @@ iommufd_backend_free_id(int iommufd, uint32_t id, int ret= ) " iommufd=3D%d id=3D%d (% iommufd_backend_set_dirty(int iommufd, uint32_t hwpt_id, bool start, int r= et) " iommufd=3D%d hwpt=3D%u enable=3D%d (%d)" iommufd_backend_get_dirty_bitmap(int iommufd, uint32_t hwpt_id, uint64_t i= ova, uint64_t size, uint64_t page_size, int ret) " iommufd=3D%d hwpt=3D%u i= ova=3D0x%"PRIx64" size=3D0x%"PRIx64" page_size=3D0x%"PRIx64" (%d)" iommufd_backend_invalidate_cache(int iommufd, uint32_t id, uint32_t data_t= ype, uint32_t entry_len, uint32_t entry_num, uint32_t done_num, uint64_t da= ta_ptr, int ret) " iommufd=3D%d id=3D%u data_type=3D%u entry_len=3D%u entry= _num=3D%u done_num=3D%u data_ptr=3D0x%"PRIx64" (%d)" +iommufd_backend_alloc_viommu(int iommufd, uint32_t dev_id, uint32_t type, = uint32_t hwpt_id, uint32_t viommu_id, int ret) " iommufd=3D%d type=3D%u dev= _id=3D%u hwpt_id=3D%u viommu_id=3D%u (%d)" diff --git a/include/system/iommufd.h b/include/system/iommufd.h index c9c72ffc45..dfe1dc2850 100644 --- a/include/system/iommufd.h +++ b/include/system/iommufd.h @@ -38,6 +38,16 @@ struct IOMMUFDBackend { /*< public >*/ }; =20 +/* + * Virtual IOMMU object that respresents physical IOMMU's virtualization + * support + */ +typedef struct IOMMUFDViommu { + IOMMUFDBackend *iommufd; + uint32_t s2_hwpt_id; /* Id of stage 2 HWPT */ + uint32_t viommu_id; /* virtual IOMMU ID of allocated object */ +} IOMMUFDViommu; + bool iommufd_backend_connect(IOMMUFDBackend *be, Error **errp); void iommufd_backend_disconnect(IOMMUFDBackend *be); =20 @@ -59,6 +69,10 @@ bool iommufd_backend_alloc_hwpt(IOMMUFDBackend *be, uint= 32_t dev_id, uint32_t data_type, uint32_t data_len, void *data_ptr, uint32_t *out_hwpt, Error **errp); +bool iommufd_backend_alloc_viommu(IOMMUFDBackend *be, uint32_t dev_id, + uint32_t viommu_type, uint32_t hwpt_id, + uint32_t *out_hwpt, Error **errp); + bool iommufd_backend_set_dirty_tracking(IOMMUFDBackend *be, uint32_t hwpt_= id, bool start, Error **errp); bool iommufd_backend_get_dirty_bitmap(IOMMUFDBackend *be, uint32_t hwpt_id, --=20 2.43.0 From nobody Fri Nov 14 23:30:28 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" From: Nicolin Chen Add a helper to allocate an iommufd device's virtual device (in the user space) per a viommu instance. While at it, introduce a struct IOMMUFDVdev for later use by vendor IOMMU implementations. Signed-off-by: Nicolin Chen Reviewed-by: Eric Auger Signed-off-by: Shameer Kolothum Signed-off-by: Shameer Kolothum Reviewed-by: Jonathan Cameron Tested-by: Zhangfei Gao --- backends/iommufd.c | 27 +++++++++++++++++++++++++++ backends/trace-events | 1 + include/system/iommufd.h | 12 ++++++++++++ 3 files changed, 40 insertions(+) diff --git a/backends/iommufd.c b/backends/iommufd.c index 7b2e5ace2d..d3029d4658 100644 --- a/backends/iommufd.c +++ b/backends/iommufd.c @@ -472,6 +472,33 @@ bool iommufd_backend_alloc_viommu(IOMMUFDBackend *be, = uint32_t dev_id, return true; } =20 +bool iommufd_backend_alloc_vdev(IOMMUFDBackend *be, uint32_t dev_id, + uint32_t viommu_id, uint64_t virt_id, + uint32_t *out_vdev_id, Error **errp) +{ + int ret; + struct iommu_vdevice_alloc alloc_vdev =3D { + .size =3D sizeof(alloc_vdev), + .viommu_id =3D viommu_id, + .dev_id =3D dev_id, + .virt_id =3D virt_id, + }; + + ret =3D ioctl(be->fd, IOMMU_VDEVICE_ALLOC, &alloc_vdev); + + trace_iommufd_backend_alloc_vdev(be->fd, dev_id, viommu_id, virt_id, + alloc_vdev.out_vdevice_id, ret); + + if (ret) { + error_setg_errno(errp, errno, "IOMMU_VDEVICE_ALLOC failed"); + return false; + } + + g_assert(out_vdev_id); + *out_vdev_id =3D alloc_vdev.out_vdevice_id; + return true; +} + bool host_iommu_device_iommufd_attach_hwpt(HostIOMMUDeviceIOMMUFD *idev, uint32_t hwpt_id, Error **errp) { diff --git a/backends/trace-events b/backends/trace-events index 01c2d9bde9..8408dc8701 100644 --- a/backends/trace-events +++ b/backends/trace-events @@ -22,3 +22,4 @@ iommufd_backend_set_dirty(int iommufd, uint32_t hwpt_id, = bool start, int ret) " iommufd_backend_get_dirty_bitmap(int iommufd, uint32_t hwpt_id, uint64_t i= ova, uint64_t size, uint64_t page_size, int ret) " iommufd=3D%d hwpt=3D%u i= ova=3D0x%"PRIx64" size=3D0x%"PRIx64" page_size=3D0x%"PRIx64" (%d)" iommufd_backend_invalidate_cache(int iommufd, uint32_t id, uint32_t data_t= ype, uint32_t entry_len, uint32_t entry_num, uint32_t done_num, uint64_t da= ta_ptr, int ret) " iommufd=3D%d id=3D%u data_type=3D%u entry_len=3D%u entry= _num=3D%u done_num=3D%u data_ptr=3D0x%"PRIx64" (%d)" iommufd_backend_alloc_viommu(int iommufd, uint32_t dev_id, uint32_t type, = uint32_t hwpt_id, uint32_t viommu_id, int ret) " iommufd=3D%d type=3D%u dev= _id=3D%u hwpt_id=3D%u viommu_id=3D%u (%d)" +iommufd_backend_alloc_vdev(int iommufd, uint32_t dev_id, uint32_t viommu_i= d, uint64_t virt_id, uint32_t vdev_id, int ret) " iommufd=3D%d dev_id=3D%u = viommu_id=3D%u virt_id=3D0x%"PRIx64" vdev_id=3D%u (%d)" diff --git a/include/system/iommufd.h b/include/system/iommufd.h index dfe1dc2850..e852193f35 100644 --- a/include/system/iommufd.h +++ b/include/system/iommufd.h @@ -48,6 +48,14 @@ typedef struct IOMMUFDViommu { uint32_t viommu_id; /* virtual IOMMU ID of allocated object */ } IOMMUFDViommu; =20 +/* + * Virtual device object for a physical device bind to a vIOMMU. + */ +typedef struct IOMMUFDVdev { + uint32_t vdev_id; /* Virtual device ID */ + uint32_t dev_id; /* Physical device ID */ +} IOMMUFDVdev; + bool iommufd_backend_connect(IOMMUFDBackend *be, Error **errp); void iommufd_backend_disconnect(IOMMUFDBackend *be); =20 @@ -73,6 +81,10 @@ bool iommufd_backend_alloc_viommu(IOMMUFDBackend *be, ui= nt32_t dev_id, uint32_t viommu_type, uint32_t hwpt_id, uint32_t *out_hwpt, Error **errp); =20 +bool iommufd_backend_alloc_vdev(IOMMUFDBackend *be, uint32_t dev_id, + uint32_t viommu_id, uint64_t virt_id, + uint32_t *out_vdev_id, Error **errp); + bool iommufd_backend_set_dirty_tracking(IOMMUFDBackend *be, uint32_t hwpt_= id, bool start, Error **errp); bool iommufd_backend_get_dirty_bitmap(IOMMUFDBackend *be, uint32_t hwpt_id, --=20 2.43.0 From nobody Fri Nov 14 23:30:28 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Subsequent patches for smmuv3 accel support will make use of this. Signed-off-by: Nicolin Chen Reviewed-by: Eric Auger Signed-off-by: Shameer Kolothum Signed-off-by: Shameer Kolothum Reviewed-by: Jonathan Cameron Tested-by: Zhangfei Gao --- hw/arm/smmu-common.c | 44 +++++++++++++++++++++--------------- include/hw/arm/smmu-common.h | 6 +++++ 2 files changed, 32 insertions(+), 18 deletions(-) diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index 62a7612184..59d6147ec9 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -847,12 +847,24 @@ SMMUPciBus *smmu_find_smmu_pcibus(SMMUState *s, uint8= _t bus_num) return NULL; } =20 -static AddressSpace *smmu_find_add_as(PCIBus *bus, void *opaque, int devfn) +void smmu_init_sdev(SMMUState *s, SMMUDevice *sdev, PCIBus *bus, int devfn) { - SMMUState *s =3D opaque; - SMMUPciBus *sbus =3D g_hash_table_lookup(s->smmu_pcibus_by_busptr, bus= ); - SMMUDevice *sdev; static unsigned int index; + g_autofree char *name =3D g_strdup_printf("%s-%d-%d", s->mrtypename, d= evfn, + index++); + sdev->smmu =3D s; + sdev->bus =3D bus; + sdev->devfn =3D devfn; + + memory_region_init_iommu(&sdev->iommu, sizeof(sdev->iommu), + s->mrtypename, OBJECT(s), name, UINT64_MAX); + address_space_init(&sdev->as, MEMORY_REGION(&sdev->iommu), name); + trace_smmu_add_mr(name); +} + +SMMUPciBus *smmu_get_sbus(SMMUState *s, PCIBus *bus) +{ + SMMUPciBus *sbus =3D g_hash_table_lookup(s->smmu_pcibus_by_busptr, bus= ); =20 if (!sbus) { sbus =3D g_malloc0(sizeof(SMMUPciBus) + @@ -861,23 +873,19 @@ static AddressSpace *smmu_find_add_as(PCIBus *bus, vo= id *opaque, int devfn) g_hash_table_insert(s->smmu_pcibus_by_busptr, bus, sbus); } =20 + return sbus; +} + +static AddressSpace *smmu_find_add_as(PCIBus *bus, void *opaque, int devfn) +{ + SMMUState *s =3D opaque; + SMMUPciBus *sbus =3D smmu_get_sbus(s, bus); + SMMUDevice *sdev; + sdev =3D sbus->pbdev[devfn]; if (!sdev) { - char *name =3D g_strdup_printf("%s-%d-%d", s->mrtypename, devfn, i= ndex++); - sdev =3D sbus->pbdev[devfn] =3D g_new0(SMMUDevice, 1); - - sdev->smmu =3D s; - sdev->bus =3D bus; - sdev->devfn =3D devfn; - - memory_region_init_iommu(&sdev->iommu, sizeof(sdev->iommu), - s->mrtypename, - OBJECT(s), name, UINT64_MAX); - address_space_init(&sdev->as, - MEMORY_REGION(&sdev->iommu), name); - trace_smmu_add_mr(name); - g_free(name); + smmu_init_sdev(s, sdev, bus, devfn); } =20 return &sdev->as; diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index 80d0fecfde..c6f899e403 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -180,6 +180,12 @@ OBJECT_DECLARE_TYPE(SMMUState, SMMUBaseClass, ARM_SMMU) /* Return the SMMUPciBus handle associated to a PCI bus number */ SMMUPciBus *smmu_find_smmu_pcibus(SMMUState *s, uint8_t bus_num); =20 +/* Return the SMMUPciBus handle associated to a PCI bus */ +SMMUPciBus *smmu_get_sbus(SMMUState *s, PCIBus *bus); + +/* Initialize SMMUDevice handle associated to a SMMUPCIBus */ +void smmu_init_sdev(SMMUState *s, SMMUDevice *sdev, PCIBus *bus, int devfn= ); + /* Return the stream ID of an SMMU device */ static inline uint16_t smmu_get_sid(SMMUDevice *sdev) { --=20 2.43.0 From nobody Fri Nov 14 23:30:28 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(7416014)(376014)(82310400026)(1800799024)(36860700013); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Sep 2025 13:39:28.3070 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8dee559c-118e-431c-88e2-08ddff5d9cd0 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000099.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB6222 Received-SPF: permerror client-ip=2a01:111:f403:c10d::1; envelope-from=skolothumtho@nvidia.com; helo=SN4PR2101CU001.outbound.protection.outlook.com X-Spam_score_int: -15 X-Spam_score: -1.6 X-Spam_bar: - X-Spam_report: (-1.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.513, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1759153408814116600 And set to the current default smmu_ops. No functional change intended. This will allow=C2=A0SMMUv3 accel implementation=C2=A0to set a=C2=A0differe= nt=C2=A0iommu ops later. Signed-off-by: Shameer Kolothum Reviewed-by: Eric Auger Reviewed-by: Jonathan Cameron Reviewed-by: Nicolin Chen Tested-by: Zhangfei Gao --- hw/arm/smmu-common.c | 7 +++++-- include/hw/arm/smmu-common.h | 1 + 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index 59d6147ec9..4d6516443e 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -952,6 +952,9 @@ static void smmu_base_realize(DeviceState *dev, Error *= *errp) return; } =20 + if (!s->iommu_ops) { + s->iommu_ops =3D &smmu_ops; + } /* * We only allow default PCIe Root Complex(pcie.0) or pxb-pcie based e= xtra * root complexes to be associated with SMMU. @@ -971,9 +974,9 @@ static void smmu_base_realize(DeviceState *dev, Error *= *errp) } =20 if (s->smmu_per_bus) { - pci_setup_iommu_per_bus(pci_bus, &smmu_ops, s); + pci_setup_iommu_per_bus(pci_bus, s->iommu_ops, s); } else { - pci_setup_iommu(pci_bus, &smmu_ops, s); + pci_setup_iommu(pci_bus, s->iommu_ops, s); } return; } diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index c6f899e403..75b83b2b4a 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -162,6 +162,7 @@ struct SMMUState { uint8_t bus_num; PCIBus *primary_bus; bool smmu_per_bus; /* SMMU is specific to the primary_bus */ + const PCIIOMMUOps *iommu_ops; }; =20 struct SMMUBaseClass { --=20 2.43.0 From nobody Fri Nov 14 23:30:28 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass(p=reject dis=none) header.from=nvidia.com ARC-Seal: i=2; a=rsa-sha256; t=1759153331; cv=pass; d=zohomail.com; s=zohoarc; b=EmOjasjV9z/VD9XQdEku2K4jBJXzsqrT0eEBlDi5JrafFD9HpdIlWj0QFKX/GD6lIMVVs0PeXGyK3xp861e+ukjIoxecQEyxa3kqHhnKyDDfh08bizCJ6EGTx4tDc/HAVCBmeDvm8iUR5lLjMFI1jUSHA1nF4lqqElTeV2HhQqU= ARC-Message-Signature: i=2; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(376014)(7416014)(36860700013)(82310400026)(1800799024); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Sep 2025 13:39:35.0227 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c3e93561-2083-4996-8b73-08ddff5da0d4 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000009A.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY3PR12MB9678 Received-SPF: permerror client-ip=2a01:111:f403:c000::1; envelope-from=skolothumtho@nvidia.com; helo=BYAPR05CU005.outbound.protection.outlook.com X-Spam_score_int: -15 X-Spam_score: -1.6 X-Spam_bar: - X-Spam_report: (-1.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.513, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1759153331921116600 Set up dedicated PCIIOMMUOps for the accel SMMUv3, since it will need different callback handling in upcoming patches. This also adds a CONFIG_ARM_SMMUV3_ACCEL build option so the feature can be disabled at compile time. Because we now include CONFIG_DEVICES in the header to check for ARM_SMMUV3_ACCEL, the meson file entry for smmuv3.c needs to be changed as well. The =E2=80=9Caccel=E2=80=9D property isn=E2=80=99t user visible yet, it wil= l be introduced in a later patch once all the supporting pieces are ready. Reviewed-by: Nicolin Chen Signed-off-by: Shameer Kolothum Reviewed-by: Eric Auger Reviewed-by: Jonathan Cameron Tested-by: Zhangfei Gao --- hw/arm/Kconfig | 5 ++++ hw/arm/meson.build | 3 ++- hw/arm/smmuv3-accel.c | 52 +++++++++++++++++++++++++++++++++++++++++ hw/arm/smmuv3-accel.h | 27 +++++++++++++++++++++ hw/arm/smmuv3.c | 5 ++++ include/hw/arm/smmuv3.h | 3 +++ 6 files changed, 94 insertions(+), 1 deletion(-) create mode 100644 hw/arm/smmuv3-accel.c create mode 100644 hw/arm/smmuv3-accel.h diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 3baa6c6c74..157c0f3517 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -12,6 +12,7 @@ config ARM_VIRT select ARM_GIC select ACPI select ARM_SMMUV3 + select ARM_SMMUV3_ACCEL select GPIO_KEY select DEVICE_TREE select FW_CFG_DMA @@ -625,6 +626,10 @@ config FSL_IMX8MP_EVK config ARM_SMMUV3 bool =20 +config ARM_SMMUV3_ACCEL + bool + depends on ARM_SMMUV3 && IOMMUFD + config FSL_IMX6UL bool default y diff --git a/hw/arm/meson.build b/hw/arm/meson.build index dc68391305..bcb27c0bf6 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -61,7 +61,8 @@ arm_common_ss.add(when: 'CONFIG_ARMSSE', if_true: files('= armsse.c')) arm_common_ss.add(when: 'CONFIG_FSL_IMX7', if_true: files('fsl-imx7.c', 'm= cimx7d-sabre.c')) arm_common_ss.add(when: 'CONFIG_FSL_IMX8MP', if_true: files('fsl-imx8mp.c'= )) arm_common_ss.add(when: 'CONFIG_FSL_IMX8MP_EVK', if_true: files('imx8mp-ev= k.c')) -arm_common_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmuv3.c')) +arm_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmuv3.c')) +arm_ss.add(when: 'CONFIG_ARM_SMMUV3_ACCEL', if_true: files('smmuv3-accel.c= ')) arm_common_ss.add(when: 'CONFIG_FSL_IMX6UL', if_true: files('fsl-imx6ul.c'= , 'mcimx6ul-evk.c')) arm_common_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_soc.c')) arm_ss.add(when: 'CONFIG_XEN', if_true: files( diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c new file mode 100644 index 0000000000..79f1713be6 --- /dev/null +++ b/hw/arm/smmuv3-accel.c @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2025 Huawei Technologies R & D (UK) Ltd + * Copyright (C) 2025 NVIDIA + * Written by Nicolin Chen, Shameer Kolothum + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" + +#include "hw/arm/smmuv3.h" +#include "smmuv3-accel.h" + +static SMMUv3AccelDevice *smmuv3_accel_get_dev(SMMUState *bs, SMMUPciBus *= sbus, + PCIBus *bus, int devfn) +{ + SMMUDevice *sdev =3D sbus->pbdev[devfn]; + SMMUv3AccelDevice *accel_dev; + + if (sdev) { + return container_of(sdev, SMMUv3AccelDevice, sdev); + } + + accel_dev =3D g_new0(SMMUv3AccelDevice, 1); + sdev =3D &accel_dev->sdev; + + sbus->pbdev[devfn] =3D sdev; + smmu_init_sdev(bs, sdev, bus, devfn); + return accel_dev; +} + +static AddressSpace *smmuv3_accel_find_add_as(PCIBus *bus, void *opaque, + int devfn) +{ + SMMUState *bs =3D opaque; + SMMUPciBus *sbus =3D smmu_get_sbus(bs, bus); + SMMUv3AccelDevice *accel_dev =3D smmuv3_accel_get_dev(bs, sbus, bus, d= evfn); + SMMUDevice *sdev =3D &accel_dev->sdev; + + return &sdev->as; +} + +static const PCIIOMMUOps smmuv3_accel_ops =3D { + .get_address_space =3D smmuv3_accel_find_add_as, +}; + +void smmuv3_accel_init(SMMUv3State *s) +{ + SMMUState *bs =3D ARM_SMMU(s); + + bs->iommu_ops =3D &smmuv3_accel_ops; +} diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h new file mode 100644 index 0000000000..70da16960f --- /dev/null +++ b/hw/arm/smmuv3-accel.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2025 Huawei Technologies R & D (UK) Ltd + * Copyright (C) 2025 NVIDIA + * Written by Nicolin Chen, Shameer Kolothum + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_ARM_SMMUV3_ACCEL_H +#define HW_ARM_SMMUV3_ACCEL_H + +#include "hw/arm/smmu-common.h" +#include CONFIG_DEVICES + +typedef struct SMMUv3AccelDevice { + SMMUDevice sdev; +} SMMUv3AccelDevice; + +#ifdef CONFIG_ARM_SMMUV3_ACCEL +void smmuv3_accel_init(SMMUv3State *s); +#else +static inline void smmuv3_accel_init(SMMUv3State *s) +{ +} +#endif + +#endif /* HW_ARM_SMMUV3_ACCEL_H */ diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index bcf8af8dc7..ef991cb7d8 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -32,6 +32,7 @@ #include "qapi/error.h" =20 #include "hw/arm/smmuv3.h" +#include "smmuv3-accel.h" #include "smmuv3-internal.h" #include "smmu-internal.h" =20 @@ -1882,6 +1883,10 @@ static void smmu_realize(DeviceState *d, Error **err= p) SysBusDevice *dev =3D SYS_BUS_DEVICE(d); Error *local_err =3D NULL; =20 + if (s->accel) { + smmuv3_accel_init(s); + } + c->parent_realize(d, &local_err); if (local_err) { error_propagate(errp, local_err); diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index d183a62766..bb7076286b 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -63,6 +63,9 @@ struct SMMUv3State { qemu_irq irq[4]; QemuMutex mutex; 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charset="utf-8" Accelerated SMMUv3 is only useful when the device can take advantage of the host's SMMUv3 in nested mode. To keep things simple and correct, we only allow this feature for vfio-pci endpoint devices that use the iommufd backend. We also allow non-endpoint emulated devices like PCI bridges and root ports, so that users can plug in these vfio-pci devices. We can only enforce this if devices are cold plugged. For hotplug cases, give appropria= te warnings. Another reason for this limit is to avoid problems with IOTLB invalidations. Some commands (e.g., CMD_TLBI_NH_ASID) lack an associated SID, making it difficult to trace the originating device. If we allowed emulated endpoint devices, QEMU would have to invalidate both its own software IOTLB and the host's hardware IOTLB, which could slow things down. Since vfio-pci devices in nested mode rely on the host SMMUv3's nested translation (S1+S2), their get_address_space() callback must return the system address space so that VFIO core can setup correct S2 mappings for guest RAM. So in short: - vfio-pci devices(with iommufd as backend) return the system address space. - bridges and root ports return the IOMMU address space. Signed-off-by: Shameer Kolothum Reviewed-by: Jonathan Cameron Reviewed-by: Nicolin Chen Tested-by: Zhangfei Gao --- hw/arm/smmuv3-accel.c | 68 ++++++++++++++++++++++++++++- hw/pci-bridge/pci_expander_bridge.c | 1 - include/hw/pci/pci_bridge.h | 1 + 3 files changed, 68 insertions(+), 2 deletions(-) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 79f1713be6..44410cfb2a 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -7,8 +7,13 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/error-report.h" =20 #include "hw/arm/smmuv3.h" +#include "hw/pci/pci_bridge.h" +#include "hw/pci-host/gpex.h" +#include "hw/vfio/pci.h" + #include "smmuv3-accel.h" =20 static SMMUv3AccelDevice *smmuv3_accel_get_dev(SMMUState *bs, SMMUPciBus *= sbus, @@ -29,15 +34,76 @@ static SMMUv3AccelDevice *smmuv3_accel_get_dev(SMMUStat= e *bs, SMMUPciBus *sbus, return accel_dev; } =20 +static bool smmuv3_accel_pdev_allowed(PCIDevice *pdev, bool *vfio_pci) +{ + + if (object_dynamic_cast(OBJECT(pdev), TYPE_PCI_BRIDGE) || + object_dynamic_cast(OBJECT(pdev), TYPE_PXB_PCIE_DEV) || + object_dynamic_cast(OBJECT(pdev), TYPE_GPEX_ROOT_DEVICE)) { + return true; + } else if ((object_dynamic_cast(OBJECT(pdev), TYPE_VFIO_PCI))) { + *vfio_pci =3D true; + if (object_property_get_link(OBJECT(pdev), "iommufd", NULL)) { + return true; + } + } + return false; +} + static AddressSpace *smmuv3_accel_find_add_as(PCIBus *bus, void *opaque, int devfn) { + PCIDevice *pdev =3D pci_find_device(bus, pci_bus_num(bus), devfn); SMMUState *bs =3D opaque; SMMUPciBus *sbus =3D smmu_get_sbus(bs, bus); SMMUv3AccelDevice *accel_dev =3D smmuv3_accel_get_dev(bs, sbus, bus, d= evfn); SMMUDevice *sdev =3D &accel_dev->sdev; + bool vfio_pci =3D false; + + if (pdev && !smmuv3_accel_pdev_allowed(pdev, &vfio_pci)) { + if (DEVICE(pdev)->hotplugged) { + if (vfio_pci) { + warn_report("Hot plugging a vfio-pci device (%s) without " + "iommufd as backend is not supported", pdev->n= ame); + } else { + warn_report("Hot plugging an emulated device %s with " + "accelerated SMMUv3. This will bring down " + "performace", pdev->name); + } + /* + * Both cases, we will return IOMMU address space. For hotplug= ged + * vfio-pci dev without iommufd as backend, it will fail later= in + * smmuv3_notify_flag_changed() with "requires iommu MAP notif= ier" + * error message. + */ + return &sdev->as; + } else { + error_report("Device(%s) not allowed. Only PCIe root complex " + "devices or PCI bridge devices or vfio-pci endpoi= nt " + "devices with iommufd as backend is allowed with " + "arm-smmuv3,accel=3Don", pdev->name); + exit(1); + } + } =20 - return &sdev->as; + /* + * We return the system address for vfio-pci devices(with iommufd as + * backend) so that the VFIO core can set up Stage-2 (S2) mappings for + * guest RAM. This is needed because, in the accelerated SMMUv3 case, + * the host SMMUv3 runs in nested (S1 + S2) mode where the guest + * manages its own S1 page tables while the host manages S2. + * + * We are using the global &address_space_memory here, as this will en= sure + * same system address space pointer for all devices behind the accele= rated + * SMMUv3s in a VM. That way VFIO/iommufd can reuse a single IOAS ID in + * iommufd_cdev_attach(), allowing the Stage-2 page tables to be shared + * within the VM instead of duplicating them for every SMMUv3 instance. + */ + if (vfio_pci) { + return &address_space_memory; + } else { + return &sdev->as; + } } =20 static const PCIIOMMUOps smmuv3_accel_ops =3D { diff --git a/hw/pci-bridge/pci_expander_bridge.c b/hw/pci-bridge/pci_expand= er_bridge.c index 1bcceddbc4..a8eb2d2426 100644 --- a/hw/pci-bridge/pci_expander_bridge.c +++ b/hw/pci-bridge/pci_expander_bridge.c @@ -48,7 +48,6 @@ struct PXBBus { char bus_path[8]; }; =20 -#define TYPE_PXB_PCIE_DEV "pxb-pcie" OBJECT_DECLARE_SIMPLE_TYPE(PXBPCIEDev, PXB_PCIE_DEV) =20 static GList *pxb_dev_list; diff --git a/include/hw/pci/pci_bridge.h b/include/hw/pci/pci_bridge.h index a055fd8d32..b61360b900 100644 --- a/include/hw/pci/pci_bridge.h +++ b/include/hw/pci/pci_bridge.h @@ -106,6 +106,7 @@ typedef struct PXBPCIEDev { =20 #define TYPE_PXB_PCIE_BUS "pxb-pcie-bus" #define TYPE_PXB_CXL_BUS "pxb-cxl-bus" +#define TYPE_PXB_PCIE_DEV "pxb-pcie" #define TYPE_PXB_DEV "pxb" OBJECT_DECLARE_SIMPLE_TYPE(PXBDev, PXB_DEV) =20 --=20 2.43.0 From nobody Fri Nov 14 23:30:28 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" For accelerated SMMUv3, we need nested parent domain creation. Add the callback support so that VFIO can create a nested parent. In the accelerated SMMUv3 case, the host SMMUv3 is configured in nested mode (S1 + S2), and the guest owns the Stage-1 page table. Therefore, we expose only Stage-1 to the guest to ensure it uses the correct page-table format. Reviewed-by: Nicolin Chen Signed-off-by: Shameer Kolothum Signed-off-by: Shameer Kolothum Reviewed-by: Jonathan Cameron Tested-by: Zhangfei Gao --- hw/arm/smmuv3-accel.c | 13 +++++++++++++ hw/arm/virt.c | 13 +++++++++++++ 2 files changed, 26 insertions(+) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 44410cfb2a..6b0e512d86 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -10,6 +10,7 @@ #include "qemu/error-report.h" =20 #include "hw/arm/smmuv3.h" +#include "hw/iommu.h" #include "hw/pci/pci_bridge.h" #include "hw/pci-host/gpex.h" #include "hw/vfio/pci.h" @@ -106,8 +107,20 @@ static AddressSpace *smmuv3_accel_find_add_as(PCIBus *= bus, void *opaque, } } =20 +static uint64_t smmuv3_accel_get_viommu_flags(void *opaque) +{ + /* + * We return VIOMMU_FLAG_WANT_NESTING_PARENT to inform VFIO core to cr= eate a + * nesting parent which is required for accelerated SMMUv3 support. + * The real HW nested support should be reported from host SMMUv3 and = if + * it doesn't, the nesting parent allocation will fail anyway in VFIO = core. + */ + return VIOMMU_FLAG_WANT_NESTING_PARENT; +} + static const PCIIOMMUOps smmuv3_accel_ops =3D { .get_address_space =3D smmuv3_accel_find_add_as, + .get_viommu_flags =3D smmuv3_accel_get_viommu_flags, }; =20 void smmuv3_accel_init(SMMUv3State *s) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 02209fadcf..b533b0556e 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -3073,6 +3073,19 @@ static void virt_machine_device_plug_cb(HotplugHandl= er *hotplug_dev, return; } =20 + if (object_property_get_bool(OBJECT(dev), "accel", &error_abor= t)) { + char *stage; + + stage =3D object_property_get_str(OBJECT(dev), "stage", + &error_fatal); + /* If no stage specified, SMMUv3 will default to stage 1 */ + if (*stage && strcmp("1", stage)) { + error_setg(errp, "Only stage1 is supported for SMMUV3 = with " + "accel=3Don"); + return; + } + } + create_smmuv3_dev_dtb(vms, dev, bus); } } --=20 2.43.0 From nobody Fri Nov 14 23:30:28 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(1800799024)(82310400026)(36860700013)(376014)(7416014); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Sep 2025 13:39:52.8790 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 509fbfd8-dcc8-4c6e-aff6-08ddff5dab75 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000009A.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV3PR12MB9354 Received-SPF: permerror client-ip=2a01:111:f403:c105::1; envelope-from=skolothumtho@nvidia.com; helo=CH1PR05CU001.outbound.protection.outlook.com X-Spam_score_int: -15 X-Spam_score: -1.6 X-Spam_bar: - X-Spam_report: (-1.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.513, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, SPF_HELO_PASS=-0.001, T_SPF_TEMPERROR=0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1759153610498116600 From: Nicolin Chen Implement a set_iommu_device callback: -If found an existing viommu reuse that. -Else, Allocate a vIOMMU with the nested parent S2 hwpt allocated by VFIO. Though, iommufd=E2=80=99s vIOMMU model supports nested translation by encapsulating a S2 nesting parent HWPT, devices cannot attach to this parent HWPT directly. So two proxy nested HWPTs (bypass and abort) are allocated to handle device attachments. -And add the dev to viommu device list Also add an unset_iommu_device to unwind/cleanup above. Signed-off-by: Nicolin Chen Signed-off-by: Shameer Kolothum Reviewed-by: Jonathan Cameron Tested-by: Zhangfei Gao --- hw/arm/smmuv3-accel.c | 150 ++++++++++++++++++++++++++++++++++++++++ hw/arm/smmuv3-accel.h | 17 +++++ hw/arm/trace-events | 4 ++ include/hw/arm/smmuv3.h | 1 + 4 files changed, 172 insertions(+) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 6b0e512d86..81fa738f6f 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -8,6 +8,7 @@ =20 #include "qemu/osdep.h" #include "qemu/error-report.h" +#include "trace.h" =20 #include "hw/arm/smmuv3.h" #include "hw/iommu.h" @@ -17,6 +18,9 @@ =20 #include "smmuv3-accel.h" =20 +#define SMMU_STE_VALID (1ULL << 0) +#define SMMU_STE_CFG_BYPASS (1ULL << 3) + static SMMUv3AccelDevice *smmuv3_accel_get_dev(SMMUState *bs, SMMUPciBus *= sbus, PCIBus *bus, int devfn) { @@ -35,6 +39,149 @@ static SMMUv3AccelDevice *smmuv3_accel_get_dev(SMMUStat= e *bs, SMMUPciBus *sbus, return accel_dev; } =20 +static bool +smmuv3_accel_dev_alloc_viommu(SMMUv3AccelDevice *accel_dev, + HostIOMMUDeviceIOMMUFD *idev, Error **errp) +{ + struct iommu_hwpt_arm_smmuv3 bypass_data =3D { + .ste =3D { SMMU_STE_CFG_BYPASS | SMMU_STE_VALID, 0x0ULL }, + }; + struct iommu_hwpt_arm_smmuv3 abort_data =3D { + .ste =3D { SMMU_STE_VALID, 0x0ULL }, + }; + SMMUDevice *sdev =3D &accel_dev->sdev; + SMMUState *bs =3D sdev->smmu; + SMMUv3State *s =3D ARM_SMMUV3(bs); + SMMUv3AccelState *s_accel =3D s->s_accel; + uint32_t s2_hwpt_id =3D idev->hwpt_id; + SMMUViommu *viommu; + uint32_t viommu_id; + + if (s_accel->viommu) { + accel_dev->viommu =3D s_accel->viommu; + return true; + } + + if (!iommufd_backend_alloc_viommu(idev->iommufd, idev->devid, + IOMMU_VIOMMU_TYPE_ARM_SMMUV3, + s2_hwpt_id, &viommu_id, errp)) { + return false; + } + + viommu =3D g_new0(SMMUViommu, 1); + viommu->core.viommu_id =3D viommu_id; + viommu->core.s2_hwpt_id =3D s2_hwpt_id; + viommu->core.iommufd =3D idev->iommufd; + + if (!iommufd_backend_alloc_hwpt(idev->iommufd, idev->devid, + viommu->core.viommu_id, 0, + IOMMU_HWPT_DATA_ARM_SMMUV3, + sizeof(abort_data), &abort_data, + &viommu->abort_hwpt_id, errp)) { + goto free_viommu; + } + + if (!iommufd_backend_alloc_hwpt(idev->iommufd, idev->devid, + viommu->core.viommu_id, 0, + IOMMU_HWPT_DATA_ARM_SMMUV3, + sizeof(bypass_data), &bypass_data, + &viommu->bypass_hwpt_id, errp)) { + goto free_abort_hwpt; + } + + viommu->iommufd =3D idev->iommufd; + + s_accel->viommu =3D viommu; + accel_dev->viommu =3D viommu; + return true; + +free_abort_hwpt: + iommufd_backend_free_id(idev->iommufd, viommu->abort_hwpt_id); +free_viommu: + iommufd_backend_free_id(idev->iommufd, viommu->core.viommu_id); + g_free(viommu); + return false; +} + +static bool smmuv3_accel_set_iommu_device(PCIBus *bus, void *opaque, int d= evfn, + HostIOMMUDevice *hiod, Error **e= rrp) +{ + HostIOMMUDeviceIOMMUFD *idev =3D HOST_IOMMU_DEVICE_IOMMUFD(hiod); + SMMUState *bs =3D opaque; + SMMUv3State *s =3D ARM_SMMUV3(bs); + SMMUv3AccelState *s_accel =3D s->s_accel; + SMMUPciBus *sbus =3D smmu_get_sbus(bs, bus); + SMMUv3AccelDevice *accel_dev =3D smmuv3_accel_get_dev(bs, sbus, bus, d= evfn); + SMMUDevice *sdev =3D &accel_dev->sdev; + uint16_t sid =3D smmu_get_sid(sdev); + + if (!idev) { + return true; + } + + if (accel_dev->idev) { + if (accel_dev->idev !=3D idev) { + error_setg(errp, "Device 0x%x already has an associated IOMMU = dev", + sid); + return false; + } + return true; + } + + if (!smmuv3_accel_dev_alloc_viommu(accel_dev, idev, errp)) { + error_setg(errp, "Device 0x%x: Unable to alloc viommu", sid); + return false; + } + + accel_dev->idev =3D idev; + QLIST_INSERT_HEAD(&s_accel->viommu->device_list, accel_dev, next); + trace_smmuv3_accel_set_iommu_device(devfn, sid); + return true; +} + +static void smmuv3_accel_unset_iommu_device(PCIBus *bus, void *opaque, + int devfn) +{ + SMMUState *bs =3D opaque; + SMMUv3State *s =3D ARM_SMMUV3(bs); + SMMUPciBus *sbus =3D g_hash_table_lookup(bs->smmu_pcibus_by_busptr, bu= s); + SMMUv3AccelDevice *accel_dev; + SMMUViommu *viommu; + SMMUDevice *sdev; + uint16_t sid; + + if (!sbus) { + return; + } + + sdev =3D sbus->pbdev[devfn]; + if (!sdev) { + return; + } + + sid =3D smmu_get_sid(sdev); + accel_dev =3D container_of(sdev, SMMUv3AccelDevice, sdev); + if (!host_iommu_device_iommufd_attach_hwpt(accel_dev->idev, + accel_dev->idev->hwpt_id, + NULL)) { + error_report("Unable to attach dev 0x%x to the default HW pagetabl= e", + sid); + } + + accel_dev->idev =3D NULL; + QLIST_REMOVE(accel_dev, next); + trace_smmuv3_accel_unset_iommu_device(devfn, sid); + + viommu =3D s->s_accel->viommu; + if (QLIST_EMPTY(&viommu->device_list)) { + iommufd_backend_free_id(viommu->iommufd, viommu->bypass_hwpt_id); + iommufd_backend_free_id(viommu->iommufd, viommu->abort_hwpt_id); + iommufd_backend_free_id(viommu->iommufd, viommu->core.viommu_id); + g_free(viommu); + s->s_accel->viommu =3D NULL; + } +} + static bool smmuv3_accel_pdev_allowed(PCIDevice *pdev, bool *vfio_pci) { =20 @@ -121,6 +268,8 @@ static uint64_t smmuv3_accel_get_viommu_flags(void *opa= que) static const PCIIOMMUOps smmuv3_accel_ops =3D { .get_address_space =3D smmuv3_accel_find_add_as, .get_viommu_flags =3D smmuv3_accel_get_viommu_flags, + .set_iommu_device =3D smmuv3_accel_set_iommu_device, + .unset_iommu_device =3D smmuv3_accel_unset_iommu_device, }; =20 void smmuv3_accel_init(SMMUv3State *s) @@ -128,4 +277,5 @@ void smmuv3_accel_init(SMMUv3State *s) SMMUState *bs =3D ARM_SMMU(s); =20 bs->iommu_ops =3D &smmuv3_accel_ops; + s->s_accel =3D g_new0(SMMUv3AccelState, 1); } diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h index 70da16960f..3c8506d1e6 100644 --- a/hw/arm/smmuv3-accel.h +++ b/hw/arm/smmuv3-accel.h @@ -10,12 +10,29 @@ #define HW_ARM_SMMUV3_ACCEL_H =20 #include "hw/arm/smmu-common.h" +#include "system/iommufd.h" +#include #include CONFIG_DEVICES =20 +typedef struct SMMUViommu { + IOMMUFDBackend *iommufd; + IOMMUFDViommu core; + uint32_t bypass_hwpt_id; + uint32_t abort_hwpt_id; + QLIST_HEAD(, SMMUv3AccelDevice) device_list; +} SMMUViommu; + typedef struct SMMUv3AccelDevice { SMMUDevice sdev; + HostIOMMUDeviceIOMMUFD *idev; + SMMUViommu *viommu; + QLIST_ENTRY(SMMUv3AccelDevice) next; } SMMUv3AccelDevice; =20 +typedef struct SMMUv3AccelState { + SMMUViommu *viommu; +} SMMUv3AccelState; + #ifdef CONFIG_ARM_SMMUV3_ACCEL void smmuv3_accel_init(SMMUv3State *s); #else diff --git a/hw/arm/trace-events b/hw/arm/trace-events index f3386bd7ae..86370d448a 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -66,6 +66,10 @@ smmuv3_notify_flag_del(const char *iommu) "DEL SMMUNotif= ier node for iommu mr=3D%s smmuv3_inv_notifiers_iova(const char *name, int asid, int vmid, uint64_t i= ova, uint8_t tg, uint64_t num_pages, int stage) "iommu mr=3D%s asid=3D%d vm= id=3D%d iova=3D0x%"PRIx64" tg=3D%d num_pages=3D0x%"PRIx64" stage=3D%d" smmu_reset_exit(void) "" =20 +#smmuv3-accel.c +smmuv3_accel_set_iommu_device(int devfn, uint32_t sid) "devfn=3D0x%x (sid= =3D0x%x)" +smmuv3_accel_unset_iommu_device(int devfn, uint32_t sid) "devfn=3D0x%x (si= d=3D0x%x)" + # strongarm.c strongarm_uart_update_parameters(const char *label, int speed, char parity= , int data_bits, int stop_bits) "%s speed=3D%d parity=3D%c data=3D%d stop= =3D%d" strongarm_ssp_read_underrun(void) "SSP rx underrun" diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index bb7076286b..5f3e9089a7 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -66,6 +66,7 @@ struct SMMUv3State { =20 /* SMMU has HW accelerator support for nested S1 + s2 */ bool accel; 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charset="utf-8" From: Nicolin Chen Allocates a s1 HWPT for the Guest s1 stage and attaches that to the pass-through vfio device. This will be invoked when Guest issues SMMU_CMD_CFGI_STE/STE_RANGE. While at it, we are also exporting both smmu_find_ste() and smmuv3_flush_config() from smmuv3.c for use here. Signed-off-by: Nicolin Chen Signed-off-by: Shameer Kolothum Signed-off-by: Shameer Kolothum Reviewed-by: Jonathan Cameron Tested-by: Zhangfei Gao --- hw/arm/smmuv3-accel.c | 164 +++++++++++++++++++++++++++++++++++++++ hw/arm/smmuv3-accel.h | 22 ++++++ hw/arm/smmuv3-internal.h | 3 + hw/arm/smmuv3.c | 18 ++++- hw/arm/trace-events | 1 + 5 files changed, 205 insertions(+), 3 deletions(-) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 81fa738f6f..5c3825cecd 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -17,10 +17,174 @@ #include "hw/vfio/pci.h" =20 #include "smmuv3-accel.h" +#include "smmuv3-internal.h" =20 #define SMMU_STE_VALID (1ULL << 0) #define SMMU_STE_CFG_BYPASS (1ULL << 3) =20 +#define STE0_V MAKE_64BIT_MASK(0, 1) +#define STE0_CONFIG MAKE_64BIT_MASK(1, 3) +#define STE0_S1FMT MAKE_64BIT_MASK(4, 2) +#define STE0_CTXPTR MAKE_64BIT_MASK(6, 50) +#define STE0_S1CDMAX MAKE_64BIT_MASK(59, 5) +#define STE0_MASK (STE0_S1CDMAX | STE0_CTXPTR | STE0_S1FMT | STE0_CONFI= G | \ + STE0_V) + +#define STE1_S1DSS MAKE_64BIT_MASK(0, 2) +#define STE1_S1CIR MAKE_64BIT_MASK(2, 2) +#define STE1_S1COR MAKE_64BIT_MASK(4, 2) +#define STE1_S1CSH MAKE_64BIT_MASK(6, 2) +#define STE1_S1STALLD MAKE_64BIT_MASK(27, 1) +#define STE1_ETS MAKE_64BIT_MASK(28, 2) +#define STE1_MASK (STE1_ETS | STE1_S1STALLD | STE1_S1CSH | STE1_S1COR = | \ + STE1_S1CIR | STE1_S1DSS) + +static bool +smmuv3_accel_dev_uninstall_nested_ste(SMMUv3AccelDevice *accel_dev, bool a= bort, + Error **errp) +{ + HostIOMMUDeviceIOMMUFD *idev =3D accel_dev->idev; + SMMUS1Hwpt *s1_hwpt =3D accel_dev->s1_hwpt; + uint32_t hwpt_id; + + if (!s1_hwpt || !accel_dev->viommu) { + return true; + } + + if (abort) { + hwpt_id =3D accel_dev->viommu->abort_hwpt_id; + } else { + hwpt_id =3D accel_dev->viommu->bypass_hwpt_id; + } + + if (!host_iommu_device_iommufd_attach_hwpt(idev, hwpt_id, errp)) { + return false; + } + + iommufd_backend_free_id(s1_hwpt->iommufd, s1_hwpt->hwpt_id); + accel_dev->s1_hwpt =3D NULL; + g_free(s1_hwpt); + return true; +} + +static bool +smmuv3_accel_dev_install_nested_ste(SMMUv3AccelDevice *accel_dev, + uint32_t data_type, uint32_t data_len, + void *data, Error **errp) +{ + SMMUViommu *viommu =3D accel_dev->viommu; + SMMUS1Hwpt *s1_hwpt =3D accel_dev->s1_hwpt; + HostIOMMUDeviceIOMMUFD *idev =3D accel_dev->idev; + uint32_t flags =3D 0; + + if (!idev || !viommu) { + error_setg(errp, "Device 0x%x has no associated IOMMU dev or vIOMM= U", + smmu_get_sid(&accel_dev->sdev)); + return false; + } + + if (s1_hwpt) { + if (!smmuv3_accel_dev_uninstall_nested_ste(accel_dev, true, errp))= { + return false; + } + } + + s1_hwpt =3D g_new0(SMMUS1Hwpt, 1); + s1_hwpt->iommufd =3D idev->iommufd; + if (!iommufd_backend_alloc_hwpt(idev->iommufd, idev->devid, + viommu->core.viommu_id, flags, data_ty= pe, + data_len, data, &s1_hwpt->hwpt_id, err= p)) { + return false; + } + + if (!host_iommu_device_iommufd_attach_hwpt(idev, s1_hwpt->hwpt_id, err= p)) { + iommufd_backend_free_id(idev->iommufd, s1_hwpt->hwpt_id); + return false; + } + accel_dev->s1_hwpt =3D s1_hwpt; + return true; +} + +bool +smmuv3_accel_install_nested_ste(SMMUv3State *s, SMMUDevice *sdev, int sid, + Error **errp) +{ + SMMUv3AccelDevice *accel_dev; + SMMUEventInfo event =3D {.type =3D SMMU_EVT_NONE, .sid =3D sid, + .inval_ste_allowed =3D true}; + struct iommu_hwpt_arm_smmuv3 nested_data =3D {}; + uint64_t ste_0, ste_1; + uint32_t config; + STE ste; + int ret; + + if (!s->accel) { + return true; + } + + accel_dev =3D container_of(sdev, SMMUv3AccelDevice, sdev); + if (!accel_dev->viommu) { + return true; + } + + ret =3D smmu_find_ste(sdev->smmu, sid, &ste, &event); + if (ret) { + error_setg(errp, "Failed to find STE for Device 0x%x", sid); + return true; + } + + config =3D STE_CONFIG(&ste); + if (!STE_VALID(&ste) || !STE_CFG_S1_ENABLED(config)) { + if (!smmuv3_accel_dev_uninstall_nested_ste(accel_dev, + STE_CFG_ABORT(config), + errp)) { + return false; + } + smmuv3_flush_config(sdev); + return true; + } + + ste_0 =3D (uint64_t)ste.word[0] | (uint64_t)ste.word[1] << 32; + ste_1 =3D (uint64_t)ste.word[2] | (uint64_t)ste.word[3] << 32; + nested_data.ste[0] =3D cpu_to_le64(ste_0 & STE0_MASK); + nested_data.ste[1] =3D cpu_to_le64(ste_1 & STE1_MASK); + + if (!smmuv3_accel_dev_install_nested_ste(accel_dev, + IOMMU_HWPT_DATA_ARM_SMMUV3, + sizeof(nested_data), + &nested_data, errp)) { + error_setg(errp, "Unable to install nested STE=3D%16LX:%16LX, sid= =3D0x%x," + "ret=3D%d", nested_data.ste[1], nested_data.ste[0], sid= , ret); + return false; + } + trace_smmuv3_accel_install_nested_ste(sid, nested_data.ste[1], + nested_data.ste[0]); + return true; +} + +bool smmuv3_accel_install_nested_ste_range(SMMUv3State *s, SMMUSIDRange *r= ange, + Error **errp) +{ + SMMUv3AccelState *s_accel =3D s->s_accel; + SMMUv3AccelDevice *accel_dev; + + if (!s_accel || !s_accel->viommu) { + return true; + } + + QLIST_FOREACH(accel_dev, &s_accel->viommu->device_list, next) { + uint32_t sid =3D smmu_get_sid(&accel_dev->sdev); + + if (sid >=3D range->start && sid <=3D range->end) { + if (!smmuv3_accel_install_nested_ste(s, &accel_dev->sdev, + sid, errp)) { + return false; + } + } + } + return true; +} + static SMMUv3AccelDevice *smmuv3_accel_get_dev(SMMUState *bs, SMMUPciBus *= sbus, PCIBus *bus, int devfn) { diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h index 3c8506d1e6..f631443b09 100644 --- a/hw/arm/smmuv3-accel.h +++ b/hw/arm/smmuv3-accel.h @@ -22,9 +22,15 @@ typedef struct SMMUViommu { QLIST_HEAD(, SMMUv3AccelDevice) device_list; } SMMUViommu; =20 +typedef struct SMMUS1Hwpt { + IOMMUFDBackend *iommufd; + uint32_t hwpt_id; +} SMMUS1Hwpt; + typedef struct SMMUv3AccelDevice { SMMUDevice sdev; HostIOMMUDeviceIOMMUFD *idev; + SMMUS1Hwpt *s1_hwpt; SMMUViommu *viommu; QLIST_ENTRY(SMMUv3AccelDevice) next; } SMMUv3AccelDevice; @@ -35,10 +41,26 @@ typedef struct SMMUv3AccelState { =20 #ifdef CONFIG_ARM_SMMUV3_ACCEL void smmuv3_accel_init(SMMUv3State *s); +bool smmuv3_accel_install_nested_ste(SMMUv3State *s, SMMUDevice *sdev, int= sid, + Error **errp); +bool smmuv3_accel_install_nested_ste_range(SMMUv3State *s, SMMUSIDRange *r= ange, + Error **errp); #else static inline void smmuv3_accel_init(SMMUv3State *s) { } +static inline bool +smmuv3_accel_install_nested_ste(SMMUv3State *s, SMMUDevice *sdev, int sid, + Error **errp) +{ + return true; +} +static inline bool +smmuv3_accel_install_nested_ste_range(SMMUv3State *s, SMMUSIDRange *range, + Error **errp) +{ + return true; +} #endif =20 #endif /* HW_ARM_SMMUV3_ACCEL_H */ diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h index b6b7399347..b0dfa9465c 100644 --- a/hw/arm/smmuv3-internal.h +++ b/hw/arm/smmuv3-internal.h @@ -547,6 +547,9 @@ typedef struct CD { uint32_t word[16]; } CD; =20 +int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste, SMMUEventInfo *e= vent); +void smmuv3_flush_config(SMMUDevice *sdev); + /* STE fields */ =20 #define STE_VALID(x) extract32((x)->word[0], 0, 1) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index ef991cb7d8..1fd8aaa0c7 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -630,8 +630,7 @@ bad_ste: * Supports linear and 2-level stream table * Return 0 on success, -EINVAL otherwise */ -static int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste, - SMMUEventInfo *event) +int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste, SMMUEventInfo *e= vent) { dma_addr_t addr, strtab_base; uint32_t log2size; @@ -900,7 +899,7 @@ static SMMUTransCfg *smmuv3_get_config(SMMUDevice *sdev= , SMMUEventInfo *event) return cfg; } =20 -static void smmuv3_flush_config(SMMUDevice *sdev) +void smmuv3_flush_config(SMMUDevice *sdev) { SMMUv3State *s =3D sdev->smmu; SMMUState *bc =3D &s->smmu_state; @@ -1330,6 +1329,7 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) { uint32_t sid =3D CMD_SID(&cmd); SMMUDevice *sdev =3D smmu_find_sdev(bs, sid); + Error *local_err =3D NULL; =20 if (CMD_SSEC(&cmd)) { cmd_error =3D SMMU_CERROR_ILL; @@ -1341,6 +1341,11 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) } =20 trace_smmuv3_cmdq_cfgi_ste(sid); + if (!smmuv3_accel_install_nested_ste(s, sdev, sid, &local_err)= ) { + error_report_err(local_err); + cmd_error =3D SMMU_CERROR_ILL; + break; + } smmuv3_flush_config(sdev); =20 break; @@ -1350,6 +1355,7 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) uint32_t sid =3D CMD_SID(&cmd), mask; uint8_t range =3D CMD_STE_RANGE(&cmd); SMMUSIDRange sid_range; + Error *local_err =3D NULL; =20 if (CMD_SSEC(&cmd)) { cmd_error =3D SMMU_CERROR_ILL; @@ -1361,6 +1367,12 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) sid_range.end =3D sid_range.start + mask; =20 trace_smmuv3_cmdq_cfgi_ste_range(sid_range.start, sid_range.en= d); + if (!smmuv3_accel_install_nested_ste_range(s, &sid_range, + &local_err)) { + error_report_err(local_err); + cmd_error =3D SMMU_CERROR_ILL; + break; + } smmu_configs_inv_sid_range(bs, sid_range); break; } diff --git a/hw/arm/trace-events b/hw/arm/trace-events index 86370d448a..3b1e9bf083 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -69,6 +69,7 @@ smmu_reset_exit(void) "" #smmuv3-accel.c smmuv3_accel_set_iommu_device(int devfn, uint32_t sid) "devfn=3D0x%x (sid= =3D0x%x)" smmuv3_accel_unset_iommu_device(int devfn, uint32_t sid) "devfn=3D0x%x (si= d=3D0x%x)" +smmuv3_accel_install_nested_ste(uint32_t sid, uint64_t ste_1, uint64_t ste= _0) "sid=3D%d ste=3D%"PRIx64":%"PRIx64 =20 # strongarm.c strongarm_uart_update_parameters(const char *label, int speed, char parity= , int data_bits, int stop_bits) "%s speed=3D%d parity=3D%c data=3D%d stop= =3D%d" --=20 2.43.0 From nobody Fri Nov 14 23:30:28 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); 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charset="utf-8" From: Nicolin Chen Allocate and associate a vDEVICE object for the Guest device with the vIOMMU. This will help the host kernel to make a virtual SID --> physical SID mapping. Since we pass the raw invalidation commands(eg: CMD_CFGI_CD) from Guest directly to host kernel, this provides a way to retrieve the correct physical SID. Signed-off-by: Nicolin Chen Signed-off-by: Shameer Kolothum Signed-off-by: Shameer Kolothum Reviewed-by: Jonathan Cameron Tested-by: Zhangfei Gao --- hw/arm/smmuv3-accel.c | 41 +++++++++++++++++++++++++++++++++++++++++ hw/arm/smmuv3-accel.h | 1 + 2 files changed, 42 insertions(+) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 5c3825cecd..790887ac31 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -39,6 +39,35 @@ #define STE1_MASK (STE1_ETS | STE1_S1STALLD | STE1_S1CSH | STE1_S1COR = | \ STE1_S1CIR | STE1_S1DSS) =20 +static bool +smmuv3_accel_alloc_vdev(SMMUv3AccelDevice *accel_dev, int sid, Error **err= p) +{ + SMMUViommu *viommu =3D accel_dev->viommu; + IOMMUFDVdev *vdev; + uint32_t vdev_id; + + if (!accel_dev->idev || accel_dev->vdev) { + return true; + } + + if (!iommufd_backend_alloc_vdev(viommu->iommufd, accel_dev->idev->devi= d, + viommu->core.viommu_id, sid, + &vdev_id, errp)) { + return false; + } + if (!host_iommu_device_iommufd_attach_hwpt(accel_dev->idev, + viommu->bypass_hwpt_id, err= p)) { + iommufd_backend_free_id(viommu->iommufd, vdev_id); + return false; + } + + vdev =3D g_new(IOMMUFDVdev, 1); + vdev->vdev_id =3D vdev_id; + vdev->dev_id =3D sid; + accel_dev->vdev =3D vdev; + return true; +} + static bool smmuv3_accel_dev_uninstall_nested_ste(SMMUv3AccelDevice *accel_dev, bool a= bort, Error **errp) @@ -127,6 +156,10 @@ smmuv3_accel_install_nested_ste(SMMUv3State *s, SMMUDe= vice *sdev, int sid, return true; } =20 + if (!smmuv3_accel_alloc_vdev(accel_dev, sid, errp)) { + return false; + } + ret =3D smmu_find_ste(sdev->smmu, sid, &ste, &event); if (ret) { error_setg(errp, "Failed to find STE for Device 0x%x", sid); @@ -311,6 +344,7 @@ static void smmuv3_accel_unset_iommu_device(PCIBus *bus= , void *opaque, SMMUPciBus *sbus =3D g_hash_table_lookup(bs->smmu_pcibus_by_busptr, bu= s); SMMUv3AccelDevice *accel_dev; SMMUViommu *viommu; + IOMMUFDVdev *vdev; SMMUDevice *sdev; uint16_t sid; =20 @@ -337,6 +371,13 @@ static void smmuv3_accel_unset_iommu_device(PCIBus *bu= s, void *opaque, trace_smmuv3_accel_unset_iommu_device(devfn, sid); =20 viommu =3D s->s_accel->viommu; + vdev =3D accel_dev->vdev; + if (vdev) { + iommufd_backend_free_id(viommu->iommufd, vdev->vdev_id); + g_free(vdev); + accel_dev->vdev =3D NULL; + } + if (QLIST_EMPTY(&viommu->device_list)) { iommufd_backend_free_id(viommu->iommufd, viommu->bypass_hwpt_id); iommufd_backend_free_id(viommu->iommufd, viommu->abort_hwpt_id); diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h index f631443b09..6242614c00 100644 --- a/hw/arm/smmuv3-accel.h +++ b/hw/arm/smmuv3-accel.h @@ -31,6 +31,7 @@ typedef struct SMMUv3AccelDevice { SMMUDevice sdev; HostIOMMUDeviceIOMMUFD *idev; SMMUS1Hwpt *s1_hwpt; + IOMMUFDVdev *vdev; SMMUViommu *viommu; QLIST_ENTRY(SMMUv3AccelDevice) next; } SMMUv3AccelDevice; --=20 2.43.0 From nobody Fri Nov 14 23:30:28 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" On ARM, when a device is behind an IOMMU, its MSI doorbell address is subject to translation by the IOMMU. This behavior affects vfio-pci passthrough devices assigned to guests using an accelerated SMMUv3. In this setup, we configure the host SMMUv3 in nested mode, where VFIO sets up the Stage-2 (S2) mappings for guest RAM, while the guest controls Stage-1 (S1). To allow VFIO to correctly configure S2 mappings, we currently return the system address space via the get_address_space() callback for vfio-pci devices. However, QEMU/KVM also uses this same callback path when resolving the address space for MSI doorbells: kvm_irqchip_add_msi_route() kvm_arch_fixup_msi_route() pci_device_iommu_address_space() get_address_space() This will cause the device to be configured with wrong MSI doorbell address if it return the system address space. Introduce an optional get_msi_address_space() callback and use that in the above path if available. This will enable IOMMU implementations to make use of this if required. Suggested-by: Nicolin Chen Signed-off-by: Shameer Kolothum Signed-off-by: Shameer Kolothum Reviewed-by Nicolin Chen Reviewed-by: Jonathan Cameron Tested-by: Zhangfei Gao --- hw/pci/pci.c | 19 +++++++++++++++++++ include/hw/pci/pci.h | 16 ++++++++++++++++ target/arm/kvm.c | 2 +- 3 files changed, 36 insertions(+), 1 deletion(-) diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 1315ef13ea..6f9e1616dd 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -2964,6 +2964,25 @@ AddressSpace *pci_device_iommu_address_space(PCIDevi= ce *dev) return &address_space_memory; } =20 +AddressSpace *pci_device_iommu_msi_address_space(PCIDevice *dev) +{ + PCIBus *bus; + PCIBus *iommu_bus; + int devfn; + + pci_device_get_iommu_bus_devfn(dev, &iommu_bus, &bus, &devfn); + if (iommu_bus) { + if (iommu_bus->iommu_ops->get_msi_address_space) { + return iommu_bus->iommu_ops->get_msi_address_space(bus, + iommu_bus->iommu_opaque, devfn); + } else { + return iommu_bus->iommu_ops->get_address_space(bus, + iommu_bus->iommu_opaque, devfn); + } + } + return &address_space_memory; +} + int pci_iommu_init_iotlb_notifier(PCIDevice *dev, IOMMUNotifier *n, IOMMUNotify fn, void *opaque) { diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index c54f2b53ae..0d3b351903 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -652,6 +652,21 @@ typedef struct PCIIOMMUOps { uint32_t pasid, bool priv_req, bool exec_req, hwaddr addr, bool lpig, uint16_t prgi, bool is= _read, bool is_write); + /** + * @get_msi_address_space: get the address space for MSI doorbell addr= ess + * for devices + * + * Optional callback which returns a pointer to an #AddressSpace. This + * is required if MSI doorbell also gets translated through IOMMU(eg: = ARM) + * + * @bus: the #PCIBus being accessed. + * + * @opaque: the data passed to pci_setup_iommu(). + * + * @devfn: device and function number + */ + AddressSpace * (*get_msi_address_space)(PCIBus *bus, void *opaque, + int devfn); } PCIIOMMUOps; =20 bool pci_device_get_iommu_bus_devfn(PCIDevice *dev, PCIBus **piommu_bus, @@ -660,6 +675,7 @@ AddressSpace *pci_device_iommu_address_space(PCIDevice = *dev); bool pci_device_set_iommu_device(PCIDevice *dev, HostIOMMUDevice *hiod, Error **errp); void pci_device_unset_iommu_device(PCIDevice *dev); +AddressSpace *pci_device_iommu_msi_address_space(PCIDevice *dev); =20 /** * pci_device_get_viommu_flags: get vIOMMU flags. diff --git a/target/arm/kvm.c b/target/arm/kvm.c index b8a1c071f5..10eb8655c6 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -1611,7 +1611,7 @@ int kvm_arm_set_irq(int cpu, int irqtype, int irq, in= t level) int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route, uint64_t address, uint32_t data, PCIDevice *d= ev) { - AddressSpace *as =3D pci_device_iommu_address_space(dev); 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(1800799024)(36860700013)(82310400026)(7416014)(376014); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Sep 2025 13:40:06.5704 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 82712470-82b0-46a8-0481-08ddff5db39c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000009B.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8881 Received-SPF: permerror client-ip=2a01:111:f403:c110::1; envelope-from=skolothumtho@nvidia.com; helo=BN1PR04CU002.outbound.protection.outlook.com X-Spam_score_int: -2 X-Spam_score: -0.3 X-Spam_bar: / X-Spam_report: (-0.3 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, FORGED_SPF_HELO=1, KHOP_HELO_FCRDNS=0.4, SPF_HELO_PASS=-0.001, T_SPF_TEMPERROR=0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1759153863289116600 Content-Type: text/plain; charset="utf-8" Here we return the IOMMU address space if the device has S1 translation enabled by Guest. Otherwise return system address space. Signed-off-by: Shameer Kolothum Signed-off-by: Shameer Kolothum Reviewed-by: Nicolin Chen Tested-by: Zhangfei Gao --- hw/arm/smmuv3-accel.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 790887ac31..f4e01fba6d 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -387,6 +387,26 @@ static void smmuv3_accel_unset_iommu_device(PCIBus *bu= s, void *opaque, } } =20 +static AddressSpace *smmuv3_accel_find_msi_as(PCIBus *bus, void *opaque, + int devfn) +{ + SMMUState *bs =3D opaque; + SMMUPciBus *sbus =3D smmu_get_sbus(bs, bus); + SMMUv3AccelDevice *accel_dev =3D smmuv3_accel_get_dev(bs, sbus, bus, d= evfn); + SMMUDevice *sdev =3D &accel_dev->sdev; + + /* + * If the assigned vfio-pci dev has S1 translation enabled by + * Guest, return IOMMU address space for MSI translation. + * Otherwise, return system address space. + */ + if (accel_dev->s1_hwpt) { + return &sdev->as; + } else { + return &address_space_memory; + } +} + static bool smmuv3_accel_pdev_allowed(PCIDevice *pdev, bool *vfio_pci) { =20 @@ -475,6 +495,7 @@ static const PCIIOMMUOps smmuv3_accel_ops =3D { .get_viommu_flags =3D smmuv3_accel_get_viommu_flags, .set_iommu_device =3D smmuv3_accel_set_iommu_device, .unset_iommu_device =3D smmuv3_accel_unset_iommu_device, + .get_msi_address_space =3D smmuv3_accel_find_msi_as, }; =20 void smmuv3_accel_init(SMMUv3State *s) --=20 2.43.0 From nobody Fri Nov 14 23:30:28 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass(p=reject dis=none) header.from=nvidia.com ARC-Seal: i=2; a=rsa-sha256; t=1759153953; cv=pass; d=zohomail.com; s=zohoarc; b=lJQ4XzdXucu0evUg3TrGkcN6WQmh8NtNex7lIjJauV9mQNh/QpZPbJaIX1yeHqLMy0WYfCck3PJkMfZe2WdWYQNxuxgwcbGFuVfd7+iMiMVsdwKVG8UU37pslDBtu6hg5rewXOFmAqDmZEK29w2aGHQiuEJzRtED9HNyq/wkk4k= ARC-Message-Signature: i=2; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(36860700013)(82310400026)(376014)(7416014)(1800799024); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Sep 2025 13:40:09.5778 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a52c8ddc-6b66-47a1-7b3f-08ddff5db56b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000009B.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB6605 Received-SPF: permerror client-ip=2a01:111:f403:c005::5; envelope-from=skolothumtho@nvidia.com; helo=CO1PR03CU002.outbound.protection.outlook.com X-Spam_score_int: -15 X-Spam_score: -1.6 X-Spam_bar: - X-Spam_report: (-1.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.513, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1759153954916116600 Provide a helper and use that to issue the invalidation cmd to host SMMUv3. We only issue one cmd at a time for now. Support for batching of commands=C2=A0will be added later after analysing t= he impact. Signed-off-by: Shameer Kolothum Reviewed-by: Jonathan Cameron Reviewed-by: Nicolin Chen Tested-by: Zhangfei Gao --- hw/arm/smmuv3-accel.c | 38 ++++++++++++++++++++++++++++++++++++++ hw/arm/smmuv3-accel.h | 8 ++++++++ hw/arm/smmuv3.c | 30 ++++++++++++++++++++++++++++++ 3 files changed, 76 insertions(+) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index f4e01fba6d..9ad8595ce2 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -218,6 +218,44 @@ bool smmuv3_accel_install_nested_ste_range(SMMUv3State= *s, SMMUSIDRange *range, return true; } =20 +/* + * This issues the invalidation cmd to the host SMMUv3. + * Note: sdev can be NULL for certain invalidation commands + * e.g., SMMU_CMD_TLBI_NH_ASID, SMMU_CMD_TLBI_NH_VA etc. + */ +bool smmuv3_accel_issue_inv_cmd(SMMUv3State *bs, void *cmd, SMMUDevice *sd= ev, + Error **errp) +{ + SMMUv3State *s =3D ARM_SMMUV3(bs); + SMMUv3AccelState *s_accel =3D s->s_accel; + IOMMUFDViommu *viommu_core; + uint32_t entry_num =3D 1; + + if (!s->accel || !s_accel->viommu) { + return true; + } + + /* + * We may end up here for any emulated PCI bridge or root port type dev= ices. + * However, passing invalidation commands with sid (eg: CFGI_CD) to host + * SMMUv3 only matters for vfio-pci endpoint devices. Hence check that = if + * sdev is valid. + */ + if (sdev) { + SMMUv3AccelDevice *accel_dev =3D container_of(sdev, SMMUv3AccelDev= ice, + sdev); + if (!accel_dev->vdev) { + return true; + } + } + + viommu_core =3D &s_accel->viommu->core; + return iommufd_backend_invalidate_cache( + viommu_core->iommufd, viommu_core->viommu_id, + IOMMU_VIOMMU_INVALIDATE_DATA_ARM_SMMUV3, + sizeof(Cmd), &entry_num, cmd, errp); +} + static SMMUv3AccelDevice *smmuv3_accel_get_dev(SMMUState *bs, SMMUPciBus *= sbus, PCIBus *bus, int devfn) { diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h index 6242614c00..3bdba47616 100644 --- a/hw/arm/smmuv3-accel.h +++ b/hw/arm/smmuv3-accel.h @@ -46,6 +46,8 @@ bool smmuv3_accel_install_nested_ste(SMMUv3State *s, SMMU= Device *sdev, int sid, Error **errp); bool smmuv3_accel_install_nested_ste_range(SMMUv3State *s, SMMUSIDRange *r= ange, Error **errp); +bool smmuv3_accel_issue_inv_cmd(SMMUv3State *s, void *cmd, SMMUDevice *sde= v, + Error **errp); #else static inline void smmuv3_accel_init(SMMUv3State *s) { @@ -62,6 +64,12 @@ smmuv3_accel_install_nested_ste_range(SMMUv3State *s, SM= MUSIDRange *range, { return true; } +static inline bool +smmuv3_accel_issue_inv_cmd(SMMUv3State *s, void *cmd, SMMUDevice *sdev, + Error **errp) +{ + return true; +} #endif =20 #endif /* HW_ARM_SMMUV3_ACCEL_H */ diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 1fd8aaa0c7..3963bdc87f 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -1381,6 +1381,7 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) { uint32_t sid =3D CMD_SID(&cmd); SMMUDevice *sdev =3D smmu_find_sdev(bs, sid); + Error *local_err =3D NULL; =20 if (CMD_SSEC(&cmd)) { cmd_error =3D SMMU_CERROR_ILL; @@ -1393,11 +1394,17 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) =20 trace_smmuv3_cmdq_cfgi_cd(sid); smmuv3_flush_config(sdev); + if (!smmuv3_accel_issue_inv_cmd(s, &cmd, sdev, &local_err)) { + error_report_err(local_err); + cmd_error =3D SMMU_CERROR_ILL; + break; + } break; } case SMMU_CMD_TLBI_NH_ASID: { int asid =3D CMD_ASID(&cmd); + Error *local_err =3D NULL; int vmid =3D -1; =20 if (!STAGE1_SUPPORTED(s)) { @@ -1416,6 +1423,11 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) trace_smmuv3_cmdq_tlbi_nh_asid(asid); smmu_inv_notifiers_all(&s->smmu_state); smmu_iotlb_inv_asid_vmid(bs, asid, vmid); + if (!smmuv3_accel_issue_inv_cmd(s, &cmd, NULL, &local_err)) { + error_report_err(local_err); + cmd_error =3D SMMU_CERROR_ILL; + break; + } break; } case SMMU_CMD_TLBI_NH_ALL: @@ -1440,18 +1452,36 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) QEMU_FALLTHROUGH; } case SMMU_CMD_TLBI_NSNH_ALL: + { + Error *local_err =3D NULL; + trace_smmuv3_cmdq_tlbi_nsnh(); smmu_inv_notifiers_all(&s->smmu_state); smmu_iotlb_inv_all(bs); + if (!smmuv3_accel_issue_inv_cmd(s, &cmd, NULL, &local_err)) { + error_report_err(local_err); + cmd_error =3D SMMU_CERROR_ILL; + break; + } break; + } case SMMU_CMD_TLBI_NH_VAA: case SMMU_CMD_TLBI_NH_VA: + { + Error *local_err =3D NULL; + if (!STAGE1_SUPPORTED(s)) { cmd_error =3D SMMU_CERROR_ILL; break; } smmuv3_range_inval(bs, &cmd, SMMU_STAGE_1); + if (!smmuv3_accel_issue_inv_cmd(s, &cmd, NULL, &local_err)) { + error_report_err(local_err); + cmd_error =3D SMMU_CERROR_ILL; + break; + } break; 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charset="utf-8" Just before the device gets attached to the SMMUv3, make sure QEMU SMMUv3 features are compatible with the host SMMUv3. Not all fields in the host SMMUv3 IDR registers are meaningful for userspac= e. Only the following fields can be used: - IDR0: ST_LEVEL, TERM_MODEL, STALL_MODEL, TTENDIAN, CD2L, ASID16, TTF - IDR1: SIDSIZE, SSIDSIZE - IDR3: BBML, RIL - IDR5: VAX, GRAN64K, GRAN16K, GRAN4K For now, the check is to make sure the features are in sync to enable basic accelerated SMMUv3 support. One other related change is, move the smmuv3_init_regs() to smmu_realize() so that we do have that early enough for the check mentioned above. Signed-off-by: Shameer Kolothum Tested-by: Zhangfei Gao --- hw/arm/smmuv3-accel.c | 98 +++++++++++++++++++++++++++++++++++++++++++ hw/arm/smmuv3.c | 4 +- 2 files changed, 100 insertions(+), 2 deletions(-) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 9ad8595ce2..defeddbd8c 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -39,6 +39,96 @@ #define STE1_MASK (STE1_ETS | STE1_S1STALLD | STE1_S1CSH | STE1_S1COR = | \ STE1_S1CIR | STE1_S1DSS) =20 +static bool +smmuv3_accel_check_hw_compatible(SMMUv3State *s, + struct iommu_hw_info_arm_smmuv3 *info, + Error **errp) +{ + uint32_t val; + + /* + * QEMU SMMUv3 supports both linear and 2-level stream tables. + */ + val =3D FIELD_EX32(info->idr[0], IDR0, STLEVEL); + if (val !=3D FIELD_EX32(s->idr[0], IDR0, STLEVEL)) { + s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, STLEVEL, val); + error_setg(errp, "Host SUMMUv3 differs in Stream Table format"); + return false; + } + + /* QEMU SMMUv3 supports only little-endian translation table walks */ + val =3D FIELD_EX32(info->idr[0], IDR0, TTENDIAN); + if (!val && val > FIELD_EX32(s->idr[0], IDR0, TTENDIAN)) { + error_setg(errp, "Host SUMMUv3 doesn't support Little-endian " + "translation table"); + return false; + } + + /* QEMU SMMUv3 supports only AArch64 translation table format */ + val =3D FIELD_EX32(info->idr[0], IDR0, TTF); + if (val < FIELD_EX32(s->idr[0], IDR0, TTF)) { + error_setg(errp, "Host SUMMUv3 deosn't support Arch64 Translation " + "table format"); + return false; + } + + /* QEMU SMMUv3 supports SIDSIZE 16 */ + val =3D FIELD_EX32(info->idr[1], IDR1, SIDSIZE); + if (val < FIELD_EX32(s->idr[1], IDR1, SIDSIZE)) { + error_setg(errp, "Host SUMMUv3 SIDSIZE not compatible"); + return false; + } + + /* QEMU SMMUv3 supports Range Invalidation by default */ + val =3D FIELD_EX32(info->idr[3], IDR3, RIL); + if (val !=3D FIELD_EX32(s->idr[3], IDR3, RIL)) { + error_setg(errp, "Host SUMMUv3 deosn't support Range Invalidation"= ); + return false; + } + + val =3D FIELD_EX32(info->idr[5], IDR5, GRAN4K); + if (val !=3D FIELD_EX32(s->idr[5], IDR5, GRAN4K)) { + error_setg(errp, "Host SMMUv3 doesn't support 64K translation gran= ule"); + return false; + } + val =3D FIELD_EX32(info->idr[5], IDR5, GRAN16K); + if (val !=3D FIELD_EX32(s->idr[5], IDR5, GRAN16K)) { + error_setg(errp, "Host SMMUv3 doesn't support 16K translation gran= ule"); + return false; + } + val =3D FIELD_EX32(info->idr[5], IDR5, GRAN64K); + if (val !=3D FIELD_EX32(s->idr[5], IDR5, GRAN64K)) { + error_setg(errp, "Host SMMUv3 doesn't support 16K translation gran= ule"); + return false; + } + return true; +} + +static bool +smmuv3_accel_hw_compatible(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev, + Error **errp) +{ + struct iommu_hw_info_arm_smmuv3 info; + uint32_t data_type; + uint64_t caps; + + if (!iommufd_backend_get_device_info(idev->iommufd, idev->devid, &data= _type, + &info, sizeof(info), &caps, errp)= ) { + return false; + } + + if (data_type !=3D IOMMU_HW_INFO_TYPE_ARM_SMMUV3) { + error_setg(errp, "Wrong data type (%d) for Host SMMUv3 device info= ", + data_type); + return false; + } + + if (!smmuv3_accel_check_hw_compatible(s, &info, errp)) { + return false; + } + return true; +} + static bool smmuv3_accel_alloc_vdev(SMMUv3AccelDevice *accel_dev, int sid, Error **err= p) { @@ -363,6 +453,14 @@ static bool smmuv3_accel_set_iommu_device(PCIBus *bus,= void *opaque, int devfn, return true; } =20 + /* + * Check the host SMMUv3 associated with the dev is compatible with the + * QEMU SMMUv3 accel. + */ + if (!smmuv3_accel_hw_compatible(s, idev, errp)) { + return false; + } + if (!smmuv3_accel_dev_alloc_viommu(accel_dev, idev, errp)) { error_setg(errp, "Device 0x%x: Unable to alloc viommu", sid); return false; diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 3963bdc87f..5830cf5a03 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -1913,8 +1913,6 @@ static void smmu_reset_exit(Object *obj, ResetType ty= pe) if (c->parent_phases.exit) { c->parent_phases.exit(obj, type); } - - smmuv3_init_regs(s); } =20 static void smmu_realize(DeviceState *d, Error **errp) @@ -1945,6 +1943,8 @@ static void smmu_realize(DeviceState *d, Error **errp) sysbus_init_mmio(dev, &sys->iomem); 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charset="utf-8" From: Eric Auger At the moment we do not support other function than function 0. So according to ACPI spec "_DSM (Device Specific Method)" description, bit 0 should rath= er be 0, meaning no other function is supported than function 0. Signed-off-by: Eric Auger Signed-off-by: Shameer Kolothum Tested-by: Zhangfei Gao --- hw/pci-host/gpex-acpi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/pci-host/gpex-acpi.c b/hw/pci-host/gpex-acpi.c index 952a0ace19..4587baeb78 100644 --- a/hw/pci-host/gpex-acpi.c +++ b/hw/pci-host/gpex-acpi.c @@ -64,7 +64,7 @@ static Aml *build_pci_host_bridge_dsm_method(void) UUID =3D aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D"); ifctx =3D aml_if(aml_equal(aml_arg(0), UUID)); ifctx1 =3D aml_if(aml_equal(aml_arg(2), aml_int(0))); - uint8_t byte_list[1] =3D {1}; + uint8_t byte_list[1] =3D {0}; buf =3D aml_buffer(1, byte_list); aml_append(ifctx1, aml_return(buf)); aml_append(ifctx, ifctx1); --=20 2.43.0 From nobody Fri Nov 14 23:30:28 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" From: Eric Auger Add a 'preserve_config' field in struct GPEXConfig and if set, generate the DSM #5 for preserving PCI boot configurations. For SMMUV3 accel=3Don suppor= t, we are making use of IORT RMRs in a subsequent patch and that requires the DSM #5. At the moment the DSM generation is not yet enabled. Signed-off-by: Eric Auger [Shameer: Removed possible duplicate _DSM creations] Signed-off-by: Shameer Kolothum Signed-off-by: Shameer Kolothum Tested-by: Zhangfei Gao --- Previously, QEMU reverted an attempt to enable DSM #5 because it caused a regression, https://lore.kernel.org/all/20210724185234.GA2265457@roeck-us.net/. However, in this series, we enable it selectively, only when SMMUv3 is in accelerator mode. The devices involved in the earlier regression are not expected in accelerated SMMUv3 use cases. --- hw/pci-host/gpex-acpi.c | 29 +++++++++++++++++++++++------ include/hw/pci-host/gpex.h | 1 + 2 files changed, 24 insertions(+), 6 deletions(-) diff --git a/hw/pci-host/gpex-acpi.c b/hw/pci-host/gpex-acpi.c index 4587baeb78..e3825ed0b1 100644 --- a/hw/pci-host/gpex-acpi.c +++ b/hw/pci-host/gpex-acpi.c @@ -51,10 +51,11 @@ static void acpi_dsdt_add_pci_route_table(Aml *dev, uin= t32_t irq, } } =20 -static Aml *build_pci_host_bridge_dsm_method(void) +static Aml *build_pci_host_bridge_dsm_method(bool preserve_config) { Aml *method =3D aml_method("_DSM", 4, AML_NOTSERIALIZED); Aml *UUID, *ifctx, *ifctx1, *buf; + uint8_t byte_list[1] =3D {0}; =20 /* PCI Firmware Specification 3.0 * 4.6.1. _DSM for PCI Express Slot Information @@ -64,10 +65,23 @@ static Aml *build_pci_host_bridge_dsm_method(void) UUID =3D aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D"); ifctx =3D aml_if(aml_equal(aml_arg(0), UUID)); ifctx1 =3D aml_if(aml_equal(aml_arg(2), aml_int(0))); - uint8_t byte_list[1] =3D {0}; + if (preserve_config) { + /* support for function 0 and function 5 */ + byte_list[0] =3D 0x21; + } buf =3D aml_buffer(1, byte_list); aml_append(ifctx1, aml_return(buf)); aml_append(ifctx, ifctx1); + if (preserve_config) { + Aml *ifctx2 =3D aml_if(aml_equal(aml_arg(2), aml_int(5))); + /* + * 0 - The operating system must not ignore the PCI configuration = that + * firmware has done at boot time. + */ + aml_append(ifctx2, aml_return(aml_int(0))); + aml_append(ifctx, ifctx2); + } + aml_append(method, ifctx); =20 byte_list[0] =3D 0; @@ -77,12 +91,13 @@ static Aml *build_pci_host_bridge_dsm_method(void) } =20 static void acpi_dsdt_add_host_bridge_methods(Aml *dev, - bool enable_native_pcie_hotp= lug) + bool enable_native_pcie_hotp= lug, + bool preserve_config) { /* Declare an _OSC (OS Control Handoff) method */ aml_append(dev, build_pci_host_bridge_osc_method(enable_native_pcie_hotplug= )); - aml_append(dev, build_pci_host_bridge_dsm_method()); + aml_append(dev, build_pci_host_bridge_dsm_method(preserve_config)); } =20 void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg) @@ -152,7 +167,8 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *= cfg) build_cxl_osc_method(dev); } else { /* pxb bridges do not have ACPI PCI Hot-plug enabled */ - acpi_dsdt_add_host_bridge_methods(dev, true); + acpi_dsdt_add_host_bridge_methods(dev, true, + cfg->preserve_config); } =20 aml_append(scope, dev); @@ -227,7 +243,8 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *= cfg) } aml_append(dev, aml_name_decl("_CRS", rbuf)); =20 - acpi_dsdt_add_host_bridge_methods(dev, cfg->pci_native_hotplug); + acpi_dsdt_add_host_bridge_methods(dev, cfg->pci_native_hotplug, + cfg->preserve_config); =20 Aml *dev_res0 =3D aml_device("%s", "RES0"); aml_append(dev_res0, aml_name_decl("_HID", aml_string("PNP0C02"))); diff --git a/include/hw/pci-host/gpex.h b/include/hw/pci-host/gpex.h index feaf827474..7eea16e728 100644 --- a/include/hw/pci-host/gpex.h +++ b/include/hw/pci-host/gpex.h @@ -46,6 +46,7 @@ struct GPEXConfig { int irq; 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charset="utf-8" In a subsequent patch, SMMUv3 accel mode will make use of IORT RMR nodes to enable nested translation of MSI doorbell addresses. IORT RMR requires _DSM #5 to be set for the PCI host bridge so that the Guest kernel preserves the PCI boot configuration. Signed-off-by: Shameer Kolothum Reviewed-by: Jonathan Cameron Tested-by: Zhangfei Gao --- hw/arm/virt-acpi-build.c | 8 ++++++++ hw/arm/virt.c | 4 ++++ include/hw/arm/virt.h | 1 + 3 files changed, 13 insertions(+) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 96830f7c4e..fd03b7f6a9 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -163,6 +163,14 @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMap= Entry *memmap, .pci_native_hotplug =3D !acpi_pcihp, }; =20 + /* + * Accel SMMU requires RMRs for MSI 1-1 mapping, which + * require _DSM for preserving PCI Boot Configurations + */ + if (vms->pci_preserve_config) { + cfg.preserve_config =3D true; + } + if (vms->highmem_mmio) { cfg.mmio64 =3D memmap[VIRT_HIGH_PCIE_MMIO]; } diff --git a/hw/arm/virt.c b/hw/arm/virt.c index b533b0556e..6467d7cfc8 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -3087,6 +3087,10 @@ static void virt_machine_device_plug_cb(HotplugHandl= er *hotplug_dev, } =20 create_smmuv3_dev_dtb(vms, dev, bus); + if (object_property_get_bool(OBJECT(dev), "accel", &error_abor= t) && + !vms->pci_preserve_config) { + vms->pci_preserve_config =3D true; + } } } =20 diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index ea2cff05b0..00287941a9 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -180,6 +180,7 @@ struct VirtMachineState { bool ns_el2_virt_timer_irq; CXLState cxl_devices_state; bool legacy_smmuv3_present; + bool pci_preserve_config; }; =20 #define VIRT_ECAM_ID(high) (high ? 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charset="utf-8" From: Eric Auger To handle SMMUv3 nested stage support it is practical to expose the guest with reserved memory regions (RMRs) covering the IOVAs used by the host kernel to map physical MSI doorbells. Those IOVAs belong to [0x8000000, 0x8100000] matching MSI_IOVA_BASE and MSI_IOVA_LENGTH definitions in kernel arm-smmu-v3 driver. This is the window used to allocate IOVAs matching physical MSI doorbells. With those RMRs, the guest is forced to use a flat mapping for this range. Hence the assigned device is programmed with one IOVA from this range. Stage 1, owned by the guest has a flat mapping for this IOVA. Stage2, owned by the VMM then enforces a mapping from this IOVA to the physical MSI doorbell. The creation of those RMR nodes is only relevant if nested stage SMMU is in use, along with VFIO. As VFIO devices can be hotplugged, all RMRs need to be created in advance. Signed-off-by: Eric Auger Suggested-by: Jean-Philippe Brucker Signed-off-by: Nicolin Chen Signed-off-by: Shameer Kolothum Signed-off-by: Shameer Kolothum Tested-by: Zhangfei Gao --- hw/arm/virt-acpi-build.c | 75 ++++++++++++++++++++++++++++++++++++---- 1 file changed, 68 insertions(+), 7 deletions(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index fd03b7f6a9..d0c1e10019 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -264,7 +264,8 @@ static void acpi_dsdt_add_tpm(Aml *scope, VirtMachineSt= ate *vms) * Note that @id_count gets internally subtracted by one, following the sp= ec. */ static void build_iort_id_mapping(GArray *table_data, uint32_t input_base, - uint32_t id_count, uint32_t out_ref) + uint32_t id_count, uint32_t out_ref, + uint32_t flags) { build_append_int_noprefix(table_data, input_base, 4); /* Input base */ /* Number of IDs - The number of IDs in the range minus one */ @@ -272,7 +273,7 @@ static void build_iort_id_mapping(GArray *table_data, u= int32_t input_base, build_append_int_noprefix(table_data, input_base, 4); /* Output base */ build_append_int_noprefix(table_data, out_ref, 4); /* Output Reference= */ /* Flags */ - build_append_int_noprefix(table_data, 0 /* Single mapping (disabled) *= /, 4); + build_append_int_noprefix(table_data, flags, 4); } =20 struct AcpiIortIdMapping { @@ -320,6 +321,7 @@ typedef struct AcpiIortSMMUv3Dev { GArray *rc_smmu_idmaps; /* Offset of the SMMUv3 IORT Node relative to the start of the IORT */ size_t offset; + bool accel; } AcpiIortSMMUv3Dev; =20 /* @@ -374,6 +376,7 @@ static int iort_smmuv3_devices(Object *obj, void *opaqu= e) } =20 bus =3D PCI_BUS(object_property_get_link(obj, "primary-bus", &error_ab= ort)); + sdev.accel =3D object_property_get_bool(obj, "accel", &error_abort); pbus =3D PLATFORM_BUS_DEVICE(vms->platform_bus_dev); sbdev =3D SYS_BUS_DEVICE(obj); sdev.base =3D platform_bus_get_mmio_addr(pbus, sbdev, 0); @@ -447,6 +450,56 @@ static void create_rc_its_idmaps(GArray *its_idmaps, G= Array *smmuv3_devs) } } =20 +static void +build_iort_rmr_nodes(GArray *table_data, GArray *smmuv3_devices, uint32_t = *id) +{ + AcpiIortSMMUv3Dev *sdev; + AcpiIortIdMapping *idmap; + int i; + + for (i =3D 0; i < smmuv3_devices->len; i++) { + sdev =3D &g_array_index(smmuv3_devices, AcpiIortSMMUv3Dev, i); + idmap =3D &g_array_index(sdev->rc_smmu_idmaps, AcpiIortIdMapping, = 0); + int bdf =3D idmap->input_base; + + if (!sdev->accel) { + continue; + } + + /* Table 18 Reserved Memory Range Node */ + build_append_int_noprefix(table_data, 6 /* RMR */, 1); /* Type */ + /* Length */ + build_append_int_noprefix(table_data, 28 + ID_MAPPING_ENTRY_SIZE += 20, + 2); + build_append_int_noprefix(table_data, 3, 1); /* Revision */ + build_append_int_noprefix(table_data, *id, 4); /* Identifier */ + /* Number of ID mappings */ + build_append_int_noprefix(table_data, 1, 4); + /* Reference to ID Array */ + build_append_int_noprefix(table_data, 28, 4); + + /* RMR specific data */ + + /* Flags */ + build_append_int_noprefix(table_data, 0 /* Disallow remapping */, = 4); + /* Number of Memory Range Descriptors */ + build_append_int_noprefix(table_data, 1 , 4); + /* Reference to Memory Range Descriptors */ + build_append_int_noprefix(table_data, 28 + ID_MAPPING_ENTRY_SIZE, = 4); + build_iort_id_mapping(table_data, bdf, idmap->id_count, sdev->offs= et, + 1); + + /* Table 19 Memory Range Descriptor */ + + /* Physical Range offset */ + build_append_int_noprefix(table_data, 0x8000000, 8); + /* Physical Range length */ + build_append_int_noprefix(table_data, 0x100000, 8); + build_append_int_noprefix(table_data, 0, 4); /* Reserved */ + *id +=3D 1; + } +} + /* * Input Output Remapping Table (IORT) * Conforms to "IO Remapping Table System Software on ARM Platforms", @@ -464,7 +517,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) GArray *smmuv3_devs =3D g_array_new(false, true, sizeof(AcpiIortSMMUv3= Dev)); GArray *rc_its_idmaps =3D g_array_new(false, true, sizeof(AcpiIortIdMa= pping)); =20 - AcpiTable table =3D { .sig =3D "IORT", .rev =3D 3, .oem_id =3D vms->oe= m_id, + AcpiTable table =3D { .sig =3D "IORT", .rev =3D 5, .oem_id =3D vms->oe= m_id, .oem_table_id =3D vms->oem_table_id }; /* Table 2 The IORT */ acpi_table_begin(&table, table_data); @@ -490,6 +543,13 @@ build_iort(GArray *table_data, BIOSLinker *linker, Vir= tMachineState *vms) nb_nodes++; /* ITS */ rc_mapping_count +=3D rc_its_idmaps->len; } + /* Calculate RMR nodes required. One per SMMUv3 with accelerated m= ode */ + for (i =3D 0; i < num_smmus; i++) { + sdev =3D &g_array_index(smmuv3_devs, AcpiIortSMMUv3Dev, i); + if (sdev->accel) { + nb_nodes++; + } + } } else { if (vms->its) { nb_nodes =3D 2; /* RC and ITS */ @@ -562,7 +622,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) /* Array of ID mappings */ if (smmu_mapping_count) { /* Output IORT node is the ITS Group node (the first node). */ - build_iort_id_mapping(table_data, 0, 0x10000, IORT_NODE_OFFSET= ); + build_iort_id_mapping(table_data, 0, 0x10000, IORT_NODE_OFFSET= , 0); } } =20 @@ -614,7 +674,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) AcpiIortIdMapping, j); /* Output IORT node is the SMMUv3 node. */ build_iort_id_mapping(table_data, range->input_base, - range->id_count, sdev->offset); + range->id_count, sdev->offset, 0); } } =20 @@ -627,7 +687,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) range =3D &g_array_index(rc_its_idmaps, AcpiIortIdMapping,= i); /* Output IORT node is the ITS Group node (the first node)= . */ build_iort_id_mapping(table_data, range->input_base, - range->id_count, IORT_NODE_OFFSET); + range->id_count, IORT_NODE_OFFSET, 0= ); } } } else { @@ -636,9 +696,10 @@ build_iort(GArray *table_data, BIOSLinker *linker, Vir= tMachineState *vms) * SMMU: RC -> ITS. * Output IORT node is the ITS Group node (the first node). */ - build_iort_id_mapping(table_data, 0, 0x10000, IORT_NODE_OFFSET); + build_iort_id_mapping(table_data, 0, 0x10000, IORT_NODE_OFFSET, 0); } =20 + build_iort_rmr_nodes(table_data, smmuv3_devs, &id); acpi_table_end(linker, &table); g_array_free(rc_its_idmaps, true); for (i =3D 0; i < num_smmus; i++) { --=20 2.43.0 From nobody Fri Nov 14 23:30:28 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); 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charset="utf-8" When the guest reboots with devices in nested mode (S1 + S2), any QEMU/UEFI access to those devices can fail because S1 translation is not valid during the reboot. For example, a passthrough NVMe device may hold GRUB boot info that UEFI tries to read during the reboot. Set S1 to bypass mode during reset to avoid such failures. Reported-by: Matthew R. Ochs Signed-off-by: Shameer Kolothum Reviewed-by: Jonathan Cameron Tested-by: Zhangfei Gao --- hw/arm/smmuv3-accel.c | 29 +++++++++++++++++++++++++++++ hw/arm/smmuv3-accel.h | 4 ++++ hw/arm/smmuv3.c | 1 + 3 files changed, 34 insertions(+) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index defeddbd8c..8396053a6c 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -634,6 +634,35 @@ static const PCIIOMMUOps smmuv3_accel_ops =3D { .get_msi_address_space =3D smmuv3_accel_find_msi_as, }; =20 +/* + * If the guest reboots and devices are configured for S1+S2, Stage1 must + * be switched to bypass. Otherwise, QEMU/UEFI may fail when accessing a + * device, e.g. when UEFI retrieves boot partition information from an + * assigned vfio-pci NVMe device. + */ +void smmuv3_accel_attach_bypass_hwpt(SMMUv3State *s) +{ + SMMUv3AccelDevice *accel_dev; + SMMUViommu *viommu; + + if (!s->accel || !s->s_accel->viommu) { + return; + } + + viommu =3D s->s_accel->viommu; + QLIST_FOREACH(accel_dev, &viommu->device_list, next) { + if (!accel_dev->vdev) { + continue; + } + if (!host_iommu_device_iommufd_attach_hwpt(accel_dev->idev, + viommu->bypass_hwpt_id, + NULL)) { + error_report("Failed to install bypass hwpt id %u for dev id %= u", + viommu->bypass_hwpt_id, accel_dev->idev->devid); + } + } +} + void smmuv3_accel_init(SMMUv3State *s) { SMMUState *bs =3D ARM_SMMU(s); diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h index 3bdba47616..75f858e34a 100644 --- a/hw/arm/smmuv3-accel.h +++ b/hw/arm/smmuv3-accel.h @@ -48,6 +48,7 @@ bool smmuv3_accel_install_nested_ste_range(SMMUv3State *s= , SMMUSIDRange *range, Error **errp); bool smmuv3_accel_issue_inv_cmd(SMMUv3State *s, void *cmd, SMMUDevice *sde= v, Error **errp); +void smmuv3_accel_attach_bypass_hwpt(SMMUv3State *s); #else static inline void smmuv3_accel_init(SMMUv3State *s) { @@ -70,6 +71,9 @@ smmuv3_accel_issue_inv_cmd(SMMUv3State *s, void *cmd, SMM= UDevice *sdev, { return true; } +static inline void smmuv3_accel_attach_bypass_hwpt(SMMUv3State *s) +{ +} #endif =20 #endif /* HW_ARM_SMMUV3_ACCEL_H */ diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 5830cf5a03..94b2bbc374 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -1913,6 +1913,7 @@ static void smmu_reset_exit(Object *obj, ResetType ty= pe) if (c->parent_phases.exit) { c->parent_phases.exit(obj, type); } + smmuv3_accel_attach_bypass_hwpt(s); } =20 static void smmu_realize(DeviceState *d, Error **errp) --=20 2.43.0 From nobody Fri Nov 14 23:30:28 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Live migration is currently unsupported when accelerator mode is enabled, so a migration blocker is added. Because this mode relies on IORT RMR for MSI support, accelerator mode is not supported for device tree boot. Signed-off-by: Shameer Kolothum Reviewed-by: Eric Auger Reviewed-by: Nicolin Chen Tested-by: Zhangfei Gao --- hw/arm/smmuv3.c | 28 ++++++++++++++++++++++++++++ hw/arm/virt.c | 19 ++++++++++++------- include/hw/arm/smmuv3.h | 1 + 3 files changed, 41 insertions(+), 7 deletions(-) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 94b2bbc374..a0f704fc35 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -20,6 +20,7 @@ #include "qemu/bitops.h" #include "hw/irq.h" #include "hw/sysbus.h" +#include "migration/blocker.h" #include "migration/vmstate.h" #include "hw/qdev-properties.h" #include "hw/qdev-core.h" @@ -1916,6 +1917,17 @@ static void smmu_reset_exit(Object *obj, ResetType t= ype) smmuv3_accel_attach_bypass_hwpt(s); } =20 +static bool smmu_validate_property(SMMUv3State *s, Error **errp) +{ +#ifndef CONFIG_ARM_SMMUV3_ACCEL + if (s->accel) { + error_setg(errp, "accel=3Don support not compiled in"); + return false; + } +#endif + return true; +} + static void smmu_realize(DeviceState *d, Error **errp) { SMMUState *sys =3D ARM_SMMU(d); @@ -1924,8 +1936,17 @@ static void smmu_realize(DeviceState *d, Error **err= p) SysBusDevice *dev =3D SYS_BUS_DEVICE(d); Error *local_err =3D NULL; =20 + if (!smmu_validate_property(s, errp)) { + return; + } + if (s->accel) { smmuv3_accel_init(s); + error_setg(&s->migration_blocker, "Migration not supported with SM= MUv3 " + "accelerator mode enabled"); + if (migrate_add_blocker(&s->migration_blocker, errp) < 0) { + return; + } } =20 c->parent_realize(d, &local_err); @@ -2025,6 +2046,7 @@ static const Property smmuv3_properties[] =3D { * Defaults to stage 1 */ DEFINE_PROP_STRING("stage", SMMUv3State, stage), + DEFINE_PROP_BOOL("accel", SMMUv3State, accel, false), }; =20 static void smmuv3_instance_init(Object *obj) @@ -2046,6 +2068,12 @@ static void smmuv3_class_init(ObjectClass *klass, co= nst void *data) device_class_set_props(dc, smmuv3_properties); dc->hotpluggable =3D false; dc->user_creatable =3D true; + + object_class_property_set_description(klass, + "accel", + "Enable SMMUv3 accelerator suppo= rt." + "Allows host SMMUv3 to be config= ured " + "in nested mode for vfio-pci dev= assignment"); } =20 static int smmuv3_notify_flag_changed(IOMMUMemoryRegion *iommu, diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 6467d7cfc8..6b789fd7b5 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1474,8 +1474,8 @@ static void create_smmuv3_dt_bindings(const VirtMachi= neState *vms, hwaddr base, g_free(node); } =20 -static void create_smmuv3_dev_dtb(VirtMachineState *vms, - DeviceState *dev, PCIBus *bus) +static void create_smmuv3_dev_dtb(VirtMachineState *vms, DeviceState *dev, + PCIBus *bus, Error **errp) { PlatformBusDevice *pbus =3D PLATFORM_BUS_DEVICE(vms->platform_bus_dev); SysBusDevice *sbdev =3D SYS_BUS_DEVICE(dev); @@ -1483,10 +1483,15 @@ static void create_smmuv3_dev_dtb(VirtMachineState = *vms, hwaddr base =3D platform_bus_get_mmio_addr(pbus, sbdev, 0); MachineState *ms =3D MACHINE(vms); =20 - if (!(vms->bootinfo.firmware_loaded && virt_is_acpi_enabled(vms)) && - strcmp("pcie.0", bus->qbus.name)) { - warn_report("SMMUv3 device only supported with pcie.0 for DT"); - return; + if (!(vms->bootinfo.firmware_loaded && virt_is_acpi_enabled(vms))) { + if (object_property_get_bool(OBJECT(dev), "accel", &error_abort)) { + error_setg(errp, "SMMUv3 with accel=3Don not supported for DT"= ); + return; + } + if (strcmp("pcie.0", bus->qbus.name)) { + warn_report("SMMUv3 device only supported with pcie.0 for DT"); + return; + } } base +=3D vms->memmap[VIRT_PLATFORM_BUS].base; irq +=3D vms->irqmap[VIRT_PLATFORM_BUS]; @@ -3086,7 +3091,7 @@ static void virt_machine_device_plug_cb(HotplugHandle= r *hotplug_dev, } } =20 - create_smmuv3_dev_dtb(vms, dev, bus); + create_smmuv3_dev_dtb(vms, dev, bus, errp); if (object_property_get_bool(OBJECT(dev), "accel", &error_abor= t) && !vms->pci_preserve_config) { vms->pci_preserve_config =3D true; diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index 5f3e9089a7..874cbaaf32 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -67,6 +67,7 @@ struct SMMUv3State { /* SMMU has HW accelerator support for nested S1 + s2 */ bool accel; struct SMMUv3AccelState *s_accel; + Error *migration_blocker; }; =20 typedef enum { --=20 2.43.0 From nobody Fri Nov 14 23:30:28 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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But if accelerated mode is enabled, RIL has=C2=A0to be compatible with host SMMUv3 support. Add a property so that the user can specify this. Signed-off-by: Shameer Kolothum Reviewed-by: Jonathan Cameron Tested-by: Zhangfei Gao --- hw/arm/smmuv3-accel.c | 16 ++++++++++++++-- hw/arm/smmuv3-accel.h | 4 ++++ hw/arm/smmuv3.c | 13 +++++++++++++ include/hw/arm/smmuv3.h | 1 + 4 files changed, 32 insertions(+), 2 deletions(-) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 8396053a6c..e8607b253e 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -79,10 +79,10 @@ smmuv3_accel_check_hw_compatible(SMMUv3State *s, return false; } =20 - /* QEMU SMMUv3 supports Range Invalidation by default */ + /* User can override QEMU SMMUv3 Range Invalidation support */ val =3D FIELD_EX32(info->idr[3], IDR3, RIL); if (val !=3D FIELD_EX32(s->idr[3], IDR3, RIL)) { - error_setg(errp, "Host SUMMUv3 deosn't support Range Invalidation"= ); + error_setg(errp, "Host SUMMUv3 differs in Range Invalidation suppo= rt"); return false; } =20 @@ -634,6 +634,18 @@ static const PCIIOMMUOps smmuv3_accel_ops =3D { .get_msi_address_space =3D smmuv3_accel_find_msi_as, }; =20 +void smmuv3_accel_idr_override(SMMUv3State *s) +{ + if (!s->accel) { + return; + } + + /* By default QEMU SMMUv3 has RIL. Update IDR3 if user has disabled it= */ + if (!s->ril) { + s->idr[3] =3D FIELD_DP32(s->idr[3], IDR3, RIL, 0); + } +} + /* * If the guest reboots and devices are configured for S1+S2, Stage1 must * be switched to bypass. Otherwise, QEMU/UEFI may fail when accessing a diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h index 75f858e34a..357d8352c5 100644 --- a/hw/arm/smmuv3-accel.h +++ b/hw/arm/smmuv3-accel.h @@ -49,6 +49,7 @@ bool smmuv3_accel_install_nested_ste_range(SMMUv3State *s= , SMMUSIDRange *range, bool smmuv3_accel_issue_inv_cmd(SMMUv3State *s, void *cmd, SMMUDevice *sde= v, Error **errp); void smmuv3_accel_attach_bypass_hwpt(SMMUv3State *s); +void smmuv3_accel_idr_override(SMMUv3State *s); #else static inline void smmuv3_accel_init(SMMUv3State *s) { @@ -74,6 +75,9 @@ smmuv3_accel_issue_inv_cmd(SMMUv3State *s, void *cmd, SMM= UDevice *sdev, static inline void smmuv3_accel_attach_bypass_hwpt(SMMUv3State *s) { } +static inline void smmuv3_accel_idr_override(SMMUv3State *s) +{ +} #endif =20 #endif /* HW_ARM_SMMUV3_ACCEL_H */ diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index a0f704fc35..0f3a61646a 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -300,6 +300,8 @@ static void smmuv3_init_regs(SMMUv3State *s) s->idr[5] =3D FIELD_DP32(s->idr[5], IDR5, GRAN16K, 1); s->idr[5] =3D FIELD_DP32(s->idr[5], IDR5, GRAN64K, 1); =20 + smmuv3_accel_idr_override(s); + s->cmdq.base =3D deposit64(s->cmdq.base, 0, 5, SMMU_CMDQS); s->cmdq.prod =3D 0; s->cmdq.cons =3D 0; @@ -1925,6 +1927,13 @@ static bool smmu_validate_property(SMMUv3State *s, E= rror **errp) return false; } #endif + if (s->accel) { + return true; + } + if (!s->ril) { + error_setg(errp, "ril can only be disabled if accel=3Don"); + return false; + } return true; } =20 @@ -2047,6 +2056,8 @@ static const Property smmuv3_properties[] =3D { */ DEFINE_PROP_STRING("stage", SMMUv3State, stage), DEFINE_PROP_BOOL("accel", SMMUv3State, accel, false), + /* RIL can be turned off for accel cases */ + DEFINE_PROP_BOOL("ril", SMMUv3State, ril, true), }; =20 static void smmuv3_instance_init(Object *obj) @@ -2074,6 +2085,8 @@ static void smmuv3_class_init(ObjectClass *klass, con= st void *data) "Enable SMMUv3 accelerator suppo= rt." "Allows host SMMUv3 to be config= ured " "in nested mode for vfio-pci dev= assignment"); + object_class_property_set_description(klass, "ril", + "Enable/disable range invalidation support"); } =20 static int smmuv3_notify_flag_changed(IOMMUMemoryRegion *iommu, diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index 874cbaaf32..c555ea684e 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -68,6 +68,7 @@ struct SMMUv3State { bool accel; struct SMMUv3AccelState *s_accel; Error *migration_blocker; + bool ril; }; =20 typedef enum { --=20 2.43.0 From nobody Fri Nov 14 23:30:28 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass(p=reject dis=none) header.from=nvidia.com ARC-Seal: i=2; a=rsa-sha256; t=1759153862; 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charset="utf-8" QEMU SMMUv3 does not enable ATS (Address Translation Services) by default. When accelerated mode is enabled and the host SMMUv3 supports ATS, it can be useful to report ATS capability to the guest so it can take advantage of it if the device also supports ATS. Note: ATS support cannot be reliably detected from the host SMMUv3 IDR registers alone, as firmware ACPI IORT tables may override them. The user must therefore ensure the support before enabling it. Signed-off-by: Shameer Kolothum Reviewed-by: Jonathan Cameron Tested-by: Zhangfei Gao --- hw/arm/smmuv3-accel.c | 4 ++++ hw/arm/smmuv3.c | 25 ++++++++++++++++++++++++- hw/arm/virt-acpi-build.c | 10 ++++++++-- include/hw/arm/smmuv3.h | 1 + 4 files changed, 37 insertions(+), 3 deletions(-) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index e8607b253e..eee54316bf 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -644,6 +644,10 @@ void smmuv3_accel_idr_override(SMMUv3State *s) if (!s->ril) { s->idr[3] =3D FIELD_DP32(s->idr[3], IDR3, RIL, 0); } + /* QEMU SMMUv3 has no ATS. Update IDR0 if user has enabled it */ + if (s->ats) { + s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, ATS, 1); /* ATS */ + } } =20 /* diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 0f3a61646a..77d46a9cd6 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -1510,13 +1510,28 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) */ smmuv3_range_inval(bs, &cmd, SMMU_STAGE_2); break; + case SMMU_CMD_ATC_INV: + { + SMMUDevice *sdev =3D smmu_find_sdev(bs, CMD_SID(&cmd)); + Error *local_err =3D NULL; + + if (!sdev) { + break; + } + + if (!smmuv3_accel_issue_inv_cmd(s, &cmd, sdev, &local_err)) { + error_report_err(local_err); + cmd_error =3D SMMU_CERROR_ILL; + break; + } + break; + } case SMMU_CMD_TLBI_EL3_ALL: case SMMU_CMD_TLBI_EL3_VA: case SMMU_CMD_TLBI_EL2_ALL: case SMMU_CMD_TLBI_EL2_ASID: case SMMU_CMD_TLBI_EL2_VA: case SMMU_CMD_TLBI_EL2_VAA: - case SMMU_CMD_ATC_INV: case SMMU_CMD_PRI_RESP: case SMMU_CMD_RESUME: case SMMU_CMD_STALL_TERM: @@ -1934,6 +1949,10 @@ static bool smmu_validate_property(SMMUv3State *s, E= rror **errp) error_setg(errp, "ril can only be disabled if accel=3Don"); return false; } + if (s->ats) { + error_setg(errp, "ats can only be enabled if accel=3Don"); + return false; + } return true; } =20 @@ -2058,6 +2077,7 @@ static const Property smmuv3_properties[] =3D { DEFINE_PROP_BOOL("accel", SMMUv3State, accel, false), /* RIL can be turned off for accel cases */ DEFINE_PROP_BOOL("ril", SMMUv3State, ril, true), + DEFINE_PROP_BOOL("ats", SMMUv3State, ats, false), }; =20 static void smmuv3_instance_init(Object *obj) @@ -2087,6 +2107,9 @@ static void smmuv3_class_init(ObjectClass *klass, con= st void *data) "in nested mode for vfio-pci dev= assignment"); object_class_property_set_description(klass, "ril", "Enable/disable range invalidation support"); + object_class_property_set_description(klass, "ats", + "Enable/disable ATS support. Please ensure host platform has ATS " + "support before enabling this"); } =20 static int smmuv3_notify_flag_changed(IOMMUMemoryRegion *iommu, diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index d0c1e10019..a53f0229b8 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -322,6 +322,7 @@ typedef struct AcpiIortSMMUv3Dev { /* Offset of the SMMUv3 IORT Node relative to the start of the IORT */ size_t offset; bool accel; + bool ats; } AcpiIortSMMUv3Dev; =20 /* @@ -377,6 +378,7 @@ static int iort_smmuv3_devices(Object *obj, void *opaqu= e) =20 bus =3D PCI_BUS(object_property_get_link(obj, "primary-bus", &error_ab= ort)); sdev.accel =3D object_property_get_bool(obj, "accel", &error_abort); + sdev.ats =3D object_property_get_bool(obj, "ats", &error_abort); pbus =3D PLATFORM_BUS_DEVICE(vms->platform_bus_dev); sbdev =3D SYS_BUS_DEVICE(obj); sdev.base =3D platform_bus_get_mmio_addr(pbus, sbdev, 0); @@ -511,6 +513,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) int i, nb_nodes, rc_mapping_count; AcpiIortSMMUv3Dev *sdev; size_t node_size; + bool ats_needed =3D false; int num_smmus =3D 0; uint32_t id =3D 0; int rc_smmu_idmaps_len =3D 0; @@ -546,6 +549,9 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) /* Calculate RMR nodes required. One per SMMUv3 with accelerated m= ode */ for (i =3D 0; i < num_smmus; i++) { sdev =3D &g_array_index(smmuv3_devs, AcpiIortSMMUv3Dev, i); + if (sdev->ats) { + ats_needed =3D true; + } if (sdev->accel) { nb_nodes++; } @@ -645,8 +651,8 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) build_append_int_noprefix(table_data, 0, 2); /* Reserved */ /* Table 15 Memory Access Flags */ build_append_int_noprefix(table_data, 0x3 /* CCA =3D CPM =3D DACS =3D = 1 */, 1); - - build_append_int_noprefix(table_data, 0, 4); /* ATS Attribute */ + /* ATS Attribute */ + build_append_int_noprefix(table_data, (ats_needed ? 1 : 0), 4); /* MCFG pci_segment */ build_append_int_noprefix(table_data, 0, 4); /* PCI Segment number */ =20 diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index c555ea684e..6f07baa144 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -69,6 +69,7 @@ struct SMMUv3State { struct SMMUv3AccelState *s_accel; Error *migration_blocker; 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charset="utf-8" QEMU SMMUv3 currently sets the output address size (OAS) to 44 bits. With accelerator mode enabled, a guest device may use SVA where CPU page tables are shared with SMMUv3, requiring OAS at least equal to the CPU OAS. Add a user option to set this. Note: Linux kernel docs currently state the OAS field in the IDR register is not meaningful for users. But looks like we need this information. Signed-off-by: Shameer Kolothum Tested-by: Zhangfei Gao --- hw/arm/smmuv3-accel.c | 15 +++++++++++++++ hw/arm/smmuv3-internal.h | 3 ++- hw/arm/smmuv3.c | 15 ++++++++++++++- include/hw/arm/smmuv3.h | 1 + 4 files changed, 32 insertions(+), 2 deletions(-) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index eee54316bf..ba37d690ad 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -86,6 +86,17 @@ smmuv3_accel_check_hw_compatible(SMMUv3State *s, return false; } =20 + /* + * ToDo: OAS is not something Linux kernel doc says meaningful for use= r. + * But looks like OAS needs to be compatibe for accelerator support. P= lease + * check. + */ + val =3D FIELD_EX32(info->idr[5], IDR5, OAS); + if (val < FIELD_EX32(s->idr[5], IDR5, OAS)) { + error_setg(errp, "Host SUMMUv3 OAS not compatible"); + return false; + } + val =3D FIELD_EX32(info->idr[5], IDR5, GRAN4K); if (val !=3D FIELD_EX32(s->idr[5], IDR5, GRAN4K)) { error_setg(errp, "Host SMMUv3 doesn't support 64K translation gran= ule"); @@ -648,6 +659,10 @@ void smmuv3_accel_idr_override(SMMUv3State *s) if (s->ats) { s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, ATS, 1); /* ATS */ } + /* QEMU SMMUv3 has oas set 44. Update IDR5 if user has it set to 48 bi= ts*/ + if (s->oas =3D=3D 48) { + s->idr[5] =3D FIELD_DP32(s->idr[5], IDR5, OAS, SMMU_IDR5_OAS_48); + } } =20 /* diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h index b0dfa9465c..910a34e05b 100644 --- a/hw/arm/smmuv3-internal.h +++ b/hw/arm/smmuv3-internal.h @@ -111,7 +111,8 @@ REG32(IDR5, 0x14) FIELD(IDR5, VAX, 10, 2); FIELD(IDR5, STALL_MAX, 16, 16); =20 -#define SMMU_IDR5_OAS 4 +#define SMMU_IDR5_OAS_44 4 +#define SMMU_IDR5_OAS_48 5 =20 REG32(IIDR, 0x18) REG32(AIDR, 0x1c) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 77d46a9cd6..7c391ab711 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -294,7 +294,8 @@ static void smmuv3_init_regs(SMMUv3State *s) s->idr[3] =3D FIELD_DP32(s->idr[3], IDR3, RIL, 1); s->idr[3] =3D FIELD_DP32(s->idr[3], IDR3, BBML, 2); =20 - s->idr[5] =3D FIELD_DP32(s->idr[5], IDR5, OAS, SMMU_IDR5_OAS); /* 44 b= its */ + /* OAS: 44 bits */ + s->idr[5] =3D FIELD_DP32(s->idr[5], IDR5, OAS, SMMU_IDR5_OAS_44); /* 4K, 16K and 64K granule support */ s->idr[5] =3D FIELD_DP32(s->idr[5], IDR5, GRAN4K, 1); s->idr[5] =3D FIELD_DP32(s->idr[5], IDR5, GRAN16K, 1); @@ -1943,6 +1944,10 @@ static bool smmu_validate_property(SMMUv3State *s, E= rror **errp) } #endif if (s->accel) { + if (s->oas !=3D 44 && s->oas !=3D 48) { + error_setg(errp, "oas can only be set to 44 or 48 bits"); + return false; + } return true; } if (!s->ril) { @@ -1953,6 +1958,10 @@ static bool smmu_validate_property(SMMUv3State *s, E= rror **errp) error_setg(errp, "ats can only be enabled if accel=3Don"); return false; } + if (s->oas !=3D 44) { + error_setg(errp, "oas can only be set to 44 bits if accel=3Doff"); + return false; + } return true; } =20 @@ -2078,6 +2087,7 @@ static const Property smmuv3_properties[] =3D { /* RIL can be turned off for accel cases */ DEFINE_PROP_BOOL("ril", SMMUv3State, ril, true), DEFINE_PROP_BOOL("ats", SMMUv3State, ats, false), + DEFINE_PROP_UINT8("oas", SMMUv3State, oas, 44), }; =20 static void smmuv3_instance_init(Object *obj) @@ -2110,6 +2120,9 @@ static void smmuv3_class_init(ObjectClass *klass, con= st void *data) object_class_property_set_description(klass, "ats", "Enable/disable ATS support. Please ensure host platform has ATS " "support before enabling this"); + object_class_property_set_description(klass, "oas", + "Specify Output Address Size. Supported values are 44 or 48 bits " + "Defaults to 44 bits"); } =20 static int smmuv3_notify_flag_changed(IOMMUMemoryRegion *iommu, diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index 6f07baa144..d3788b2d85 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -70,6 +70,7 @@ struct SMMUv3State { Error *migration_blocker; bool ril; bool ats; + uint8_t oas; }; =20 typedef enum { --=20 2.43.0 From nobody Fri Nov 14 23:30:28 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass(p=reject dis=none) header.from=nvidia.com ARC-Seal: i=2; a=rsa-sha256; t=1759153867; cv=pass; d=zohomail.com; s=zohoarc; b=KO5VLC64hd7lig5j44c2aIsvgHIFZoCJEHHPe+fpHgjAV/VVV8bSHIZZV/XuYDQ39eIOP4qkOdhIF1wiRU5NtuTmhS2LQXJFxpFEIXlWwZvUChY7ki0tgpo03TBsrSJZYCnSWdt78dj4K5cbNAui+XgaNwdu/qkKz8L6EbacYB8= ARC-Message-Signature: i=2; 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charset="utf-8" And store it in HostIOMMUDeviceCaps for later use. Signed-off-by: Shameer Kolothum Reviewed-by: Eric Auger Reviewed-by: Jonathan Cameron Tested-by: Zhangfei Gao --- backends/iommufd.c | 6 +++++- hw/arm/smmuv3-accel.c | 3 ++- hw/vfio/iommufd.c | 7 +++++-- include/system/host_iommu_device.h | 2 ++ include/system/iommufd.h | 3 ++- 5 files changed, 16 insertions(+), 5 deletions(-) diff --git a/backends/iommufd.c b/backends/iommufd.c index d3029d4658..023e67bc46 100644 --- a/backends/iommufd.c +++ b/backends/iommufd.c @@ -388,7 +388,8 @@ bool iommufd_backend_get_dirty_bitmap(IOMMUFDBackend *b= e, =20 bool iommufd_backend_get_device_info(IOMMUFDBackend *be, uint32_t devid, uint32_t *type, void *data, uint32_t = len, - uint64_t *caps, Error **errp) + uint64_t *caps, uint8_t *pasid_log2, + Error **errp) { struct iommu_hw_info info =3D { .size =3D sizeof(info), @@ -407,6 +408,9 @@ bool iommufd_backend_get_device_info(IOMMUFDBackend *be= , uint32_t devid, g_assert(caps); *caps =3D info.out_capabilities; =20 + if (pasid_log2) { + *pasid_log2 =3D info.out_max_pasid_log2; + } return true; } =20 diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index ba37d690ad..283d36e6cd 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -124,7 +124,8 @@ smmuv3_accel_hw_compatible(SMMUv3State *s, HostIOMMUDev= iceIOMMUFD *idev, uint64_t caps; =20 if (!iommufd_backend_get_device_info(idev->iommufd, idev->devid, &data= _type, - &info, sizeof(info), &caps, errp)= ) { + &info, sizeof(info), &caps, NULL, + errp)) { return false; } =20 diff --git a/hw/vfio/iommufd.c b/hw/vfio/iommufd.c index 525df30ed1..89aa1b76a8 100644 --- a/hw/vfio/iommufd.c +++ b/hw/vfio/iommufd.c @@ -366,7 +366,8 @@ static bool iommufd_cdev_autodomains_get(VFIODevice *vb= asedev, * instead. */ if (!iommufd_backend_get_device_info(vbasedev->iommufd, vbasedev->devi= d, - &type, NULL, 0, &hw_caps, errp)) { + &type, NULL, 0, &hw_caps, NULL, + errp)) { return false; } =20 @@ -901,19 +902,21 @@ static bool hiod_iommufd_vfio_realize(HostIOMMUDevice= *hiod, void *opaque, HostIOMMUDeviceCaps *caps =3D &hiod->caps; VendorCaps *vendor_caps =3D &caps->vendor_caps; enum iommu_hw_info_type type; + uint8_t pasid_log2; uint64_t hw_caps; =20 hiod->agent =3D opaque; =20 if (!iommufd_backend_get_device_info(vdev->iommufd, vdev->devid, &type, vendor_caps, sizeof(*vendor_caps), - &hw_caps, errp)) { + &hw_caps, &pasid_log2, errp)) { return false; } =20 hiod->name =3D g_strdup(vdev->name); caps->type =3D type; caps->hw_caps =3D hw_caps; + caps->max_pasid_log2 =3D pasid_log2; =20 idev =3D HOST_IOMMU_DEVICE_IOMMUFD(hiod); idev->iommufd =3D vdev->iommufd; diff --git a/include/system/host_iommu_device.h b/include/system/host_iommu= _device.h index ab849a4a82..c6a2a3899a 100644 --- a/include/system/host_iommu_device.h +++ b/include/system/host_iommu_device.h @@ -29,6 +29,7 @@ typedef union VendorCaps { * * @hw_caps: host platform IOMMU capabilities (e.g. on IOMMUFD this repres= ents * the @out_capabilities value returned from IOMMU_GET_HW_INFO i= octl) + * @max_pasid_log2: width of PASIDs supported by host IOMMU device * * @vendor_caps: host platform IOMMU vendor specific capabilities (e.g. on * IOMMUFD this represents a user-space buffer filled by ker= nel @@ -37,6 +38,7 @@ typedef union VendorCaps { typedef struct HostIOMMUDeviceCaps { uint32_t type; uint64_t hw_caps; + uint8_t max_pasid_log2; VendorCaps vendor_caps; } HostIOMMUDeviceCaps; #endif diff --git a/include/system/iommufd.h b/include/system/iommufd.h index e852193f35..d3efcffc45 100644 --- a/include/system/iommufd.h +++ b/include/system/iommufd.h @@ -71,7 +71,8 @@ int iommufd_backend_unmap_dma(IOMMUFDBackend *be, uint32_= t ioas_id, hwaddr iova, ram_addr_t size); bool iommufd_backend_get_device_info(IOMMUFDBackend *be, uint32_t devid, uint32_t *type, void *data, uint32_t = len, - uint64_t *caps, Error **errp); + uint64_t *caps, uint8_t *pasid_log2, + Error **errp); bool iommufd_backend_alloc_hwpt(IOMMUFDBackend *be, uint32_t dev_id, uint32_t pt_id, uint32_t flags, uint32_t data_type, uint32_t data_len, --=20 2.43.0 From nobody Fri Nov 14 23:30:28 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Signed-off-by: Shameer Kolothum Tested-by: Zhangfei Gao --- backends/iommufd.c | 9 +++++++++ include/system/host_iommu_device.h | 12 ++++++++++++ 2 files changed, 21 insertions(+) diff --git a/backends/iommufd.c b/backends/iommufd.c index 023e67bc46..0ff46a5747 100644 --- a/backends/iommufd.c +++ b/backends/iommufd.c @@ -523,6 +523,14 @@ bool host_iommu_device_iommufd_detach_hwpt(HostIOMMUDe= viceIOMMUFD *idev, return idevc->detach_hwpt(idev, errp); } =20 +static uint8_t hiod_iommufd_get_pasid(HostIOMMUDevice *hiod, uint64_t *hw_= caps) +{ + HostIOMMUDeviceCaps *caps =3D &hiod->caps; + + *hw_caps =3D caps->hw_caps; + return caps->max_pasid_log2; +} + static int hiod_iommufd_get_cap(HostIOMMUDevice *hiod, int cap, Error **er= rp) { HostIOMMUDeviceCaps *caps =3D &hiod->caps; @@ -543,6 +551,7 @@ static void hiod_iommufd_class_init(ObjectClass *oc, co= nst void *data) HostIOMMUDeviceClass *hioc =3D HOST_IOMMU_DEVICE_CLASS(oc); =20 hioc->get_cap =3D hiod_iommufd_get_cap; + hioc->get_pasid =3D hiod_iommufd_get_pasid; }; =20 static const TypeInfo types[] =3D { diff --git a/include/system/host_iommu_device.h b/include/system/host_iommu= _device.h index c6a2a3899a..3773c54977 100644 --- a/include/system/host_iommu_device.h +++ b/include/system/host_iommu_device.h @@ -115,6 +115,18 @@ struct HostIOMMUDeviceClass { * @hiod: handle to the host IOMMU device */ uint64_t (*get_page_size_mask)(HostIOMMUDevice *hiod); + /** + * @get_pasid: Get PASID support information along this + * @hiod Host IOMMU device + * Optional callback. If not implemented, PASID not supported + * + * @hiod: handle to the host IOMMU device + * + * @out_hw_caps: Output the generic iommu capability info which includ= es + * device PASID CAP info + * Returns the width of PASIDs. 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charset="utf-8" From: Yi Liu If user wants to expose PASID capability in vIOMMU, then VFIO would also report the PASID cap for this device if the underlying hardware supports it as well. As a start, this chooses to put the vPASID cap in the last 8 bytes of the vconfig space. This is a choice in the good hope of no conflict with any existing cap or hidden registers. For the devices that has hidden registers, user should figure out a proper offset for the vPASID cap. This may require an option for user to config it. Here we leave it as a future extension. There are more discussions on the mechanism of finding the proper offset. https://lore.kernel.org/kvm/BN9PR11MB5276318969A212AD0649C7BE8CBE2@BN9PR11M= B5276.namprd11.prod.outlook.com/ Signed-off-by: Yi Liu Signed-off-by: Shameer Kolothum Tested-by: Zhangfei Gao --- hw/vfio/pci.c | 31 +++++++++++++++++++++++++++++++ include/hw/iommu.h | 1 + 2 files changed, 32 insertions(+) diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c index 5b022da19e..f54ebd0111 100644 --- a/hw/vfio/pci.c +++ b/hw/vfio/pci.c @@ -24,6 +24,7 @@ #include =20 #include "hw/hw.h" +#include "hw/iommu.h" #include "hw/pci/msi.h" #include "hw/pci/msix.h" #include "hw/pci/pci_bridge.h" @@ -2500,7 +2501,12 @@ static int vfio_setup_rebar_ecap(VFIOPCIDevice *vdev= , uint16_t pos) =20 static void vfio_add_ext_cap(VFIOPCIDevice *vdev) { + HostIOMMUDevice *hiod =3D vdev->vbasedev.hiod; + HostIOMMUDeviceClass *hiodc =3D HOST_IOMMU_DEVICE_GET_CLASS(hiod); PCIDevice *pdev =3D PCI_DEVICE(vdev); + uint8_t max_pasid_log2 =3D 0; + bool pasid_cap_added =3D false; + uint64_t hw_caps; uint32_t header; uint16_t cap_id, next, size; uint8_t cap_ver; @@ -2578,12 +2584,37 @@ static void vfio_add_ext_cap(VFIOPCIDevice *vdev) pcie_add_capability(pdev, cap_id, cap_ver, next, size); } break; + case PCI_EXT_CAP_ID_PASID: + pasid_cap_added =3D true; + /* fallthrough */ default: pcie_add_capability(pdev, cap_id, cap_ver, next, size); } =20 } =20 + /* + * If PCI_EXT_CAP_ID_PASID not present, try to get information from th= e host + */ + if (!pasid_cap_added && hiodc->get_pasid) { + max_pasid_log2 =3D hiodc->get_pasid(hiod, &hw_caps); + } + + /* + * If supported, adds the PASID capability in the end of the PCIE conf= ig + * space. TODO: Add option for enabling pasid at a safe offset. + */ + if (max_pasid_log2 && (pci_device_get_viommu_flags(pdev) & + VIOMMU_FLAG_PASID_SUPPORTED)) { + bool exec_perm =3D (hw_caps & IOMMU_HW_CAP_PCI_PASID_EXEC) ? true = : false; + bool priv_mod =3D (hw_caps & IOMMU_HW_CAP_PCI_PASID_PRIV) ? true := false; + + pcie_pasid_init(pdev, PCIE_CONFIG_SPACE_SIZE - PCI_EXT_CAP_PASID_S= IZEOF, + max_pasid_log2, exec_perm, priv_mod); + /* PASID capability is fully emulated by QEMU */ + memset(vdev->emulated_config_bits + pdev->exp.pasid_cap, 0xff, 8); + } + /* Cleanup chain head ID if necessary */ if (pci_get_word(pdev->config + PCI_CONFIG_SPACE_SIZE) =3D=3D 0xFFFF) { pci_set_word(pdev->config + PCI_CONFIG_SPACE_SIZE, 0); diff --git a/include/hw/iommu.h b/include/hw/iommu.h index 65d652950a..52e7f0cd96 100644 --- a/include/hw/iommu.h +++ b/include/hw/iommu.h @@ -14,6 +14,7 @@ enum { /* Nesting parent HWPT will be reused by vIOMMU to create nested HWPT = */ VIOMMU_FLAG_WANT_NESTING_PARENT =3D BIT_ULL(0), + VIOMMU_FLAG_PASID_SUPPORTED =3D BIT_ULL(1), }; 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charset="utf-8" QEMU SMMUv3 currently forces SSID (Substream ID) to zero. One key use case for accelerated mode is Shared Virtual Addressing (SVA), which requires SSID support so the guest can maintain multiple context descriptors per substream ID. Provide an option for user to enable PASID support. A SSIDSIZE of 16 is currently used as default. Signed-off-by: Shameer Kolothum Reviewed-by: Jonathan Cameron Tested-by: Zhangfei Gao --- hw/arm/smmuv3-accel.c | 24 +++++++++++++++++++++++- hw/arm/smmuv3-internal.h | 1 + hw/arm/smmuv3.c | 8 +++++++- include/hw/arm/smmuv3.h | 1 + 4 files changed, 32 insertions(+), 2 deletions(-) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 283d36e6cd..0de9598dcb 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -79,6 +79,13 @@ smmuv3_accel_check_hw_compatible(SMMUv3State *s, return false; } =20 + /* If user enables PASID support(pasid=3Don), QEMU sets SSIDSIZE to 16= */ + val =3D FIELD_EX32(info->idr[1], IDR1, SSIDSIZE); + if (val < FIELD_EX32(s->idr[1], IDR1, SSIDSIZE)) { + error_setg(errp, "Host SUMMUv3 SSIDSIZE not compatible"); + return false; + } + /* User can override QEMU SMMUv3 Range Invalidation support */ val =3D FIELD_EX32(info->idr[3], IDR3, RIL); if (val !=3D FIELD_EX32(s->idr[3], IDR3, RIL)) { @@ -635,7 +642,14 @@ static uint64_t smmuv3_accel_get_viommu_flags(void *op= aque) * The real HW nested support should be reported from host SMMUv3 and = if * it doesn't, the nesting parent allocation will fail anyway in VFIO = core. */ - return VIOMMU_FLAG_WANT_NESTING_PARENT; + uint64_t flags =3D VIOMMU_FLAG_WANT_NESTING_PARENT; + SMMUState *bs =3D opaque; + SMMUv3State *s =3D ARM_SMMUV3(bs); + + if (s->pasid) { + flags |=3D VIOMMU_FLAG_PASID_SUPPORTED; + } + return flags; } =20 static const PCIIOMMUOps smmuv3_accel_ops =3D { @@ -664,6 +678,14 @@ void smmuv3_accel_idr_override(SMMUv3State *s) if (s->oas =3D=3D 48) { s->idr[5] =3D FIELD_DP32(s->idr[5], IDR5, OAS, SMMU_IDR5_OAS_48); } + + /* + * By default QEMU SMMUv3 has no PASID(SSID) support. Update IDR1 if u= ser + * has enabled it. + */ + if (s->pasid) { + s->idr[1] =3D FIELD_DP32(s->idr[1], IDR1, SSIDSIZE, SMMU_IDR1_SSID= SIZE); + } } =20 /* diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h index 910a34e05b..38e9da245b 100644 --- a/hw/arm/smmuv3-internal.h +++ b/hw/arm/smmuv3-internal.h @@ -81,6 +81,7 @@ REG32(IDR1, 0x4) FIELD(IDR1, ECMDQ, 31, 1) =20 #define SMMU_IDR1_SIDSIZE 16 +#define SMMU_IDR1_SSIDSIZE 16 #define SMMU_CMDQS 19 #define SMMU_EVENTQS 19 =20 diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 7c391ab711..f7a1635ec7 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -604,7 +604,8 @@ static int decode_ste(SMMUv3State *s, SMMUTransCfg *cfg, } } =20 - if (STE_S1CDMAX(ste) !=3D 0) { + /* If pasid enabled, we report SSIDSIZE =3D 16 */ + if (!FIELD_EX32(s->idr[1], IDR1, SSIDSIZE) && STE_S1CDMAX(ste) !=3D 0)= { qemu_log_mask(LOG_UNIMP, "SMMUv3 does not support multiple context descriptor= s yet\n"); goto bad_ste; @@ -1962,6 +1963,10 @@ static bool smmu_validate_property(SMMUv3State *s, E= rror **errp) error_setg(errp, "oas can only be set to 44 bits if accel=3Doff"); return false; } + if (s->pasid) { + error_setg(errp, "pasid can only be enabled if accel=3Don"); + return false; + } return true; } =20 @@ -2088,6 +2093,7 @@ static const Property smmuv3_properties[] =3D { DEFINE_PROP_BOOL("ril", SMMUv3State, ril, true), DEFINE_PROP_BOOL("ats", SMMUv3State, ats, false), DEFINE_PROP_UINT8("oas", SMMUv3State, oas, 44), + DEFINE_PROP_BOOL("pasid", SMMUv3State, pasid, false), }; =20 static void smmuv3_instance_init(Object *obj) diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index d3788b2d85..3781b79fc8 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -71,6 +71,7 @@ struct SMMUv3State { bool ril; bool ats; uint8_t oas; + bool pasid; }; =20 typedef enum { --=20 2.43.0