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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=harshpb@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=-0.01, RCVD_IN_MSPIKE_WL=-0.01, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1759087674158116600 From: Aditya Gupta Existing code in XIVE2 assumes the chip to be a Power10 Chip. Instead add a handler to get reference to the interrupt controller (XIVE) for a given Power Chip. Signed-off-by: Aditya Gupta Reviewed-by: C=C3=A9dric Le Goater Tested-by: Amit Machhiwal Tested-by: C=C3=A9dric Le Goater Signed-off-by: Harsh Prateek Bora Link: https://lore.kernel.org/r/20250925173049.891406-4-adityag@linux.ibm.c= om Message-ID: <20250925173049.891406-4-adityag@linux.ibm.com> --- include/hw/ppc/pnv_chip.h | 1 + hw/intc/pnv_xive2.c | 4 ++-- hw/ppc/pnv.c | 12 ++++++++++++ 3 files changed, 15 insertions(+), 2 deletions(-) diff --git a/include/hw/ppc/pnv_chip.h b/include/hw/ppc/pnv_chip.h index 6bd930f8b4..a5b8c49680 100644 --- a/include/hw/ppc/pnv_chip.h +++ b/include/hw/ppc/pnv_chip.h @@ -170,6 +170,7 @@ struct PnvChipClass { void (*intc_reset)(PnvChip *chip, PowerPCCPU *cpu); void (*intc_destroy)(PnvChip *chip, PowerPCCPU *cpu); void (*intc_print_info)(PnvChip *chip, PowerPCCPU *cpu, GString *buf); + void* (*intc_get)(PnvChip *chip); ISABus *(*isa_create)(PnvChip *chip, Error **errp); void (*dt_populate)(PnvChip *chip, void *fdt); void (*pic_print_info)(PnvChip *chip, GString *buf); diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c index e019cad5c1..0663baab54 100644 --- a/hw/intc/pnv_xive2.c +++ b/hw/intc/pnv_xive2.c @@ -110,8 +110,8 @@ static PnvXive2 *pnv_xive2_get_remote(uint32_t vsd_type= , hwaddr fwd_addr) int i; =20 for (i =3D 0; i < pnv->num_chips; i++) { - Pnv10Chip *chip10 =3D PNV10_CHIP(pnv->chips[i]); - PnvXive2 *xive =3D &chip10->xive; + PnvChipClass *k =3D PNV_CHIP_GET_CLASS(pnv->chips[i]); + PnvXive2 *xive =3D PNV_XIVE2(k->intc_get(pnv->chips[i])); =20 /* * Is this the XIVE matching the forwarded VSD address is for this diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 423954ba7e..a4fdf59207 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -1486,6 +1486,16 @@ static void pnv_chip_power10_intc_print_info(PnvChip= *chip, PowerPCCPU *cpu, xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), buf); } =20 +static void *pnv_chip_power10_intc_get(PnvChip *chip) +{ + return &PNV10_CHIP(chip)->xive; +} + +static void *pnv_chip_power11_intc_get(PnvChip *chip) +{ + return &PNV11_CHIP(chip)->xive; +} + /* * Allowed core identifiers on a POWER8 Processor Chip : * @@ -2680,6 +2690,7 @@ static void pnv_chip_power10_class_init(ObjectClass *= klass, const void *data) k->intc_reset =3D pnv_chip_power10_intc_reset; k->intc_destroy =3D pnv_chip_power10_intc_destroy; k->intc_print_info =3D pnv_chip_power10_intc_print_info; + k->intc_get =3D pnv_chip_power10_intc_get; k->isa_create =3D pnv_chip_power10_isa_create; k->dt_populate =3D pnv_chip_power10_dt_populate; k->pic_print_info =3D pnv_chip_power10_pic_print_info; @@ -2709,6 +2720,7 @@ static void pnv_chip_power11_class_init(ObjectClass *= klass, const void *data) k->chip_cfam_id =3D 0x220da04980000000ull; /* P11 DD2.0 (with NX) */ k->cores_mask =3D POWER11_CORE_MASK; k->get_pir_tir =3D pnv_get_pir_tir_p10; + k->intc_get =3D pnv_chip_power11_intc_get; k->isa_create =3D pnv_chip_power11_isa_create; k->dt_populate =3D pnv_chip_power11_dt_populate; k->pic_print_info =3D pnv_chip_power11_pic_print_info; --=20 2.43.5