From nobody Fri Nov 14 23:29:46 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1759077238; cv=none; d=zohomail.com; s=zohoarc; b=QRVr/VrFbxMDGo25VTuZpy4z+XABMSYVyEIyBZ/2qXhAxbOa2KQG15KbMUUxz8wONJ+xYsIYdRUU7m7hF7FdCwlQJqO5OZKqj0WJCiSIhvZ4aFIqbscekjNQDg+o/1orCGzfiRsoswQ6mBmIW6+NL8JVVerSt4WfTbfGkb1RQLw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1759077238; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=w0XY9KSWG9rZfV1tYL0tGWSihRd8RTWjYxQ6oR/cY7w=; b=l/S++JEge0ETjrfVncL+NC3GkL05zWjzP+3jJ5n0A0kmwkUtb/3aGHkySxGrzfLaiXjT+UigYe9A12gX6e+zrWfydT3vNvAQkfAAhfgZyleDDY7Z6C7/EBtETS/CB92wvG7dZQtdcg/pZV7W/M1BeWkqiUZ1cfJtogslKsnn/Rw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1759077238122299.71361606907567; Sun, 28 Sep 2025 09:33:58 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v2uJr-000369-MZ; Sun, 28 Sep 2025 12:32:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v2uJo-00035V-9U for qemu-devel@nongnu.org; Sun, 28 Sep 2025 12:32:12 -0400 Received: from mail-pf1-x42f.google.com ([2607:f8b0:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1v2uJg-0005xy-U2 for qemu-devel@nongnu.org; Sun, 28 Sep 2025 12:32:10 -0400 Received: by mail-pf1-x42f.google.com with SMTP id d2e1a72fcca58-78125ed4052so1789711b3a.0 for ; Sun, 28 Sep 2025 09:32:00 -0700 (PDT) Received: from stoup.. ([71.212.157.132]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-27ed6996963sm107236335ad.104.2025.09.28.09.31.57 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Sep 2025 09:31:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1759077117; x=1759681917; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=w0XY9KSWG9rZfV1tYL0tGWSihRd8RTWjYxQ6oR/cY7w=; b=pKLNUSB/GW2xiq0dqhhhAV1yU5LSvHjR0ADa9ywz7e3vqC1N3AzOBpacZGPwY0rnAa Qn7XMs29ltwSYuMaxnexiyKqQJbbimxRwqnHsFRV9qmZbkHMNpCyPZOdgZqmGnug0JpJ qqQ/eHZDdd62gPMyi1w5kbLT7IiFEEuWFa9//wfoW7SDQIecAHYrXT926InD0NJvzGvr vAJ5ha3nav18HVJSvCkMuSZW29aOzqRdI08gnJOicRyQBnNCvFYoRNO/XnSDEUlVn+72 aCiCeWCDp5Pua19FVzN5tSdP0n6on7UKpbMXsPPI3AxV5QN30VTKq6vKPX/YzFeehwx1 U32A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1759077117; x=1759681917; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=w0XY9KSWG9rZfV1tYL0tGWSihRd8RTWjYxQ6oR/cY7w=; b=nHjp3d1nXYshxeBsUk09c7HXu9k/zhuxVo7XjvnFD/6QT7LXQlpWLsNcqXg0g5S7I4 fl9qPt7Iq6hqG9+7GqrwsE+/Kew2DrxK3Nhsl2U/DW/dTbMoU1cKswAMUfAz/mvQsGj+ oH9myJ4A7AmxEkhZrFqV5IdotJA6Zpsaap2Luta3qFN54jcxwWamoNvPkmuZ6nawtiF5 5+OIQFhFuS4Zvc6Gt7qr/KmYkmOtDbn8RmGQBQECMfc6gZ1TdzCpyOtFXnxyVp1PlSPy xP+g+zfD82V+JMOEo0rbPZuanZ6VzQtucFc4N5B6j+YoyD9h49oNnVJnmEyC/cwph8e/ aAzQ== X-Gm-Message-State: AOJu0Yy3YbuyQXI2njbdZB+6XOW0uGlpiHUDmcf562sMX43sQl6YmdmQ 58NSzcmx9Rm03V97rKp7EzEDNcFqykUrA11sQzVh1v/ID9jPrbXBK3Grl3AjL2lbAS1JJ4ilahN +PjucIlE= X-Gm-Gg: ASbGncs6yjFkSpMVYqVJp0CeJSDNTAzkriznLlheb0XALl6apLTJxcBQR5phaCbtHHf 7u3jbt6RXapN/54KtL4cs5/mYft2b/BBI8bbUZiBDDxwGkjX32oN7aqU/GFDGNCqyqoY4LdaTyY nFlDRNoNp9MBjlMWdclmpR3OKdSnFo+WOk4DJHKsrSzlxJbqyAKiMP/A5NREVRbNjLlepD+IYby 3MBYuEPOAUS224UsUnqQwKMD7m76WtbQGVawaAvJS5qS062a4syTmWmmzW1hZV7Nx6wiu36X+4G pGr+KkargUD/sbn6bfK49U5o7Blx1dIDie1EfTLjn5THsweLPrIwja7jdB3ftJWrOYXKWBXoVZU za8ZFuHJ9i6SRNW1kpm29JmxXetbj X-Google-Smtp-Source: AGHT+IGR3h09q8Aw5DyOYUR9r92d3zeA3dkSMr7jK0wfO2/edfkiKS5f6njwFyPY/qmZbQwSTHoquA== X-Received: by 2002:a17:902:f54c:b0:271:479d:3de3 with SMTP id d9443c01a7336-27ed49c7763mr157494395ad.12.1759077117436; Sun, 28 Sep 2025 09:31:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 1/5] tcg: Simplify extract2 usage in tcg_gen_shifti_i64 Date: Sun, 28 Sep 2025 09:31:51 -0700 Message-ID: <20250928163155.1472914-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250928163155.1472914-1-richard.henderson@linaro.org> References: <20250928163155.1472914-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1759077239850116600 Content-Type: text/plain; charset="utf-8" The else after the TCG_TARGET_HAS_extract2 test is exactly the same as what tcg_gen_extract2_i32 would emit itself. Signed-off-by: Richard Henderson Reviewed-by: Manos Pitsidianakis Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tcg/tcg-op.c | 22 ++++------------------ 1 file changed, 4 insertions(+), 18 deletions(-) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index dfa5c38728..ab7b409be6 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -1818,30 +1818,16 @@ static inline void tcg_gen_shifti_i64(TCGv_i64 ret,= TCGv_i64 arg1, tcg_gen_movi_i32(TCGV_LOW(ret), 0); } } else if (right) { - if (tcg_op_supported(INDEX_op_extract2, TCG_TYPE_I32, 0)) { - tcg_gen_extract2_i32(TCGV_LOW(ret), - TCGV_LOW(arg1), TCGV_HIGH(arg1), c); - } else { - tcg_gen_shri_i32(TCGV_LOW(ret), TCGV_LOW(arg1), c); - tcg_gen_deposit_i32(TCGV_LOW(ret), TCGV_LOW(ret), - TCGV_HIGH(arg1), 32 - c, c); - } + tcg_gen_extract2_i32(TCGV_LOW(ret), TCGV_LOW(arg1), + TCGV_HIGH(arg1), c); if (arith) { tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), c); } else { tcg_gen_shri_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), c); } } else { - if (tcg_op_supported(INDEX_op_extract2, TCG_TYPE_I32, 0)) { - tcg_gen_extract2_i32(TCGV_HIGH(ret), - TCGV_LOW(arg1), TCGV_HIGH(arg1), 32 - c); - } else { - TCGv_i32 t0 =3D tcg_temp_ebb_new_i32(); - tcg_gen_shri_i32(t0, TCGV_LOW(arg1), 32 - c); - tcg_gen_deposit_i32(TCGV_HIGH(ret), t0, - TCGV_HIGH(arg1), c, 32 - c); - tcg_temp_free_i32(t0); - } + tcg_gen_extract2_i32(TCGV_HIGH(ret), TCGV_LOW(arg1), + TCGV_HIGH(arg1), 32 - c); tcg_gen_shli_i32(TCGV_LOW(ret), TCGV_LOW(arg1), c); } } --=20 2.43.0 From nobody Fri Nov 14 23:29:46 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1759077239; cv=none; d=zohomail.com; s=zohoarc; b=buMaVlTQT8aLspJsrV9UMKDdPr6QX/0M1Fx+/E8mZyA7OLQFkuUhgO9BeroPf7+sd7pi4f7J0i/OqXYG2jjm892gkoct+tgqX/uWVOK7phcK79dTrv5gnDEjVW+06ZM+dKibuROPf0M2dmDMxDatL4CcdXicxmf9ml82UrO9hNA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1759077239; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=H3d7H8XovfFDI+ME0yUN7n1tyhLF4vt5e6dSGVMQOB0=; b=i17j5hKnY+mw10pNnYLAo2p4qYckhq+SJAvc8oqWTVLD0cpOn0sOV9Bm4v5DrHUDXmXa4VzOr93LCOgfDQI+OJ/lACSlTNKQePwMfbVLXlHP/uuMSVf8RzKLiJOW5d6amBnojKjoXOp7VI5KqvywDeaj0jdCaOKiZC1bawM2rsw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1759077239769544.4114247806285; Sun, 28 Sep 2025 09:33:59 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v2uK1-00037g-NS; Sun, 28 Sep 2025 12:32:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v2uJz-00036w-29 for qemu-devel@nongnu.org; Sun, 28 Sep 2025 12:32:23 -0400 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1v2uJj-0005y8-J3 for qemu-devel@nongnu.org; Sun, 28 Sep 2025 12:32:21 -0400 Received: by mail-pl1-x635.google.com with SMTP id d9443c01a7336-28832ad6f64so3814975ad.1 for ; Sun, 28 Sep 2025 09:32:05 -0700 (PDT) Received: from stoup.. ([71.212.157.132]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-27ed6996963sm107236335ad.104.2025.09.28.09.31.57 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Sep 2025 09:31:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1759077118; x=1759681918; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=H3d7H8XovfFDI+ME0yUN7n1tyhLF4vt5e6dSGVMQOB0=; b=GPbzmJRGYkHSk00RKOO4/rxMXerjebLIf62/H0dxIq4b9MC8+Tb0DcnEBFV36cmzS9 wzEwfli9A1ST8n5wmiIy5U2F2W79oySIBYT3+1b7+0zzwTnxFVanXa/I5Q1smbsyjoJe Bgcw/ySpcegDnv/ytpZyj0i5y3PKO8dwZUTrG5JFmihO/y38zB0wpIs/8ANKdje/5gRK MHF3qhtPmflzuIbphzi5LWFYI0U95quTavc2oCUpMpGSPITrAClBtsHzP9FRoz/sNOUt FGl8DcssDSKogvqj89wZfOOX/0eVSfJoFSy9ZrXUTeffgcq9ZREbxDH9KcbF0cRdyDgw aK1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1759077118; x=1759681918; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=H3d7H8XovfFDI+ME0yUN7n1tyhLF4vt5e6dSGVMQOB0=; b=BOqqa/NifWoJjfUKtQdCulOUsWNQKyfePA2p7Wdxi5kkIEiuMj8dqklWEFBPMM28KC 7/5lR5etpFV1WB1WUm85AjgRKaUmwLHCufHPwYoNlbOCzspjHOcj2vNcviDFJgCBXge9 wY0Cb7808A4FfK/4eMwzTldppq37fro1E3QZNoGM7WZCCoa2W65+HrNNbW0bwV7CJCZS /z2OJFN9eN0Fesm0dvev3PDguM5nK4E7zayte3kITXEzhyYpLqgHk3sF7H4zguxlHyGm EhF2Y/nblSxgSX5n2vzv1lO1bQuG3KC6o7myFEyCdEusz3HS1yertprv4xfJqeOiyW7P HRxA== X-Gm-Message-State: AOJu0YxgnSIHjscuPi/lw7Vw1PrN7tUJIu2JmGjZxopuALZQ61Z89FkS vsd2tm0CiXSyjn+wnnyZJAAs0gwMIEYOZNmuafbv8ctlFi9STya2XWmNU84Es2/YmLbycpR/ghR icTDlG48= X-Gm-Gg: ASbGncsQxAm65aHqsym0wzxvd9pJpSTI8hy75OOtryqvKqHSgO0+nW/JS+o1bQQqWwL DBiGTvinQ0MJt/9S/X32hZOZ43Ep9Bm6049t/m7cFeV6oNDxQiHIqZbCRKdrohughur4QVI10Q4 p/9xXCpVeXzxf7Hb3Ef6F5LDoADJF/TIaPBax/Jb+JFpq24YwvedyDKPa+2HCiqj/CO8sBczVdv hMjXDsa+mGchW0xFr53AfzwxYy0oASkSW3TrQEgLp2/BUonwclhT9KJmbAjWOOtLckQgfc34BLJ np3KFm/siRUhre37tU6vLYtGjAXR62/jmZ6/CeHDAvFnfy08vJAExkCoRjq2KwDVA0I/Y8SHOe5 UTXl7FHI9LFdE9FyAqdE/IBTVWCgbFG3qRFYPU9Y= X-Google-Smtp-Source: AGHT+IHNRi0VE/2ylg1KB5sZs+2jf16X0EwpDgsC6dHyRQszvPkMNK+4+rDwExxMvTjPpYSjrEfZsA== X-Received: by 2002:a17:903:ac4:b0:25c:76f1:b024 with SMTP id d9443c01a7336-27ed4a0e498mr172315075ad.25.1759077118135; Sun, 28 Sep 2025 09:31:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 2/5] tcg/optimize: Lower unsupported deposit during optimize Date: Sun, 28 Sep 2025 09:31:52 -0700 Message-ID: <20250928163155.1472914-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250928163155.1472914-1-richard.henderson@linaro.org> References: <20250928163155.1472914-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1759077241560116600 Content-Type: text/plain; charset="utf-8" The expansions that we chose in tcg-op.c may be less than optimial. Delay lowering until optimize, so that we have propagated constants and have computed known zero/one masks. Signed-off-by: Richard Henderson --- tcg/optimize.c | 194 +++++++++++++++++++++++++++++++++++++++++++------ tcg/tcg-op.c | 189 +++++++++++++++-------------------------------- 2 files changed, 230 insertions(+), 153 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index f69702b26e..5df57049c2 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -1865,12 +1865,17 @@ static bool fold_ctpop(OptContext *ctx, TCGOp *op) =20 static bool fold_deposit(OptContext *ctx, TCGOp *op) { - TempOptInfo *t1 =3D arg_info(op->args[1]); - TempOptInfo *t2 =3D arg_info(op->args[2]); + TCGArg ret =3D op->args[0]; + TCGArg arg1 =3D op->args[1]; + TCGArg arg2 =3D op->args[2]; int ofs =3D op->args[3]; int len =3D op->args[4]; - int width =3D 8 * tcg_type_size(ctx->type); - uint64_t z_mask, o_mask, s_mask; + TempOptInfo *t1 =3D arg_info(arg1); + TempOptInfo *t2 =3D arg_info(arg2); + int width; + uint64_t z_mask, o_mask, s_mask, type_mask, len_mask; + TCGOp *op2; + bool valid; =20 if (ti_is_const(t1) && ti_is_const(t2)) { return tcg_opt_gen_movi(ctx, op, op->args[0], @@ -1878,35 +1883,182 @@ static bool fold_deposit(OptContext *ctx, TCGOp *o= p) ti_const_val(t2))); } =20 - /* Inserting a value into zero at offset 0. */ - if (ti_is_const_val(t1, 0) && ofs =3D=3D 0) { - uint64_t mask =3D MAKE_64BIT_MASK(0, len); + width =3D 8 * tcg_type_size(ctx->type); + type_mask =3D MAKE_64BIT_MASK(0, width); + len_mask =3D MAKE_64BIT_MASK(0, len); =20 + /* Inserting all-zero into a value. */ + if ((t2->z_mask & len_mask) =3D=3D 0) { op->opc =3D INDEX_op_and; - op->args[1] =3D op->args[2]; - op->args[2] =3D arg_new_constant(ctx, mask); + op->args[2] =3D arg_new_constant(ctx, ~(len_mask << ofs)); return fold_and(ctx, op); } =20 - /* Inserting zero into a value. */ - if (ti_is_const_val(t2, 0)) { - uint64_t mask =3D deposit64(-1, ofs, len, 0); - - op->opc =3D INDEX_op_and; - op->args[2] =3D arg_new_constant(ctx, mask); - return fold_and(ctx, op); + /* Inserting all-one into a value. */ + if ((t2->o_mask & len_mask) =3D=3D len_mask) { + op->opc =3D INDEX_op_or; + op->args[2] =3D arg_new_constant(ctx, len_mask << ofs); + return fold_or(ctx, op); } =20 - /* The s_mask from the top portion of the deposit is still valid. */ - if (ofs + len =3D=3D width) { - s_mask =3D t2->s_mask << ofs; - } else { - s_mask =3D t1->s_mask & ~MAKE_64BIT_MASK(0, ofs + len); + valid =3D TCG_TARGET_deposit_valid(ctx->type, ofs, len); + + /* Lower invalid deposit of constant as AND + OR. */ + if (!valid && ti_is_const(t2)) { + uint64_t ins_val =3D (ti_const_val(t2) & len_mask) << ofs; + + op2 =3D opt_insert_before(ctx, op, INDEX_op_and, 3); + op2->args[0] =3D ret; + op2->args[1] =3D arg1; + op2->args[2] =3D arg_new_constant(ctx, ~(len_mask << ofs)); + fold_and(ctx, op2); + + op->opc =3D INDEX_op_or; + op->args[1] =3D ret; + op->args[2] =3D arg_new_constant(ctx, ins_val); + return fold_or(ctx, op); } =20 + /* + * Compute result masks before calling other fold_* subroutines + * which could modify the masks of our inputs. + */ z_mask =3D deposit64(t1->z_mask, ofs, len, t2->z_mask); o_mask =3D deposit64(t1->o_mask, ofs, len, t2->o_mask); + if (ofs + len < width) { + s_mask =3D t1->s_mask & ~MAKE_64BIT_MASK(0, ofs + len); + } else { + s_mask =3D t2->s_mask << ofs; + } =20 + /* Inserting a value into zero. */ + if (ti_is_const_val(t1, 0)) { + uint64_t need_mask; + + /* Always lower deposit into zero at 0 as AND. */ + if (ofs =3D=3D 0) { + op->opc =3D INDEX_op_and; + op->args[1] =3D arg2; + op->args[2] =3D arg_new_constant(ctx, len_mask); + return fold_and(ctx, op); + } + + /* + * If the portion of the value outside len that remains after + * shifting is zero, we can elide the mask and just shift. + */ + need_mask =3D t2->z_mask & ~len_mask; + need_mask =3D (need_mask << ofs) & type_mask; + if (!need_mask) { + op->opc =3D INDEX_op_shl; + op->args[1] =3D arg2; + op->args[2] =3D arg_new_constant(ctx, ofs); + goto done; + } + + /* Lower invalid deposit into zero as AND + SHL or SHL + AND. */ + if (!valid) { + if (TCG_TARGET_extract_valid(ctx->type, 0, ofs + len) && + !TCG_TARGET_extract_valid(ctx->type, 0, len)) { + op2 =3D opt_insert_before(ctx, op, INDEX_op_shl, 3); + op2->args[0] =3D ret; + op2->args[1] =3D arg2; + op2->args[2] =3D arg_new_constant(ctx, ofs); + + op->opc =3D INDEX_op_extract; + op->args[1] =3D ret; + op->args[2] =3D 0; + op->args[3] =3D ofs + len; + goto done; + } + + op2 =3D opt_insert_before(ctx, op, INDEX_op_and, 3); + op2->args[0] =3D ret; + op2->args[1] =3D arg2; + op2->args[2] =3D arg_new_constant(ctx, len_mask); + fold_and(ctx, op2); + + op->opc =3D INDEX_op_shl; + op->args[1] =3D ret; + op->args[2] =3D arg_new_constant(ctx, ofs); + goto done; + } + } + + /* After special cases, lower invalid deposit. */ + if (!valid) { + TCGArg tmp; + bool has_ext2 =3D tcg_op_supported(INDEX_op_extract2, ctx->type, 0= ); + bool has_rotl =3D tcg_op_supported(INDEX_op_rotl, ctx->type, 0); + + /* + * ret =3D arg2:arg1 >> len + * ret =3D rotl(ret, len) + */ + if (ofs =3D=3D 0 && has_ext2 && has_rotl) { + op2 =3D opt_insert_before(ctx, op, INDEX_op_extract2, 4); + op2->args[0] =3D ret; + op2->args[1] =3D arg1; + op2->args[2] =3D arg2; + op2->args[3] =3D len; + + op->opc =3D INDEX_op_rotl; + op->args[1] =3D ret; + op->args[2] =3D arg_new_constant(ctx, len); + goto done; + } + + /* + * tmp =3D arg1 << len + * ret =3D arg2:tmp >> len + */ + if (ofs + len =3D=3D width && has_ext2) { + tmp =3D ret =3D=3D arg2 ? arg_new_temp(ctx) : ret; + + op2 =3D opt_insert_before(ctx, op, INDEX_op_shl, 4); + op2->args[0] =3D tmp; + op2->args[1] =3D arg1; + op2->args[2] =3D arg_new_constant(ctx, len); + + op->opc =3D INDEX_op_extract2; + op->args[0] =3D ret; + op->args[1] =3D tmp; + op->args[2] =3D arg2; + op->args[3] =3D len; + goto done; + } + + /* + * tmp =3D arg2 & mask + * ret =3D arg1 & ~(mask << ofs) + * tmp =3D tmp << ofs + * ret =3D ret | tmp + */ + tmp =3D arg_new_temp(ctx); + + op2 =3D opt_insert_before(ctx, op, INDEX_op_and, 3); + op2->args[0] =3D tmp; + op2->args[1] =3D arg2; + op2->args[2] =3D arg_new_constant(ctx, len_mask); + fold_and(ctx, op2); + + op2 =3D opt_insert_before(ctx, op, INDEX_op_shl, 3); + op2->args[0] =3D tmp; + op2->args[1] =3D tmp; + op2->args[2] =3D arg_new_constant(ctx, ofs); + + op2 =3D opt_insert_before(ctx, op, INDEX_op_and, 3); + op2->args[0] =3D ret; + op2->args[1] =3D arg1; + op2->args[2] =3D arg_new_constant(ctx, ~(len_mask << ofs)); + fold_and(ctx, op2); + + op->opc =3D INDEX_op_or; + op->args[1] =3D ret; + op->args[2] =3D tmp; + } + + done: return fold_masks_zos(ctx, op, z_mask, o_mask, s_mask); } =20 diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index ab7b409be6..abce307f26 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -884,9 +884,6 @@ void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, int= 32_t arg2) void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2, unsigned int ofs, unsigned int len) { - uint32_t mask; - TCGv_i32 t1; - tcg_debug_assert(ofs < 32); tcg_debug_assert(len > 0); tcg_debug_assert(len <=3D 32); @@ -894,39 +891,9 @@ void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, = TCGv_i32 arg2, =20 if (len =3D=3D 32) { tcg_gen_mov_i32(ret, arg2); - return; - } - if (TCG_TARGET_deposit_valid(TCG_TYPE_I32, ofs, len)) { - tcg_gen_op5ii_i32(INDEX_op_deposit, ret, arg1, arg2, ofs, len); - return; - } - - t1 =3D tcg_temp_ebb_new_i32(); - - if (tcg_op_supported(INDEX_op_extract2, TCG_TYPE_I32, 0)) { - if (ofs + len =3D=3D 32) { - tcg_gen_shli_i32(t1, arg1, len); - tcg_gen_extract2_i32(ret, t1, arg2, len); - goto done; - } - if (ofs =3D=3D 0) { - tcg_gen_extract2_i32(ret, arg1, arg2, len); - tcg_gen_rotli_i32(ret, ret, len); - goto done; - } - } - - mask =3D (1u << len) - 1; - if (ofs + len < 32) { - tcg_gen_andi_i32(t1, arg2, mask); - tcg_gen_shli_i32(t1, t1, ofs); } else { - tcg_gen_shli_i32(t1, arg2, ofs); + tcg_gen_op5ii_i32(INDEX_op_deposit, ret, arg1, arg2, ofs, len); } - tcg_gen_andi_i32(ret, arg1, ~(mask << ofs)); - tcg_gen_or_i32(ret, ret, t1); - done: - tcg_temp_free_i32(t1); } =20 void tcg_gen_deposit_z_i32(TCGv_i32 ret, TCGv_i32 arg, @@ -940,28 +907,10 @@ void tcg_gen_deposit_z_i32(TCGv_i32 ret, TCGv_i32 arg, if (ofs + len =3D=3D 32) { tcg_gen_shli_i32(ret, arg, ofs); } else if (ofs =3D=3D 0) { - tcg_gen_andi_i32(ret, arg, (1u << len) - 1); - } else if (TCG_TARGET_deposit_valid(TCG_TYPE_I32, ofs, len)) { + tcg_gen_extract_i32(ret, arg, 0, len); + } else { TCGv_i32 zero =3D tcg_constant_i32(0); tcg_gen_op5ii_i32(INDEX_op_deposit, ret, zero, arg, ofs, len); - } else { - /* - * To help two-operand hosts we prefer to zero-extend first, - * which allows ARG to stay live. - */ - if (TCG_TARGET_extract_valid(TCG_TYPE_I32, 0, len)) { - tcg_gen_extract_i32(ret, arg, 0, len); - tcg_gen_shli_i32(ret, ret, ofs); - return; - } - /* Otherwise prefer zero-extension over AND for code size. */ - if (TCG_TARGET_extract_valid(TCG_TYPE_I32, 0, ofs + len)) { - tcg_gen_shli_i32(ret, arg, ofs); - tcg_gen_extract_i32(ret, ret, 0, ofs + len); - return; - } - tcg_gen_andi_i32(ret, arg, (1u << len) - 1); - tcg_gen_shli_i32(ret, ret, ofs); } } =20 @@ -2523,9 +2472,6 @@ void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, i= nt64_t arg2) void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2, unsigned int ofs, unsigned int len) { - uint64_t mask; - TCGv_i64 t1; - tcg_debug_assert(ofs < 64); tcg_debug_assert(len > 0); tcg_debug_assert(len <=3D 64); @@ -2533,55 +2479,40 @@ void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg= 1, TCGv_i64 arg2, =20 if (len =3D=3D 64) { tcg_gen_mov_i64(ret, arg2); - return; - } - - if (TCG_TARGET_REG_BITS =3D=3D 64) { - if (TCG_TARGET_deposit_valid(TCG_TYPE_I64, ofs, len)) { - tcg_gen_op5ii_i64(INDEX_op_deposit, ret, arg1, arg2, ofs, len); - return; - } + } else if (TCG_TARGET_REG_BITS =3D=3D 64) { + tcg_gen_op5ii_i64(INDEX_op_deposit, ret, arg1, arg2, ofs, len); + } else if (ofs >=3D 32) { + tcg_gen_deposit_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), + TCGV_LOW(arg2), ofs - 32, len); + tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg1)); + } else if (ofs + len <=3D 32) { + tcg_gen_deposit_i32(TCGV_LOW(ret), TCGV_LOW(arg1), + TCGV_LOW(arg2), ofs, len); + tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1)); + } else if (ofs =3D=3D 0) { + tcg_gen_deposit_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), + TCGV_HIGH(arg2), 0, len - 32); + tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg2)); } else { - if (ofs >=3D 32) { - tcg_gen_deposit_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), - TCGV_LOW(arg2), ofs - 32, len); - tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg1)); - return; - } - if (ofs + len <=3D 32) { - tcg_gen_deposit_i32(TCGV_LOW(ret), TCGV_LOW(arg1), - TCGV_LOW(arg2), ofs, len); - tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1)); - return; - } - } + /* The 64-bit deposit is split across the 32-bit halves. */ + unsigned lo_len =3D 32 - ofs; + unsigned hi_len =3D len - lo_len; + TCGv_i32 tl =3D tcg_temp_ebb_new_i32(); + TCGv_i32 th =3D tcg_temp_ebb_new_i32(); =20 - t1 =3D tcg_temp_ebb_new_i64(); - - if (tcg_op_supported(INDEX_op_extract2, TCG_TYPE_I64, 0)) { - if (ofs + len =3D=3D 64) { - tcg_gen_shli_i64(t1, arg1, len); - tcg_gen_extract2_i64(ret, t1, arg2, len); - goto done; + tcg_gen_deposit_i32(tl, TCGV_LOW(arg1), TCGV_LOW(arg2), ofs, lo_le= n); + if (len <=3D 32) { + tcg_gen_shri_i32(th, TCGV_LOW(arg2), lo_len); + } else { + tcg_gen_extract2_i32(th, TCGV_LOW(arg2), TCGV_HIGH(arg2), lo_l= en); } - if (ofs =3D=3D 0) { - tcg_gen_extract2_i64(ret, arg1, arg2, len); - tcg_gen_rotli_i64(ret, ret, len); - goto done; - } - } + tcg_gen_deposit_i32(th, TCGV_HIGH(arg1), th, 0, hi_len); =20 - mask =3D (1ull << len) - 1; - if (ofs + len < 64) { - tcg_gen_andi_i64(t1, arg2, mask); - tcg_gen_shli_i64(t1, t1, ofs); - } else { - tcg_gen_shli_i64(t1, arg2, ofs); + tcg_gen_mov_i32(TCGV_LOW(ret), tl); + tcg_gen_mov_i32(TCGV_HIGH(ret), th); + tcg_temp_free_i32(tl); + tcg_temp_free_i32(th); } - tcg_gen_andi_i64(ret, arg1, ~(mask << ofs)); - tcg_gen_or_i64(ret, ret, t1); - done: - tcg_temp_free_i64(t1); } =20 void tcg_gen_deposit_z_i64(TCGv_i64 ret, TCGv_i64 arg, @@ -2596,41 +2527,35 @@ void tcg_gen_deposit_z_i64(TCGv_i64 ret, TCGv_i64 a= rg, tcg_gen_shli_i64(ret, arg, ofs); } else if (ofs =3D=3D 0) { tcg_gen_andi_i64(ret, arg, (1ull << len) - 1); - } else if (TCG_TARGET_REG_BITS =3D=3D 64 && - TCG_TARGET_deposit_valid(TCG_TYPE_I64, ofs, len)) { + } else if (TCG_TARGET_REG_BITS =3D=3D 64) { TCGv_i64 zero =3D tcg_constant_i64(0); tcg_gen_op5ii_i64(INDEX_op_deposit, ret, zero, arg, ofs, len); + } else if (ofs >=3D 32) { + tcg_gen_deposit_z_i32(TCGV_HIGH(ret), TCGV_LOW(arg), ofs - 32, len= ); + tcg_gen_movi_i32(TCGV_LOW(ret), 0); + } else if (ofs + len <=3D 32) { + tcg_gen_deposit_z_i32(TCGV_LOW(ret), TCGV_LOW(arg), ofs, len); + tcg_gen_movi_i32(TCGV_HIGH(ret), 0); + } else if (ofs =3D=3D 0) { + tcg_gen_deposit_z_i32(TCGV_HIGH(ret), TCGV_HIGH(arg), 0, len - 32); + tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg)); } else { - if (TCG_TARGET_REG_BITS =3D=3D 32) { - if (ofs >=3D 32) { - tcg_gen_deposit_z_i32(TCGV_HIGH(ret), TCGV_LOW(arg), - ofs - 32, len); - tcg_gen_movi_i32(TCGV_LOW(ret), 0); - return; - } - if (ofs + len <=3D 32) { - tcg_gen_deposit_z_i32(TCGV_LOW(ret), TCGV_LOW(arg), ofs, l= en); - tcg_gen_movi_i32(TCGV_HIGH(ret), 0); - return; - } + /* The 64-bit deposit is split across the 32-bit halves. */ + unsigned lo_len =3D 32 - ofs; + unsigned hi_len =3D len - lo_len; + TCGv_i32 tl =3D tcg_temp_ebb_new_i32(); + TCGv_i32 th =3D TCGV_HIGH(ret); + + tcg_gen_shli_i32(tl, TCGV_LOW(arg), ofs); + if (len <=3D 32) { + tcg_gen_extract_i32(th, TCGV_LOW(arg), lo_len, hi_len); + } else { + tcg_gen_extract2_i32(th, TCGV_LOW(arg), TCGV_HIGH(arg), lo_len= ); + tcg_gen_extract_i32(th, th, 0, hi_len); } - /* - * To help two-operand hosts we prefer to zero-extend first, - * which allows ARG to stay live. - */ - if (TCG_TARGET_extract_valid(TCG_TYPE_I64, 0, len)) { - tcg_gen_extract_i64(ret, arg, 0, len); - tcg_gen_shli_i64(ret, ret, ofs); - return; - } - /* Otherwise prefer zero-extension over AND for code size. */ - if (TCG_TARGET_extract_valid(TCG_TYPE_I64, 0, ofs + len)) { - tcg_gen_shli_i64(ret, arg, ofs); - tcg_gen_extract_i64(ret, ret, 0, ofs + len); - return; - } - tcg_gen_andi_i64(ret, arg, (1ull << len) - 1); - tcg_gen_shli_i64(ret, ret, ofs); + + tcg_gen_mov_i32(TCGV_LOW(ret), tl); + tcg_temp_free_i32(tl); } } =20 --=20 2.43.0 From nobody Fri Nov 14 23:29:46 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1759077238; cv=none; d=zohomail.com; s=zohoarc; b=S+qQ9oXf5hcf3Ofn2NQTHf6HTv6DaFJrzmbhsUrn1O7HueVS6KpeoVcP9YEbfki4f5IbWq2fjnmmy8Wfn2rA/OUecw7A+26/OHeAy3vz0LXKi5gbdYwnKSzy0VOFGkD48v+pJYA6crzE2D7e3mBKbDpQtS9c7xubqt3YbJI5uFQ= ARC-Message-Signature: i=1; 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([71.212.157.132]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-27ed6996963sm107236335ad.104.2025.09.28.09.31.58 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Sep 2025 09:31:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1759077119; x=1759681919; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Tcjg7Rm+FO5sfmaU4y9Lv2rGxIIqFJaHxhAj+GUNfSg=; b=qAKNXKeZko/MuQfed4KI4yScIjo75+CLhNu+zB7+nAgWwFe6mTvZVK1u8sGKFmzbA6 xu9knfQJhIJxRaEa5e/P6XbWzRWOcVEO8G2/46GEtxbw58004r3dRPVL7xnOf3uFpObx hP5hN8aMe4d85gxitjWgGeZnCjKGbP/uQg7indVWeVO7CZLZ9Tu3eSOtrJQWbX3AUR7/ x0M31NOw1uacHACrEGNUvF4loq38uSD560wS+1msw38lTIiCtpCjJh980OB35cRfwv7j vgOxzZOasjodyUkiH6Oysi00+3HNXnXAuivnEuYpb6QjJsXCYh2cl+qMwgRDgIojymS/ eo5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1759077119; x=1759681919; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Tcjg7Rm+FO5sfmaU4y9Lv2rGxIIqFJaHxhAj+GUNfSg=; b=A9uA5gdkNKQ9dQYkD/YgDKsevs25wccXB5NXIT4zQhlUWXKT5ZVEfQkArr0KSuZts5 MHOuYhF7tixuegcFs+J2gH8bBcjPwVDaEolau3nRjo+U0736YsqG++d66u20rV3MKwRX EIShS+FhOse6kpHpu3VsDrDFdcn4ZNKIJ1JxYQoL6Zzy2qeqQbTegqLBLO2CMrKuFzHI jwGhzQ6xqZR+QJcfUOr9xcOm3V0gTSm047161ANEj/9qeg0WSIgHuC6VdwAner/wNaro LIeSEWMX/Sx8EKaepb1tYEoRDfqBKwqS9vZO4ygHJsDEXgYvpQeFfKgXzuy6DE+dCMGU w1fQ== X-Gm-Message-State: AOJu0Yw0ktEJ/W2AYw+7RSMO7EA0Dj9jjxTPbvHe11ymQaH6e8+Tagee cGOPiCxQhJwUK84gX1/tEL1q6iVav+fC6YNDaytmtYcKSgDc7rJ8dby8UMjps9rkIcghhEY7d02 KE+d63fg= X-Gm-Gg: ASbGncuaL4UNDY+2pHQZBK2xUw81O9VMZse2vIytUCCkWOkO/QgG0lb/s87O7euc6eb 8X97d2sS5dAud/ExClh/SJyeDmIS4hOYdF5Cu90LdKNFCg9SJrQdko97lVu7ngEYK9zgewiSgmM m4hDdD8QKyZa3MhNtODsdZ4+Y195FlQ+26tBVLVIRyhpldtukEnyIRdzBh62vyxQh2VTt140Y92 EyOZOEusutW1LuABu77b3pqodSpyEjZHnUtf1jdqqiiewRKp6sb6QgQrV0QTPErXWikvC3bBHo3 XDdbr1S+PejMIX8X0+wQLWQk/Wp1oTmzStmuK6VTaGgXEKV5/G38McL1kTJA2gAw/jJ3SmI8VP7 gdyiYqFiUNSNhdr6AkT3OrBTmq3JV X-Google-Smtp-Source: AGHT+IGp6ercjt3fh1llC3cKIp5vfhOGTJdoLAHklItxZpyKW5P9dv5AFfBPbIQO2aJzox1u69An9Q== X-Received: by 2002:a17:902:d4cd:b0:24c:7bc6:7ac7 with SMTP id d9443c01a7336-27ed49decddmr174525795ad.18.1759077118811; Sun, 28 Sep 2025 09:31:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 3/5] tcg/optimize: Lower unsupported extract2 during optimize Date: Sun, 28 Sep 2025 09:31:53 -0700 Message-ID: <20250928163155.1472914-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250928163155.1472914-1-richard.henderson@linaro.org> References: <20250928163155.1472914-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1759077239826116600 Content-Type: text/plain; charset="utf-8" The expansions that we chose in tcg-op.c may be less than optimial. Delay lowering until optimize, so that we have propagated constants and have computed known zero/one masks. Signed-off-by: Richard Henderson Reviewed-by: Manos Pitsidianakis --- tcg/optimize.c | 63 ++++++++++++++++++++++++++++++++++++++++++++++---- tcg/tcg-op.c | 9 ++------ 2 files changed, 60 insertions(+), 12 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index 5df57049c2..47fbcd73e3 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -2161,21 +2161,74 @@ static bool fold_extract2(OptContext *ctx, TCGOp *o= p) uint64_t z2 =3D t2->z_mask; uint64_t o1 =3D t1->o_mask; uint64_t o2 =3D t2->o_mask; + uint64_t zr, or; int shr =3D op->args[3]; + int shl; =20 if (ctx->type =3D=3D TCG_TYPE_I32) { z1 =3D (uint32_t)z1 >> shr; o1 =3D (uint32_t)o1 >> shr; - z2 =3D (uint64_t)((int32_t)z2 << (32 - shr)); - o2 =3D (uint64_t)((int32_t)o2 << (32 - shr)); + shl =3D 32 - shr; + z2 =3D (uint64_t)((int32_t)z2 << shl); + o2 =3D (uint64_t)((int32_t)o2 << shl); } else { z1 >>=3D shr; o1 >>=3D shr; - z2 <<=3D 64 - shr; - o2 <<=3D 64 - shr; + shl =3D 64 - shr; + z2 <<=3D shl; + o2 <<=3D shl; + } + zr =3D z1 | z2; + or =3D o1 | o2; + + if (zr =3D=3D or) { + return tcg_opt_gen_movi(ctx, op, op->args[0], zr); } =20 - return fold_masks_zo(ctx, op, z1 | z2, o1 | o2); + if (z2 =3D=3D 0) { + /* High part zeros folds to simple right shift. */ + op->opc =3D INDEX_op_shr; + op->args[2] =3D arg_new_constant(ctx, shr); + } else if (z1 =3D=3D 0) { + /* Low part zeros folds to simple left shift. */ + op->opc =3D INDEX_op_shl; + op->args[1] =3D op->args[2]; + op->args[2] =3D arg_new_constant(ctx, shl); + } else if (!tcg_op_supported(INDEX_op_extract2, ctx->type, 0)) { + TCGArg tmp =3D arg_new_temp(ctx); + TCGOp *op2 =3D opt_insert_before(ctx, op, INDEX_op_shr, 3); + + op2->args[0] =3D tmp; + op2->args[1] =3D op->args[1]; + op2->args[2] =3D arg_new_constant(ctx, shr); + + if (TCG_TARGET_deposit_valid(ctx->type, shl, shr)) { + /* + * Deposit has more arguments than extract2, + * so we need to create a new TCGOp. + */ + op2 =3D opt_insert_before(ctx, op, INDEX_op_deposit, 5); + op2->args[0] =3D op->args[0]; + op2->args[1] =3D tmp; + op2->args[2] =3D op->args[2]; + op2->args[3] =3D shl; + op2->args[4] =3D shr; + + tcg_op_remove(ctx->tcg, op); + op =3D op2; + } else { + op2 =3D opt_insert_before(ctx, op, INDEX_op_shl, 3); + op2->args[0] =3D op->args[0]; + op2->args[1] =3D op->args[2]; + op2->args[2] =3D arg_new_constant(ctx, shl); + + op->opc =3D INDEX_op_or; + op->args[1] =3D op->args[0]; + op->args[2] =3D tmp; + } + } + + return fold_masks_zo(ctx, op, zr, or); } =20 static bool fold_exts(OptContext *ctx, TCGOp *op) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index abce307f26..4caf77da1e 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -1008,13 +1008,8 @@ void tcg_gen_extract2_i32(TCGv_i32 ret, TCGv_i32 al,= TCGv_i32 ah, tcg_gen_mov_i32(ret, ah); } else if (al =3D=3D ah) { tcg_gen_rotri_i32(ret, al, ofs); - } else if (tcg_op_supported(INDEX_op_extract2, TCG_TYPE_I32, 0)) { - tcg_gen_op4i_i32(INDEX_op_extract2, ret, al, ah, ofs); } else { - TCGv_i32 t0 =3D tcg_temp_ebb_new_i32(); - tcg_gen_shri_i32(t0, al, ofs); - tcg_gen_deposit_i32(ret, t0, ah, 32 - ofs, ofs); - tcg_temp_free_i32(t0); + tcg_gen_op4i_i32(INDEX_op_extract2, ret, al, ah, ofs); } } =20 @@ -2711,7 +2706,7 @@ void tcg_gen_extract2_i64(TCGv_i64 ret, TCGv_i64 al, = TCGv_i64 ah, tcg_gen_mov_i64(ret, ah); } else if (al =3D=3D ah) { tcg_gen_rotri_i64(ret, al, ofs); - } else if (tcg_op_supported(INDEX_op_extract2, TCG_TYPE_I64, 0)) { + } else if (TCG_TARGET_REG_BITS =3D=3D 64) { tcg_gen_op4i_i64(INDEX_op_extract2, ret, al, ah, ofs); } else { TCGv_i64 t0 =3D tcg_temp_ebb_new_i64(); --=20 2.43.0 From nobody Fri Nov 14 23:29:46 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1759077240; cv=none; d=zohomail.com; s=zohoarc; b=MKMHH55Ypd1hTV3G0HO9xB4vAcK70d2CFoJevNyPsW8zyWK9wQS3uhym+VhdEnAkzoi0v5IflZODiyZUTkjo7rXpTerxdlTZFi9SivicjLtbavH/aCPnxB4ktbApGdgNuWF1DeWTUsEAAaFJyz95HXa1cBBSqX39btui+PpfG5s= ARC-Message-Signature: i=1; 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([71.212.157.132]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-27ed6996963sm107236335ad.104.2025.09.28.09.31.59 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Sep 2025 09:31:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1759077119; x=1759681919; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=ldEtWW0ceL1Qi6i+lol9hJF8fiaAV8bH+OpsdGd9wvE=; b=ayoSsM3bJI6UybxLclQmGTu9pBJZaha8+Z02Y+y6NH5NE0mBFK3nELvS5x02nqcKQW C6AdW/Bhpf4sTHFGDmo5ESHns/vjvSjRubZdwUI885HlO+Xt+57HFpV8BhfXiUi5LMzI 5neSl/p79HL0Qs+x+RBhXqPHNfQ9M7m4oWmGHmA+hn4W4Z3yFjRs9c+2unQEgZw1jC9F Y+hnqCBBl5IRAfWfkXqBimtc0YfCHP0cm4Gf4Wtx7RVsP9IDQeH1vyf/TGOQl4ibhtA9 lXggCHcnSfrjOVA9FTeQvATQShktcioezOc6vLZJIG9aEiROV/KSwos7EFC7l+RuWqL0 7rug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1759077119; x=1759681919; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ldEtWW0ceL1Qi6i+lol9hJF8fiaAV8bH+OpsdGd9wvE=; b=a+bVyH3oLAvJ7Ceh0f+d7xORYwG8grTO5CjgmC63qTurOO5t0GaSpz7X2R7X0LDusZ emrlPBELFBHBF0DnnNWEarAGK/C1ES/MqqtABPXwbvIc9yLrmUec3dJLZpaOBSwcGupq 9v9pJnfh92eO50m/dDyYEjRd9Dv9+4UjPRz/E2TeOEPGfepP+XxqcH17aysK0DFocHLo luf5fB9fE40DrTMqVDDVqaH/BGQ3+pYBCTKtYV4r+RQNR0HLD3Qy1yIXtZ9vHf2GZSrw E3yZQ6yIx7ZWuUSop+9wJ42JJfP6juNo48cO3sfoc+Gv/cJgMm2Bpi5kwhEZJWo/Wifo raMQ== X-Gm-Message-State: AOJu0Yz5pLDk1AMKx9BQoe+Bk0TF8vM5FHu7fpXKCsc69oL1MkcrRMXu CVvADfvKGa3ofPS2BZqJ7ZJw+OBtn6MTFoEkA5NCtOPXU4v8AdmyudYYwMfRN02iMrp8SnCcw0f rST8JNWA= X-Gm-Gg: ASbGncseyABVEk6wKic3sL8XcOj8Dhqvj3s2mW/PkYCIYTjHGfvwKvETeMYQA8umUWO pVXnWGsZHfCaDg+UD8JCMXltoPx6vsWVbYC2eFr3DwAWz7ZY63dtx0EcHtLV5b7cRiNLhVJ7Qc8 IVpc/eDF1Y7yukRuvl2btEMHQNsPz+S3YJA1fiC0EoFa1cvtSe1rFmfFfcSQAnRp1lWH4oCSl84 ttM3qYLZglBipOBXVstkLbGv3nCE0GtuIYNe6Zwel6b7/w7lvRqAnSCf/q0eSoyXUiD0vGMjYsn Ieu1lD88xkFofzp54Wh8ZGv5FHhHo0bqtk80Os2l+UaPMky0zjcqsE+444wBYUPqRYPsLIa0eby deNEgolVf2KWKLM1hTDxgP7YrmIVn X-Google-Smtp-Source: AGHT+IGVKLXBh0JC0FhujuuL/hCUET6N/d+yG2dD+NOssEVUHJWI5n8nF02iHS8IOJS/MNw3kGLU0w== X-Received: by 2002:a17:903:1a2b:b0:24c:ea17:e322 with SMTP id d9443c01a7336-27ed49df28dmr162570745ad.3.1759077119503; Sun, 28 Sep 2025 09:31:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 4/5] tcg: Expand missing rotri with extract2 Date: Sun, 28 Sep 2025 09:31:54 -0700 Message-ID: <20250928163155.1472914-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250928163155.1472914-1-richard.henderson@linaro.org> References: <20250928163155.1472914-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1759077241440116600 Content-Type: text/plain; charset="utf-8" Use extract2 to implement rotri. To make this easier, redefine rotli in terms of rotri, rather than the reverse. Signed-off-by: Richard Henderson --- tcg/tcg-op.c | 70 ++++++++++++++++++++++++++++++---------------------- 1 file changed, 41 insertions(+), 29 deletions(-) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 4caf77da1e..3e10a3ad16 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -834,23 +834,12 @@ void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TC= Gv_i32 arg2) void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) { tcg_debug_assert(arg2 >=3D 0 && arg2 < 32); - /* some cases can be optimized here */ if (arg2 =3D=3D 0) { tcg_gen_mov_i32(ret, arg1); } else if (tcg_op_supported(INDEX_op_rotl, TCG_TYPE_I32, 0)) { - TCGv_i32 t0 =3D tcg_constant_i32(arg2); - tcg_gen_op3_i32(INDEX_op_rotl, ret, arg1, t0); - } else if (tcg_op_supported(INDEX_op_rotr, TCG_TYPE_I32, 0)) { - TCGv_i32 t0 =3D tcg_constant_i32(32 - arg2); - tcg_gen_op3_i32(INDEX_op_rotr, ret, arg1, t0); + tcg_gen_op3_i32(INDEX_op_rotl, ret, arg1, tcg_constant_i32(arg2)); } else { - TCGv_i32 t0 =3D tcg_temp_ebb_new_i32(); - TCGv_i32 t1 =3D tcg_temp_ebb_new_i32(); - tcg_gen_shli_i32(t0, arg1, arg2); - tcg_gen_shri_i32(t1, arg1, 32 - arg2); - tcg_gen_or_i32(ret, t0, t1); - tcg_temp_free_i32(t0); - tcg_temp_free_i32(t1); + tcg_gen_rotri_i32(ret, arg1, -arg2 & 31); } } =20 @@ -878,7 +867,16 @@ void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCG= v_i32 arg2) void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) { tcg_debug_assert(arg2 >=3D 0 && arg2 < 32); - tcg_gen_rotli_i32(ret, arg1, -arg2 & 31); + if (arg2 =3D=3D 0) { + tcg_gen_mov_i32(ret, arg1); + } else if (tcg_op_supported(INDEX_op_rotr, TCG_TYPE_I64, 0)) { + tcg_gen_op3_i32(INDEX_op_rotr, ret, arg1, tcg_constant_i32(arg2)); + } else if (tcg_op_supported(INDEX_op_rotl, TCG_TYPE_I64, 0)) { + tcg_gen_op3_i32(INDEX_op_rotl, ret, arg1, tcg_constant_i32(32 - ar= g2)); + } else { + /* Do not recurse with the rotri simplification. */ + tcg_gen_op4i_i32(INDEX_op_extract2, ret, arg1, arg1, arg2); + } } =20 void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2, @@ -2417,23 +2415,12 @@ void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, = TCGv_i64 arg2) void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) { tcg_debug_assert(arg2 >=3D 0 && arg2 < 64); - /* some cases can be optimized here */ if (arg2 =3D=3D 0) { tcg_gen_mov_i64(ret, arg1); - } else if (tcg_op_supported(INDEX_op_rotl, TCG_TYPE_I64, 0)) { - TCGv_i64 t0 =3D tcg_constant_i64(arg2); - tcg_gen_op3_i64(INDEX_op_rotl, ret, arg1, t0); - } else if (tcg_op_supported(INDEX_op_rotr, TCG_TYPE_I64, 0)) { - TCGv_i64 t0 =3D tcg_constant_i64(64 - arg2); - tcg_gen_op3_i64(INDEX_op_rotr, ret, arg1, t0); + } else if (tcg_op_supported(INDEX_op_rotl, TCG_TYPE_I32, 0)) { + tcg_gen_op3_i64(INDEX_op_rotl, ret, arg1, tcg_constant_i64(arg2)); } else { - TCGv_i64 t0 =3D tcg_temp_ebb_new_i64(); - TCGv_i64 t1 =3D tcg_temp_ebb_new_i64(); - tcg_gen_shli_i64(t0, arg1, arg2); - tcg_gen_shri_i64(t1, arg1, 64 - arg2); - tcg_gen_or_i64(ret, t0, t1); - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); + tcg_gen_rotri_i64(ret, arg1, -arg2 & 63); } } =20 @@ -2461,7 +2448,32 @@ void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, T= CGv_i64 arg2) void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) { tcg_debug_assert(arg2 >=3D 0 && arg2 < 64); - tcg_gen_rotli_i64(ret, arg1, -arg2 & 63); + if (arg2 =3D=3D 0) { + tcg_gen_mov_i64(ret, arg1); + } else if (TCG_TARGET_REG_BITS =3D=3D 32) { + TCGv_i32 rl =3D tcg_temp_ebb_new_i32(); + TCGv_i32 rh =3D TCGV_HIGH(ret); + TCGv_i32 t0, t1; + + if (arg2 & 32) { + t0 =3D TCGV_HIGH(arg1); + t1 =3D TCGV_LOW(arg1); + } else { + t0 =3D TCGV_LOW(arg1); + t1 =3D TCGV_HIGH(arg1); + } + tcg_gen_extract2_i32(rl, t0, t1, arg2 & 31); + tcg_gen_extract2_i32(rh, t1, t0, arg2 & 31); + tcg_gen_mov_i32(TCGV_LOW(ret), rl); + tcg_temp_free_i32(rl); + } else if (tcg_op_supported(INDEX_op_rotr, TCG_TYPE_I64, 0)) { + tcg_gen_op3_i64(INDEX_op_rotr, ret, arg1, tcg_constant_i64(arg2)); + } else if (tcg_op_supported(INDEX_op_rotl, TCG_TYPE_I64, 0)) { + tcg_gen_op3_i64(INDEX_op_rotl, ret, arg1, tcg_constant_i64(64 - ar= g2)); + } else { + /* Do not recurse with the rotri simplification. */ + tcg_gen_op4i_i64(INDEX_op_extract2, ret, arg1, arg1, arg2); + } } =20 void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2, --=20 2.43.0 From nobody Fri Nov 14 23:29:46 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([71.212.157.132]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-27ed6996963sm107236335ad.104.2025.09.28.09.31.59 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Sep 2025 09:31:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1759077120; x=1759681920; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=cAY2ArchBWaMGfIbT8UhS815gAC6ZiBScneQAdyyaew=; b=zWXQ8anG0mjAYgRN/IhcQWwIFQ0dsr9A3KhXlPI3jVZ1lsHf4cEb2JMzUmntmS7mUX 0AWSTFmS4fhL9Ox90o4PDmjG7wimn9V2GJ4kzA5CP2nSTLC7kut80isTkn758uwx1DWA EmWEM1ZjgZnPwXsLYhgyMob+i7SggSyQwpjYu2MGNfRqmIuk9AnBPicNMvgKJtDlh8fe k/sq8sUryzB7iVKEB5r3ZZMTbtWSsqWhjRyqO1MHP541hehMiQEKXxv5i40B6eL5wh8V z9VRgWK5h7GgI6KpvRa0q0h+efF1cN9BsofYoILfj10+YO/YgnUf+m0ilYkhio26xyJZ CslA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1759077120; x=1759681920; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cAY2ArchBWaMGfIbT8UhS815gAC6ZiBScneQAdyyaew=; b=HVIuTQokGgl4Rno0/vqD/n9EmYzzNEH/75IFCK2RxO/YG2eQw7+w7LHbpXFhdh2vL/ QWhE8X2IfymaKH6dCGJn96PPlCsJ/c8VQwpDvmKPpUrY87/xkbZakJU3ZJE7OReg5fCx KuUOfOF6azCnyYMMHUBwv5mW8KFsJWZHj60/D2Ow8rb3Q4P4wcQ06SUTTY7TdA6uKtfn XCrjwph3OAiPXtMlKki9GxlxJIKyj7qRjjC3juRaAUMo3K2kkUSCKYZ4tj/f1TjbWjUk pZ6+8j4XCt+lqekIBBkYmrFbOwt97ByHycvuZELz6Zk6I1WAETTk0bMoqJ/zXSuIz1Ux mFOQ== X-Gm-Message-State: AOJu0Yx3fCE3jkwyKFOIaRF9RkxABO5li5pLHw9zd/lURcU1WKWLMGIm seNstO37ZJvf1qw5xSJKavzm3lW7vvudcPQz2S0EMvt0p1R2JgzU54I0yue5fOmINdPi86AnrAc 6KQFTbV8= X-Gm-Gg: ASbGncvfhnmqPjWTle9GeNmLjsXK/cobm1iLR+31Cevgl55j2XH+fdYb3Vv09OFiugo 3Hlk5sz6oYC3d1KuaMC/vwUsLrewvuaAMmVHkOLnYYjJ1RwU86Hb/h5mvrLf+SB/+8P1sFQ8zxq tC0/0R2rLSnXzKWsb/yxnGg4pBtrud1TFf4pMXIm5JwYdlzqOBUEG3vyG8LAXsZJzjMk2/v56bk tuWvX7mDruGx37UBWSosu6dxTBKdgIWxtCMIjIhuknlnMfuGvSflqi/ISXWnLaMcy10Ns77itXm hZ1TGV8qzdJWa6Nh9ullX/8N3TYOteEwFlvqsJiOD5deoucfC4qFy0x9WA+ULX7v34HIFuZklcG 4UTj7rK+/TdCVeaFvo7cZIuUYy+DM X-Google-Smtp-Source: AGHT+IEE5mozXDqAViE7IhpBsaVkoYCovfCCSV79N+qbASh5UTEOsdUIivhEsArUFLsF04U+NIHLZQ== X-Received: by 2002:a17:903:2c0d:b0:250:5ff5:3f4b with SMTP id d9443c01a7336-27ed4a3e0afmr171125435ad.15.1759077120099; Sun, 28 Sep 2025 09:32:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 5/5] tcg: Expand extract2_i64 with extract2_i32 on 32-bit host Date: Sun, 28 Sep 2025 09:31:55 -0700 Message-ID: <20250928163155.1472914-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250928163155.1472914-1-richard.henderson@linaro.org> References: <20250928163155.1472914-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1759077320390116600 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tcg-op.c | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 3e10a3ad16..6c697905e2 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -2721,10 +2721,23 @@ void tcg_gen_extract2_i64(TCGv_i64 ret, TCGv_i64 al= , TCGv_i64 ah, } else if (TCG_TARGET_REG_BITS =3D=3D 64) { tcg_gen_op4i_i64(INDEX_op_extract2, ret, al, ah, ofs); } else { - TCGv_i64 t0 =3D tcg_temp_ebb_new_i64(); - tcg_gen_shri_i64(t0, al, ofs); - tcg_gen_deposit_i64(ret, t0, ah, 64 - ofs, ofs); - tcg_temp_free_i64(t0); + TCGv_i32 rl =3D tcg_temp_ebb_new_i32(); + TCGv_i32 rh =3D TCGV_HIGH(ret); + TCGv_i32 t0, t1, t2; + + if (ofs & 32) { + t0 =3D TCGV_HIGH(al); + t1 =3D TCGV_LOW(ah); + t2 =3D TCGV_HIGH(ah); + } else { + t0 =3D TCGV_LOW(al); + t1 =3D TCGV_HIGH(al); + t2 =3D TCGV_LOW(ah); + } + tcg_gen_extract2_i32(rl, t0, t1, ofs & 31); + tcg_gen_extract2_i32(rh, t1, t2, ofs & 31); + tcg_gen_mov_i32(TCGV_LOW(ret), rl); + tcg_temp_free_i32(rl); } } =20 --=20 2.43.0