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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-410f2007372sm6338315f8f.16.2025.09.26.07.09.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Sep 2025 07:09:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758895758; x=1759500558; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=yZEFx/GNhVkQj1G0HF9zfJ7+hUERk6GLhLOLXCxKnsc=; b=WJHWg2PSElYFfo83bWTPjFEZQfEzFwvJrXUs+2QmzY+NFCgJFHvGv0MBBLSXk07Mdv gCM2uihJoNDTGrumlM6rW5yQ+JofxjaEOqD1yxuaEnTqNjwOM93Ag5pn3fdP6qKl26vR h33LaJiweQo423XLjks/uMO1UNT8G/Frvg0hnTR5oKxVyMcoDRFCALuWh2sFl8ntYY4e aYkKKy8ApsIVsiIXqViQZ31IEfbQANhjOkN96GW29ksA9SmZ3EzkiwrWmQvZRTKHVPVC eZufcRE80tU0Zh2KIoqX8t0hGmsriv96pt406TtXXb+uoYdHhXI/EhDTYFz9O/etswZ1 q7Ng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758895758; x=1759500558; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yZEFx/GNhVkQj1G0HF9zfJ7+hUERk6GLhLOLXCxKnsc=; b=pmBpjPG7/MKt0zJ+koCHtmjzxSRd+DlAulSNxb+JwGD3EZOWU3ipa7jJARuSjwrzIP DsxuLgDeqqYnwEPLJs0uLifkyaW1YIlvIqB+rWmp4y85YzfuWrtwubNTxGDOJ3Wo+MGD cU2s8LcUTQYmtLh0tCcCXiRXQt7r1exQVzu/qfrVOCZm5oWIrdGZuwXHb+CQh62eyxLj VO6YEqBcuuPG5IHRihT9M+5OQQMC8X66W574mpWM4+7xO7jgtoLGL4/MQcTgP58X4XFJ MfXZM0OtgdzseGLVnjeIEu+9W5x6mf1KOzaSBTidhlGCfPgbj+jTgJYt23J1WDPh0UzB X+JA== X-Gm-Message-State: AOJu0YzNzzqon/itgxp9BoLl8/7qCq9Uk2eeVTpgmce2Va0bem2AvN4U b0rtaqf7adEM7mPfBAY1seWRnogdJBVjrSy8tG8OHqXo9pPfC1ZExJDOmsBf4tk2IF4pJyD7Z1y O3c6Y X-Gm-Gg: ASbGnctccdjy/AndbzhbT/SsJTi0EddMB656SlBO83FICbS50v8axW59VigsJmaOxiI 1oMv65R0E8PTj81Xfs++8S3i+BKoXW4uLJsjpf9A+sx4ywFhaIdoPzziKJvhkBUdfYbYinauYe+ mhoYUTkP3joo4kEYMX0OjYJMsuYfldPbx9rqeRK172oWnFTDMg9Zcw0fNx9RkL4ViU0QTI/l/vU mWp1DpODXcHg3O8Fy30o/HEYff3ZRGMNo9HHcbE/MkA7ra5ey5etDx/9DHfwAxQaoqJXe+4RaiJ 8rqBhLJgyUv+DSaeRTL9xs1+ijwvcJ5fPCa1bwy9bIlvsx3m6Uvfai4YnF8k6W65OyW06EOrqeA aESPr4Rk9z2/L69UygwLiI0uJYj2JTthFT/DXg04= X-Google-Smtp-Source: AGHT+IG6mx6ouGnhLaaeYs0SfVVodUX6c9+5lmbuhWVgngsjOYxAEhrZuedhHa4ZWU6nHYK9sZWJUw== X-Received: by 2002:a05:6000:24c6:b0:3f4:ad3f:7c35 with SMTP id ffacd0b85a97d-40f69cd780fmr5764685f8f.27.1758895758130; Fri, 26 Sep 2025 07:09:18 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 31/44] target/arm: Move writeback of CP_ANY fields Date: Fri, 26 Sep 2025 15:08:31 +0100 Message-ID: <20250926140844.1493020-32-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250926140844.1493020-1-peter.maydell@linaro.org> References: <20250926140844.1493020-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758896848931116600 From: Richard Henderson Move the writeback of cp, crm, opc1, opc2 to define_one_arm_cp_reg, which means we don't have to pass all those parameters down to subroutines. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- target/arm/helper.c | 52 ++++++++++++++++++++++----------------------- 1 file changed, 26 insertions(+), 26 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 274b7b5808e..4063c8a0b6f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7390,7 +7390,6 @@ static ARMCPRegInfo *alloc_cpreg(const ARMCPRegInfo *= in, const char *suffix) */ static void add_cpreg_to_hashtable(ARMCPU *cpu, ARMCPRegInfo *r, CPState state, CPSecureState secstate, - int cp, int crm, int opc1, int opc2, uint32_t key) { CPUARMState *env =3D &cpu->env; @@ -7457,12 +7456,8 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, ARMC= PRegInfo *r, =20 /* * Update fields to match the instantiation, overwiting wildcards - * such as CP_ANY, ARM_CP_STATE_BOTH, or ARM_CP_SECSTATE_BOTH. + * such as ARM_CP_STATE_BOTH or ARM_CP_SECSTATE_BOTH. */ - r->cp =3D cp; - r->crm =3D crm; - r->opc1 =3D opc1; - r->opc2 =3D opc2; r->state =3D state; r->secure =3D secstate; =20 @@ -7478,8 +7473,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, ARMCP= RegInfo *r, g_hash_table_insert(cpu->cp_regs, (gpointer)(uintptr_t)key, r); } =20 -static void add_cpreg_to_hashtable_aa32(ARMCPU *cpu, ARMCPRegInfo *r, - int cp, int crm, int opc1, int opc= 2) +static void add_cpreg_to_hashtable_aa32(ARMCPU *cpu, ARMCPRegInfo *r) { /* * Under AArch32 CP registers can be common @@ -7487,7 +7481,8 @@ static void add_cpreg_to_hashtable_aa32(ARMCPU *cpu, = ARMCPRegInfo *r, */ ARMCPRegInfo *r_s; bool is64 =3D r->type & ARM_CP_64BIT; - uint32_t key =3D ENCODE_CP_REG(cp, is64, 0, r->crn, crm, opc1, opc2); + uint32_t key =3D ENCODE_CP_REG(r->cp, is64, 0, r->crn, + r->crm, r->opc1, r->opc2); =20 assert(!(r->type & ARM_CP_ADD_TLBI_NXS)); /* aa64 only */ =20 @@ -7496,27 +7491,26 @@ static void add_cpreg_to_hashtable_aa32(ARMCPU *cpu= , ARMCPRegInfo *r, key |=3D CP_REG_AA32_NS_MASK; /* fall through */ case ARM_CP_SECSTATE_S: - add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32, r->secure, - cp, crm, opc1, opc2, key); + add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32, r->secure, key); break; case ARM_CP_SECSTATE_BOTH: r_s =3D alloc_cpreg(r, "_S"); - add_cpreg_to_hashtable(cpu, r_s, ARM_CP_STATE_AA32, ARM_CP_SECSTAT= E_S, - cp, crm, opc1, opc2, key); + add_cpreg_to_hashtable(cpu, r_s, ARM_CP_STATE_AA32, + ARM_CP_SECSTATE_S, key); =20 key |=3D CP_REG_AA32_NS_MASK; - add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32, ARM_CP_SECSTATE_= NS, - cp, crm, opc1, opc2, key); + add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32, + ARM_CP_SECSTATE_NS, key); break; default: g_assert_not_reached(); } } =20 -static void add_cpreg_to_hashtable_aa64(ARMCPU *cpu, ARMCPRegInfo *r, - int crm, int opc1, int opc2) +static void add_cpreg_to_hashtable_aa64(ARMCPU *cpu, ARMCPRegInfo *r) { - uint32_t key =3D ENCODE_AA64_CP_REG(r->opc0, opc1, r->crn, crm, opc2); + uint32_t key =3D ENCODE_AA64_CP_REG(r->opc0, r->opc1, + r->crn, r->crm, r->opc2); =20 if ((r->type & ARM_CP_ADD_TLBI_NXS) && cpu_isar_feature(aa64_xs, cpu)) { @@ -7542,12 +7536,11 @@ static void add_cpreg_to_hashtable_aa64(ARMCPU *cpu= , ARMCPRegInfo *r, } =20 add_cpreg_to_hashtable(cpu, nxs_ri, ARM_CP_STATE_AA64, - ARM_CP_SECSTATE_NS, 0, crm, opc1, opc2, - nxs_key); + ARM_CP_SECSTATE_NS, nxs_key); } =20 - add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA64, ARM_CP_SECSTATE_NS, - 0, crm, opc1, opc2, key); + add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA64, + ARM_CP_SECSTATE_NS, key); } =20 void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *r) @@ -7767,17 +7760,24 @@ void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCP= RegInfo *r) r2->type |=3D ARM_CP_ALIAS | ARM_CP_NO_GDB; } =20 + /* Overwrite CP_ANY with the instantiation. */ + r2->crm =3D crm; + r2->opc1 =3D opc1; + r2->opc2 =3D opc2; + switch (r->state) { case ARM_CP_STATE_AA32: - add_cpreg_to_hashtable_aa32(cpu, r2, cp, crm, opc1, op= c2); + add_cpreg_to_hashtable_aa32(cpu, r2); break; case ARM_CP_STATE_AA64: - add_cpreg_to_hashtable_aa64(cpu, r2, crm, opc1, opc2); + add_cpreg_to_hashtable_aa64(cpu, r2); break; case ARM_CP_STATE_BOTH: r3 =3D alloc_cpreg(r2, NULL); - add_cpreg_to_hashtable_aa32(cpu, r2, cp, crm, opc1, op= c2); - add_cpreg_to_hashtable_aa64(cpu, r3, crm, opc1, opc2); + r2->cp =3D cp; + add_cpreg_to_hashtable_aa32(cpu, r2); + r3->cp =3D 0; + add_cpreg_to_hashtable_aa64(cpu, r3); break; default: g_assert_not_reached(); --=20 2.43.0