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Reviewed-by: Manos Pitsidianakis Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- target/arm/cpregs.h | 10 ++++++---- target/arm/gdbstub.c | 7 +++++-- target/arm/helper.c | 18 +++++++++++++----- 3 files changed, 24 insertions(+), 11 deletions(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 6fb1994afa0..74bae7309a3 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -22,6 +22,7 @@ #define TARGET_ARM_CPREGS_H =20 #include "hw/registerfields.h" +#include "exec/memop.h" #include "target/arm/kvm-consts.h" #include "cpu.h" =20 @@ -1078,12 +1079,13 @@ void raw_write(CPUARMState *env, const ARMCPRegInfo= *ri, uint64_t value); void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *ri); =20 /* - * Return true if this reginfo struct's field in the cpu state struct - * is 64 bits wide. + * Return MO_32 if the field in CPUARMState is uint32_t or + * MO_64 if the field in CPUARMState is uint64_t. */ -static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri) +static inline MemOp cpreg_field_type(const ARMCPRegInfo *ri) { - return (ri->state =3D=3D ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BI= T); + return (ri->state =3D=3D ARM_CP_STATE_AA64 || (ri->type & ARM_CP_64BIT) + ? MO_64 : MO_32); } =20 static inline bool cp_access_ok(int current_el, diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index 2d331fff445..4e2ac49b6a9 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -247,10 +247,13 @@ static int arm_gdb_get_sysreg(CPUState *cs, GByteArra= y *buf, int reg) key =3D cpu->dyn_sysreg_feature.data.cpregs.keys[reg]; ri =3D get_arm_cp_reginfo(cpu->cp_regs, key); if (ri) { - if (cpreg_field_is_64bit(ri)) { + switch (cpreg_field_type(ri)) { + case MO_64: return gdb_get_reg64(buf, (uint64_t)read_raw_cp_reg(env, ri)); - } else { + case MO_32: return gdb_get_reg32(buf, (uint32_t)read_raw_cp_reg(env, ri)); + default: + g_assert_not_reached(); } } return 0; diff --git a/target/arm/helper.c b/target/arm/helper.c index fe298670f12..26941ecd4f8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -63,20 +63,28 @@ int compare_u64(const void *a, const void *b) uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri) { assert(ri->fieldoffset); - if (cpreg_field_is_64bit(ri)) { + switch (cpreg_field_type(ri)) { + case MO_64: return CPREG_FIELD64(env, ri); - } else { + case MO_32: return CPREG_FIELD32(env, ri); + default: + g_assert_not_reached(); } } =20 void raw_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { assert(ri->fieldoffset); - if (cpreg_field_is_64bit(ri)) { + switch (cpreg_field_type(ri)) { + case MO_64: CPREG_FIELD64(env, ri) =3D value; - } else { + break; + case MO_32: CPREG_FIELD32(env, ri) =3D value; + break; + default: + g_assert_not_reached(); } } =20 @@ -2754,7 +2762,7 @@ static void vmsa_ttbr_write(CPUARMState *env, const A= RMCPRegInfo *ri, uint64_t value) { /* If the ASID changes (with a 64-bit write), we must flush the TLB. = */ - if (cpreg_field_is_64bit(ri) && + if (cpreg_field_type(ri) =3D=3D MO_64 && extract64(raw_read(env, ri) ^ value, 48, 16) !=3D 0) { ARMCPU *cpu =3D env_archcpu(env); tlb_flush(CPU(cpu)); --=20 2.43.0