From nobody Sun Sep 28 15:26:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758897013; cv=none; d=zohomail.com; s=zohoarc; b=Y5yoUl1tCyieBjxPy+j+31nziXhlUN7YyVZhS3vrwa5KVBsrGcKeAJfHezu6/utsGTLVCRvhzOj2wzWzsOXQ3WIq7Dn40GT6ot1EgOwh5jZCh0R7yue/cbiZZMQJMpj7FMRu7BUVvfIonWlS7aUxE9UkOPcUZ3SGQT8i30fgSuc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758897013; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=O0aztZbkfa2XWgDl+0nqPzT+Opjm3fDCBodAYyqxJuM=; b=RWvsL9Fhm4B9O9ccSR5ee503Jq6q74UKHOnzYc+LfxN9eo/foQzekVddJz0kaLMCPsEP65dc7pXCnqog6QlkoScYe8TqLIVxDWIDQAXSD9RpfiuW2uJTINKGT4aVMH2h1lAtfVZ06ZaZBM/3HZR8A+DDMQP4nEQDXi6AhS489a4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 175889701351463.38597282803562; Fri, 26 Sep 2025 07:30:13 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v298B-00075X-0Y; Fri, 26 Sep 2025 10:09:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v2987-000759-NB for qemu-devel@nongnu.org; Fri, 26 Sep 2025 10:08:59 -0400 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1v2983-0005cm-Di for qemu-devel@nongnu.org; Fri, 26 Sep 2025 10:08:58 -0400 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-46de78b595dso11289375e9.1 for ; Fri, 26 Sep 2025 07:08:49 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-410f2007372sm6338315f8f.16.2025.09.26.07.08.46 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Sep 2025 07:08:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758895727; x=1759500527; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=O0aztZbkfa2XWgDl+0nqPzT+Opjm3fDCBodAYyqxJuM=; b=h6/cnikYDVk/HouLB0M7A31FUOr5JmwWw0HMf6LWixfcKLSHanPo9LJ7VEGOVqPJWk dNqicBlBlo07rDDlrkELzTNsfVf0Mxka2q3DAXZdzfiYYQtpg684DtL3nP/Q3XwJndHs 5T/rzkneh4B6CLKhkhz67MlydePd+4LK69nW5E1PIuvXiy+lAOKrgelVGWq2u7T5WwnP iMDZu6lLwADuOkH5AfJrXFGis6L5wDuHLvQsPIqsIov7UgoHJn2U3cHIwAMtJZgAOIxQ jsJ8y05ru/je7sLrLUTsEpt/QghYNfpDYcYUdCYZgpRzE4ZDslb+X2DLQrhPCJ9euvA4 bi6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758895727; x=1759500527; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=O0aztZbkfa2XWgDl+0nqPzT+Opjm3fDCBodAYyqxJuM=; b=N6nt484eKUWc8hrXhlF+l79MPWrfkPfva2zXJceO0SD58c1bnr/Hb8E4bp+u0+JdNh wp4HJfLBsASKyUN4OwFynJuOoCcEzSZb8VegVJIy2z7qg6XWYQBIrBB7Bitay5Mi2D22 GVofE3H67OFWR0vVXuJ7NBY2ZEqd39DQtf6R1C9U5/vMfg1kkVwVMXlpz9lYNxeJaJYm NDgpqlpVug9mgLxFG+tdMZRg/DBTo3oz9eRi5UCnMANYOZ51rMG5zZca202B7jpUwRAH ejwjwFO6gFSNDxqPEKgmIm/QD/8O9rcEfir3oZGFxghXXhZPYuHkZUKnmVVpRq2wTS3r vcBQ== X-Gm-Message-State: AOJu0YxMzhIWiOqWfIUNlrsRqfsAuqOwVcgE37xRb0cJ/PcaGNLN/deK 97br4ovIM9EjLO03w0KZcqC9HivckrlKgGKmNmCDx0k0uno5sMQbnyUyI5kJfYPI+5/7GqhfWh7 K1JHx X-Gm-Gg: ASbGncukGS8CEyrVoYAvS7QHWx/r5KKmYwbj+XA4ku7mpZheqQqAX51AkkBXzCLUpL/ M5BYc6MJmw9DyoZtrLwUpq4ZSAJXbBiKNh29KNA0p4xxUnxtbyO4n6GyiyNih7SE37VmFrFnvQY GF+vRCTwLRigSy2P9sawzgVuaSg0RtLzPvyDd0GzEVL7THipQxiJ6mTxFt1cR3YUl5Q+DpIaHFZ FDgBVS8SLEAKhpE1BGBfmrT+tQtRi+TKzsbMXB2jfL6RGu8nSzPClCvVbg9sDexPv9wC5hAI97H PCekEZLP5RAMyT4wkxJMkLShQKu/gCq3aMSvLtsHRBy41OOnSbvVbvkZ0BrXBXfNuo8hM9oKGYK o6zcUGJ701pPrBxSr60uKS1wXkcmY X-Google-Smtp-Source: AGHT+IHKSXMU5p1TR23tcydVkuuHAEnSkW6JQbS94rsxPN0KsST6Xewp0WR5dCjBXoWaDDF0mrM9Hw== X-Received: by 2002:a05:600c:1508:b0:458:c094:8ba5 with SMTP id 5b1f17b1804b1-46e329b62bcmr51689685e9.12.1758895727402; Fri, 26 Sep 2025 07:08:47 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/44] hw/usb/hcd-uhci: don't assert for SETUP to non-0 endpoint Date: Fri, 26 Sep 2025 15:08:01 +0100 Message-ID: <20250926140844.1493020-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250926140844.1493020-1-peter.maydell@linaro.org> References: <20250926140844.1493020-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758897014883116600 Content-Type: text/plain; charset="utf-8" If the guest feeds invalid data to the UHCI controller, we can assert: qemu-system-x86_64: ../../hw/usb/core.c:744: usb_ep_get: Assertion `pid =3D= =3D USB_TOKEN_IN || pid =3D=3D USB_TOKEN_OUT' failed. (see issue 2548 for the repro case). This happens because the guest attempts USB_TOKEN_SETUP to an endpoint other than 0, which is not valid. The controller code doesn't catch this guest error, so instead we hit the assertion in the USB core code. Catch the case of SETUP to non-zero endpoint, and treat it as a fatal error in the TD, in the same way we do for an invalid PID value in the TD. This is the UHCI equivalent of the same bug in OHCI that we fixed in commit 3c3c233677 ("hw/usb/hcd-ohci: Fix #1510, #303: pid not IN or OUT"). This bug has been tracked as CVE-2024-8354. Cc: qemu-stable@nongnu.org Fixes: https://gitlab.com/qemu-project/qemu/-/issues/2548 Signed-off-by: Peter Maydell Reviewed-by: Michael Tokarev --- hw/usb/hcd-uhci.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/hw/usb/hcd-uhci.c b/hw/usb/hcd-uhci.c index 4822c704f69..e207d0587a1 100644 --- a/hw/usb/hcd-uhci.c +++ b/hw/usb/hcd-uhci.c @@ -735,6 +735,7 @@ static int uhci_handle_td(UHCIState *s, UHCIQueue *q, u= int32_t qh_addr, bool spd; bool queuing =3D (q !=3D NULL); uint8_t pid =3D td->token & 0xff; + uint8_t ep_id =3D (td->token >> 15) & 0xf; UHCIAsync *async; =20 async =3D uhci_async_find_td(s, td_addr); @@ -778,9 +779,14 @@ static int uhci_handle_td(UHCIState *s, UHCIQueue *q, = uint32_t qh_addr, =20 switch (pid) { case USB_TOKEN_OUT: - case USB_TOKEN_SETUP: case USB_TOKEN_IN: break; + case USB_TOKEN_SETUP: + /* SETUP is only valid to endpoint 0 */ + if (ep_id =3D=3D 0) { + break; + } + /* fallthrough */ default: /* invalid pid : frame interrupted */ s->status |=3D UHCI_STS_HCPERR; @@ -829,7 +835,7 @@ static int uhci_handle_td(UHCIState *s, UHCIQueue *q, u= int32_t qh_addr, return uhci_handle_td_error(s, td, td_addr, USB_RET_NODEV, int_mask); } - ep =3D usb_ep_get(dev, pid, (td->token >> 15) & 0xf); + ep =3D usb_ep_get(dev, pid, ep_id); q =3D uhci_queue_new(s, qh_addr, td, ep); } async =3D uhci_async_alloc(q, td_addr); --=20 2.43.0 From nobody Sun Sep 28 15:26:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758896660; cv=none; d=zohomail.com; s=zohoarc; b=gh5ioL/LCCU6Zu9pbGXYiyO/IiyaOMxr9Bk5M2ELDauD3aBU63OFYqIyqgJ1gZbajPFiBdGuWbme6+lLUVZn3NJeLmkscPX07NkLTWB8sLuUQR8UXZdje1D/2oYHD49yidNCU82190WIZUtBDGPf9eMlPWRFA7Uor4oLfdy17I0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758896660; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=LteooIRckejsKoiNLalnbU5BZGqP5YHRgNXf4dsk110=; b=BP+gMH06UwJS6gv7UcaaWpohlc3oeCSvm2D6EqfSHFJc6GkwcKVYYPRvA12at4luUspZdLLpTtAcAqrxL1wiFHCFUarJPPJtNqQdl8vukw89EJIcsXYvUfDvU5G/sqIiRzIwnFNM6V0mhaEv7DfXJnFJ/P1mV3EPHWj57+P4KWg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1758896660607199.09111154705909; Fri, 26 Sep 2025 07:24:20 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v298O-0007AM-Bh; Fri, 26 Sep 2025 10:09:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v298G-00079I-SJ for qemu-devel@nongnu.org; Fri, 26 Sep 2025 10:09:09 -0400 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1v2984-0005cz-5O for qemu-devel@nongnu.org; Fri, 26 Sep 2025 10:09:08 -0400 Received: by mail-wr1-x430.google.com with SMTP id ffacd0b85a97d-3f0308469a4so1433830f8f.0 for ; Fri, 26 Sep 2025 07:08:54 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-410f2007372sm6338315f8f.16.2025.09.26.07.08.47 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Sep 2025 07:08:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758895729; x=1759500529; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=LteooIRckejsKoiNLalnbU5BZGqP5YHRgNXf4dsk110=; b=mtLJGN1K5YZ80zbZ+WUW8oVTo+blpH+o2180/LUFq/1oPL23tm2sMWgtOSnTP3Ey3n qrF4mzZnOpXeyPFTDLzKbkbVoKu5oP5i/HH/2djf2ImNtuNskbQnLAGaIynopoewjbmS ejTAERHU2RlgGlUtz/Sk9KCySbkHcJ7Sx9RzOATrtyAgTWMZYlr25u8RI+2fBvTS/cVx d9bIXd8ycHZ104DiB046cRLvnP7BB0EiZfJ7InSD6/WDs99Jze6t9qKlrWVm4DatOwW3 zQxtI7AYLvxz0TAa3j/wP9FCRkyW8Cd7jfC1Pdh3mKJBCTgcBW0sizT05/oJPSS5wjDR ICBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758895729; x=1759500529; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LteooIRckejsKoiNLalnbU5BZGqP5YHRgNXf4dsk110=; b=ZN7l5Gb8qGjX601ygOAMABiNUUsa1Q7D/uAlp+JleTp5fcZqOhifsjcg+FUxmkyHmH 9sAsROl1lpXXkDyOrVVomBPMTBW2OPyz2NP1tYpFRkLDuqG5hFQms0vwU+3C8Ujl3ls/ I3TasDhUCWIy19xxsQl/xVuNUn/82HtPvr1V3P3s/u1YgygpZxFTJ5t8OAt/rarBjI+w t0kvBsCdc3StZy3cYOVOaQJHPaxCI+mGDg1coDcjsNh6CChMPKwLkAtOY/ITOv6ZYr6X YsD1atldwjsQXW3yONS4M+o+Y4lQQMC8J/gSFMEOAxgKNlfIVkHsD+MCmSDULYSdMuZd qV7Q== X-Gm-Message-State: AOJu0Yzn3QoXl74AT1xNrco1ppRgKSxfUEnuvgullxGVuBuJqRJ3VYhA i1HFg2lUt6vq4nsJkoLJoqIC9KHspwqhTjem61mbcJY4abE8juZ3GjtQtaPhTnjbSbsxCUGjpcu 6IESK X-Gm-Gg: ASbGnctXhIe8tWnmBA4sxV81evgrEEuDqMkqHlBN/eooJyRSlcMZnmDiU6HshWT3h4U AH6t9rBIW9KqSh1RRUn2uH0SiY0rDqs8iMn4AQGBqfokkxSNclAt9eSBDPXAwilkPnmNoXBkYwV mewWbcn17tfTAwiqM94RBDRRv7r5jG2c+YnGVEa08hDoossSe92HtvBHJQda8+U9OMBhnyNnt5Q BJCcUqAMvSsmKwYseMtfJP8OfD/nd8xRIAVYVaDdTF3sMpGR4jYbB3dNeJ0wEgsuhvD2wy6Qxv9 uyXdkOCVqpSvn8+OOhqMd96Sg+MYGohAJv8sVlPvvA250s4zPxp9XqCZntSS3kdvisso8Nl90WN olY98mS1toYRSoznJ+e5mcqsAu3vxXtHXAeorfRw= X-Google-Smtp-Source: AGHT+IFiRiSDZ2YRmxIIxIX0jH+HDHQBa2F+T+f0CmG9OBsv7KjshEUKJKlWdRCH82hkfwIWbtfz7Q== X-Received: by 2002:a05:6000:4282:b0:3dd:981d:43a5 with SMTP id ffacd0b85a97d-40e4b294eacmr6139675f8f.47.1758895728770; Fri, 26 Sep 2025 07:08:48 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/44] net/passt: Fix build failure due to missing GIO dependency Date: Fri, 26 Sep 2025 15:08:02 +0100 Message-ID: <20250926140844.1493020-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250926140844.1493020-1-peter.maydell@linaro.org> References: <20250926140844.1493020-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758896662212116600 From: Laurent Vivier The passt networking backend uses functions from the GIO library, such as g_subprocess_launcher_new(), to manage its daemon process. So, building with passt enabled requires GIO to be available. If we enable passt and disable gio the build fails during linkage with undefined reference errors: /usr/bin/ld: libsystem.a.p/net_passt.c.o: in function `net_passt_start_da= emon': net/passt.c:250: undefined reference to `g_subprocess_launcher_new' /usr/bin/ld: net/passt.c:251: undefined reference to `g_subprocess_launch= er_take_fd' /usr/bin/ld: net/passt.c:253: undefined reference to `g_subprocess_launch= er_spawnv' /usr/bin/ld: net/passt.c:256: undefined reference to `g_object_unref' /usr/bin/ld: net/passt.c:263: undefined reference to `g_subprocess_wait' /usr/bin/ld: net/passt.c:268: undefined reference to `g_subprocess_get_if= _exited' /usr/bin/ld: libsystem.a.p/net_passt.c.o: in function `glib_autoptr_clear= _GSubprocess': /usr/include/glib-2.0/gio/gio-autocleanups.h:132: undefined reference to = `g_object_unref' /usr/bin/ld: libsystem.a.p/net_passt.c.o: in function `net_passt_start_da= emon': net/passt.c:269: undefined reference to `g_subprocess_get_exit_status' Fix this by adding an explicit weson dependency on GIO for the passt option. The existing dependency on linux is kept because passt is only available on this OS. Cc: qemu-stable@nongnu.org Fixes: 854ee02b222 ("net: Add passt network backend") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3121 Reported-by: Thomas Huth Signed-off-by: Laurent Vivier Reviewed-by: Thomas Huth Reviewed-by: Daniel P. Berrang=C3=A9 Signed-off-by: Peter Maydell --- meson.build | 1 + 1 file changed, 1 insertion(+) diff --git a/meson.build b/meson.build index 72da97829ab..bdfb6214e6f 100644 --- a/meson.build +++ b/meson.build @@ -1280,6 +1280,7 @@ endif =20 enable_passt =3D get_option('passt') \ .require(host_os =3D=3D 'linux', error_message: 'passt is supported only= on Linux') \ + .require(gio.found(), error_message: 'passt requires gio') \ .allowed() =20 vde =3D not_found --=20 2.43.0 From nobody Sun Sep 28 15:26:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758896886; cv=none; d=zohomail.com; s=zohoarc; b=ePqli8Ka0kPKGF/vvyWLhCzZrt2ss63HIJpy4lPyZBim+Y+4XCxsJgE2mV+yiassnmBHjjGzGbGwwaJojE6aILcG+hph1bs+3DkvGRy1YaeqCnsMtT/iZxKA72W76MO2TuTKiuPtw3b/fmH1EtMOByHBfp6cpqxslxuvcDr4Jfs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758896886; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=eDFX7y4atdN+lmLu8Si4CvEkIGbpJPZtNB7piylWeSY=; b=HwS2X89tuQ5huU+inAzpRhSMcAByBqQ/3B7Y+u5ubmMRx4AabL5hGGp4f7TOAXUZp8l3+kKgm4P7ejSJkTzqG16S3RHlc9Icp9U+JwvqwRgGgu6TUVC3FDjpwpRCZsTd4YPD+pHVcWSKWDFIE18UzZ2Fv9f6IyYYLeOG+DDy+Is= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1758896886191570.0527164758729; Fri, 26 Sep 2025 07:28:06 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v298I-00079K-Mm; Fri, 26 Sep 2025 10:09:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v298F-00078a-Kd for qemu-devel@nongnu.org; Fri, 26 Sep 2025 10:09:07 -0400 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1v2986-0005d0-2t for qemu-devel@nongnu.org; Fri, 26 Sep 2025 10:09:05 -0400 Received: by mail-wr1-x434.google.com with SMTP id ffacd0b85a97d-3ee64bc6b85so2062968f8f.3 for ; Fri, 26 Sep 2025 07:08:53 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-410f2007372sm6338315f8f.16.2025.09.26.07.08.48 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Sep 2025 07:08:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758895730; x=1759500530; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=eDFX7y4atdN+lmLu8Si4CvEkIGbpJPZtNB7piylWeSY=; b=ObcBZ9yUjUlKhEzGjNNdlUlF6BHlfkOjQsCA97VPMybnBOeH5P+pI46y8UIamfMrV7 vjLZy+T6H2sQLVj6qiFtFdivPge5X7SYPSMvfBLnYG44Y676R7C9IL+9ejk7hntL5FXm 4M1SPLSZRawJhpPEleHl02ym51FUZck+GpEOXnmoVxJr4LCcdOA0warUe6XQO+Sj6Pdf Fu/WMdCv57TDtsO+prU28XpO1tFwxro/RqQWJCPp7v1ROCAxqlZmRBHsg1Gl+epCx4em 2AUfcfNz8qtrOg+zwhEnsrZUCETAHrkfjMfQB1vtqQWnHqPX0w7qaMOGfzp6tW1Vc0wp nSsQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758895730; x=1759500530; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eDFX7y4atdN+lmLu8Si4CvEkIGbpJPZtNB7piylWeSY=; b=geZf7ZZ0mLA1g/cBNSoqlePghgx7iYZRgbeAzLjKnrhoL48ZnBOXUMu5NpmCgCE+f5 XVaTimLLnglETaNYUxjpu0fn/1cp1jyUOfVQ21ShW4Fr/bvao5yWtGhH1pjs2GSyRlH5 yVQMBT5weWXHgu3A/GvWw4JnHQc2Q43DviFJWFd2BnMYZQTMsQdT4z1DCAHcYXa8eT62 2Ur2Av64+gafxgL+Z20xPWQr0aeg9RDTuCj1S5NGIGxFaTYHj0CM0VtQKjpjejal13TN B6s3Y6p4xkrneqHAOH4T7xphmmuH+Ufbf58hqQkOo0D5RBDSsPnX4/pMNS0wcaIyjoZl UPFQ== X-Gm-Message-State: AOJu0YxZK5OEWLklZYBe6XU1KVdTkY2HELzHmYrGbtwsJLU31jMH7lWW HPqWXzQU6fsOiCVwwST54NcrLvOxUC2xS1O+AKHNPZvsJEFvk2J4mAYyJf9y0odEjipgpYF0STd /pLqc X-Gm-Gg: ASbGncubogUeVg0xZJ2i9S5XV4yL9mOL9FsxoO7kOe0uS/77AhqLhpkO77Aw7ca4f1y Gh3oarsMGpLHRzDKg+AUOkScbTBKPp9T3JKIQwKfFLlICqaX78e9rkwg+XjDxP8WP3Fq6H/cLhB mAFiv8oahiidCQix649N7ExSm6PEznLZDEKSHMmmvVj9N0Xn+tITMOKcEmqbJgqqBmST0FMeHjj 6yNn8lF28sTzOFhFdhrsQm0k3fMMQtUPTtjjHNIyeSHK6soNb7GcWYTIBbKr3BN+pFs5b/gw1VB 23vwptHrI+lMY/RFusRIq43CcO7KxTvlEE8paaTgTFX12VTL3t1GI8WttaQCBLZkKOokEiHUl9+ IgsDRvRFNLzlSIaKRcMh+Ucxy5Lu9xQIK3l6lBPg= X-Google-Smtp-Source: AGHT+IFlTbUdJ8ApgOD2m0UMPYCRAh/iL3YXXivP5feAPaZuKn2mHgpek8ysUQKXtZFRIGzKyLAOKA== X-Received: by 2002:a05:6000:26ce:b0:3ee:141a:ede5 with SMTP id ffacd0b85a97d-40e4a42f3aemr6923075f8f.57.1758895729897; Fri, 26 Sep 2025 07:08:49 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/44] target/arm: Introduce KVMID_AA64_SYS_REG64 Date: Fri, 26 Sep 2025 15:08:03 +0100 Message-ID: <20250926140844.1493020-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250926140844.1493020-1-peter.maydell@linaro.org> References: <20250926140844.1493020-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758896887481116600 From: Richard Henderson Allow us to create kvm ids directly, rather than going through ENCODE_AA64_CP_REG + cpreg_to_kvm_id. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- target/arm/kvm-consts.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/target/arm/kvm-consts.h b/target/arm/kvm-consts.h index c44d23dbe79..fdb305eea1a 100644 --- a/target/arm/kvm-consts.h +++ b/target/arm/kvm-consts.h @@ -180,4 +180,15 @@ MISMATCH_CHECK(CP_REG_ARM64_SYSREG_OP2_SHIFT, KVM_REG_= ARM64_SYSREG_OP2_SHIFT); =20 #undef MISMATCH_CHECK =20 +#define KVMID_AA64_SYS_REG_(op0, op1, crn, crm, op2) \ + (CP_REG_AA64_MASK | CP_REG_ARM64_SYSREG | \ + ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ + ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ + ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ + ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ + ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) + +#define KVMID_AA64_SYS_REG64(op0, op1, crn, crm, op2) \ + (KVMID_AA64_SYS_REG_(op0, op1, crn, crm, op2) | CP_REG_SIZE_U64) + #endif --=20 2.43.0 From nobody Sun Sep 28 15:26:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758895872; cv=none; d=zohomail.com; s=zohoarc; b=BqA4fMdyOs6HDXc4kV+lZ3LlfhOoNPLrUx/ZorfCQl7yDRWXsejZ2TZ3jrZNrtZpMU0UFg6HQwPQeW/EMIS8usVQWABeQwEt+iWKBPGVml9t5XPGR1ZcWS/9LZH2R32D9pap23orJ4HhtW1NhFt2rdPcE2XHMIQ2ww2RhplbJWs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758895872; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=Aub0nVeKDypnEosBAZhauPvYLD0GV/ykfag+qkNYCrU=; b=S3S6SFQ1G1kWiI27jK3yioqZmC/2h3XkOmzBfwnRzddK821B5wmBrwtmKwT9W/TS1ZmX6t/Urnya2Id0xQroejF79Bqe94DA/z3WgbgfjVFkD0mrgTLcBU3JDiMGogBer4AtJaVYSlN3tKpbP9nY0bBlqeAdpRvH+wS0s3FonUI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1758895872624447.8299301586003; Fri, 26 Sep 2025 07:11:12 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v298H-00079O-O6; Fri, 26 Sep 2025 10:09:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v298F-00078c-Rk for qemu-devel@nongnu.org; Fri, 26 Sep 2025 10:09:07 -0400 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1v2988-0005dP-2N for qemu-devel@nongnu.org; Fri, 26 Sep 2025 10:09:07 -0400 Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-46e317bc647so15089975e9.2 for ; Fri, 26 Sep 2025 07:08:54 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-410f2007372sm6338315f8f.16.2025.09.26.07.08.50 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Sep 2025 07:08:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758895731; x=1759500531; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Aub0nVeKDypnEosBAZhauPvYLD0GV/ykfag+qkNYCrU=; b=uXbCU6ETuUK94hrbQb5Y3wtHFvcPl7CogCCVpEa1aScS5WHeOmTtB4JvOnUHzrtCYP zaB3YJgyOnwzLDN3Ej5CBzan8rlYNYwFNndsAa/htL0jVxjxzCYv9a7qYGtynZsEbvQm 1sF8v9Bf6vaeu9GMs5/C3j2YSqzY1BvxrogVRxT9nvZrBWQlFy3hS67/sI9fga82dW6D gcXSywC/+nhaUDZ4Hc4Uaz4aBW6auZKRBO7AkJ6pBXHMAKanrQw1N6aI4niQyyfM2rxm Bco2cfnnLFFUfuWZ/7NwVPhdEEYR7Cu1iiG/J79FhRnA5F8i5joya1BWc9KlcbP43poU vFrw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758895731; x=1759500531; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Aub0nVeKDypnEosBAZhauPvYLD0GV/ykfag+qkNYCrU=; b=p4S7IwELR7kKDru2oBAXIlFnM/zuVB/t5EnlLUCwGcUf1e3v51CciosDFEzcJFHlxk RBRN4yQuJ6kzF5VUunT3x331D4IRMk0ackPaGvBREU15MOIzklcy4HAR/SXyNWcOPBRS 4c5e0mouDqwN7/61y9vYSUq7XKT+8ze0OioAITTRbjho40Cmr1FEFau5hR2TWSttro55 hJsMcpM5V4OT3ctUochFXrgrw4b3Uhy1JwgWY+/ImvMmG0/DgXOZkcBotxnHyza7bxx/ mTB3Yflg28t11DBhyZh1ecEldGNu+rCvr36sJugaL8gv2IKcMyBb8uF571eGI553tEaI +GAg== X-Gm-Message-State: AOJu0YyZv5bAuvYc8cUcA4oxwqFt9mzSuahc7ZX9YM0dHJdAKcgcIyb2 h4dejA5p4dKedCf4OA8xiIEE3LyIfnmtKd0SKKPJp84U4OvBlcRgEg3eNS5jdNlJp3KL+S6P2xn A/rYn X-Gm-Gg: ASbGncskC1HRvNrQWNLn/AfyQc7JIlritaDZn8GWX9CvrTaKNljm7XG+dsLb2NF3BxX kgE+4sZ8bKGDS8Zvoz+dnzRAwEm6p/J9Af+LoUeiaIbFddKincUEtF4jMhk7PNu2bpB9/rFB4hR Skz3WJRB7gXdfYyQvcQorgefY5SLhRsQqm+SzA+p7MUktEiODRA/F9eYQ7EAR4ozmX1YF2fvm9P VYWfaRJwRik0eaNbLCCXnK5+yibtH7Y1OpFN05jYoZUKS8sOAZzV5jkSXF5RG4Hmg9l7zQlz9s5 zoJ3YnDRlJxmxSDTwBwvJDFeCeUfMXfYVifsM6fpRjgY7upFVygPP4hL5BBIcIlPsaqJFpaJEFB ELjnvcOAyzuj4uSxCU3bXN+BBAy/1 X-Google-Smtp-Source: AGHT+IFmde5bhCain99h9qKHekJ4l7v/p00ytAq0jM1Hdu+l/yBG74LKE6hH8Fc+IJ1i2lArMRV0bA== X-Received: by 2002:a05:600c:6306:b0:46d:9d28:fb5e with SMTP id 5b1f17b1804b1-46e329ab29cmr77139855e9.5.1758895731199; Fri, 26 Sep 2025 07:08:51 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/44] target/arm: Move compare_u64 to helper.c Date: Fri, 26 Sep 2025 15:08:04 +0100 Message-ID: <20250926140844.1493020-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250926140844.1493020-1-peter.maydell@linaro.org> References: <20250926140844.1493020-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758895874315116600 From: Richard Henderson We will use this function beyond kvm.c. Reviewed-by: Manos Pitsidianakis Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- target/arm/internals.h | 3 +++ target/arm/helper.c | 11 +++++++++++ target/arm/kvm.c | 11 ----------- 3 files changed, 14 insertions(+), 11 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 0f7df97b993..1d958dbf685 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -2004,4 +2004,7 @@ void vfp_clear_float_status_exc_flags(CPUARMState *en= v); void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t val, uint32_t mask); bool arm_pan_enabled(CPUARMState *env); =20 +/* Compare uint64_t for qsort and bsearch. */ +int compare_u64(const void *a, const void *b); + #endif diff --git a/target/arm/helper.c b/target/arm/helper.c index c44294711f8..009f8d6fa1c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -40,6 +40,17 @@ =20 static void switch_mode(CPUARMState *env, int mode); =20 +int compare_u64(const void *a, const void *b) +{ + if (*(uint64_t *)a > *(uint64_t *)b) { + return 1; + } + if (*(uint64_t *)a < *(uint64_t *)b) { + return -1; + } + return 0; +} + uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri) { assert(ri->fieldoffset); diff --git a/target/arm/kvm.c b/target/arm/kvm.c index c1ec6654ca6..5a75ff59271 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -718,17 +718,6 @@ void kvm_arm_register_device(MemoryRegion *mr, uint64_= t devid, uint64_t group, memory_region_ref(kd->mr); } =20 -static int compare_u64(const void *a, const void *b) -{ - if (*(uint64_t *)a > *(uint64_t *)b) { - return 1; - } - if (*(uint64_t *)a < *(uint64_t *)b) { - return -1; - } - return 0; -} - /* * cpreg_values are sorted in ascending order by KVM register ID * (see kvm_arm_init_cpreg_list). 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-410f2007372sm6338315f8f.16.2025.09.26.07.08.51 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Sep 2025 07:08:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758895733; x=1759500533; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=R7sYGUIrEqXggeK17PbOJ3HwiSLwWiLs/Tkhv2YZqIw=; b=rA9vI3RhVA3YRLvmquks++A9TbA/nh6heMrqBpy/WN9juVRuj0/NWMYeRPY9OGZNIq VxcxcdJAEd0u8WAdQQ32g93q3R2zZFi9bCoT9vHj3UGSlTcPWBLgvI6WJ9i2CoSGBZoY 3rX3UzA6euHUqdGofm9dcxLZyJTWVClgJ3IqqOJcgKWh//ljW/h1eejGWiQ3LVe9jO55 QLbjaMlIUn0dZwRFuHIW4Fmg1hdSwwyHyVZ47nRuTevCM020PlLB20js7o1FYuTxg1Hp jbE/eilAnmQnhD4f9+0gjpzsGKfxIgZwDP4igT2yK0jPtX5lbWQCROw6sTzn8CG7bGG7 eJbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758895733; x=1759500533; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=R7sYGUIrEqXggeK17PbOJ3HwiSLwWiLs/Tkhv2YZqIw=; b=Jti/U9ad+5I9+Re29ogUYINSFtccwxuu/jRmvgAY7HE3biq+JSHvGltOqon/4Hd3tV tUjFsr+DmpTq84Qio/69ArjUCaN59XwC2aAQzrrgEmOzfvho8iWPrzAD/7sFAuEj78zW nyWW3kCRPON/SkEN/rtdh8oVNBeHfV1MFId3kXMkzmA5FqfcjLWAzJKEnDfAVh3LisE0 ML+3FgNP07hdXDO9EPNzcffzXurz59nunXAhUzlW//E8WWLpx7kxTynmxYNiDXdUKaCl GvfObtFv2QHm65fC3+T28+QZWJRka9PNg6SxfdUml5VAlAeW9XoG1JuF+zkSubflA0/r q15A== X-Gm-Message-State: AOJu0Yyug8DGKrGnGnStki2aV8lrZc1gJpm1imZX6OT7bg3yzz2zAt9w VxkEso/V4IhzBCqGXGVFrWswM0kxLFkMa6frn2vvUS0q8OXEjWCAH+/bt4pzOgS62QogCLBMJQ4 yEjbU X-Gm-Gg: ASbGncuc8B9F82AlsZw3CZwNE+HxGk7PJ/2l8D7OzkHaT/SNyuvgRMK/7kXv/VWFRQg 4yQYNwRkb7JJ4dQv7c5U35aAuwxa6mNurCnq7JDj5tZR74OxxWN/y7WoOT9l5ow5mlwr7YOGJRW GqQ0uSPbJH+m+Ldk0hkXCbEwmiZV8dhKVQbPS3jHhD2oKnI6TISkbZSNLRDBbXacaW7Qc3TL1Bc BTkVzye2nmxem0KyL9Iue78+/1j9BLPR/mdiK+CUmKF/VO9obYuAqSsLHEHJPKJ/D6Zts0K1jkI BI9HbZtDiqVX2e0/hYP5SoVhoLewUV/XCCwbTFuUSE+PwZZIpYlbBLV5Y62ITlLM0CEryWoSXbk 7wcaIMBPqyiR/1LYpuaY81Fjr7Ql1gkT4xrInFn8= X-Google-Smtp-Source: AGHT+IGy+VsjYMDrsWEYSQwhGk6P1XCRWbz/RD3mjqAgM9xQBG8G1SH2j9oItAFHLguQvJf6KC2YIA== X-Received: by 2002:a05:6000:220b:b0:3ec:df2b:14c8 with SMTP id ffacd0b85a97d-40e4458ce98mr7203647f8f.20.1758895732465; Fri, 26 Sep 2025 07:08:52 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/44] target/arm/hvf: Split out sysreg.c.inc Date: Fri, 26 Sep 2025 15:08:05 +0100 Message-ID: <20250926140844.1493020-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250926140844.1493020-1-peter.maydell@linaro.org> References: <20250926140844.1493020-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758895908559116600 From: Richard Henderson Move the list of supported sysregs to a reuseable file. Reviewed-by: Manos Pitsidianakis Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- target/arm/hvf/hvf.c | 147 ++---------------------------------- target/arm/hvf/sysreg.c.inc | 146 +++++++++++++++++++++++++++++++++++ 2 files changed, 152 insertions(+), 141 deletions(-) create mode 100644 target/arm/hvf/sysreg.c.inc diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index b77db99079e..9f8e3083b4f 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -403,150 +403,15 @@ struct hvf_sreg_match { uint32_t cp_idx; }; =20 +#define DEF_SYSREG(HVF_ID, crn, crm, op0, op1, op2) \ + { HVF_ID, HVF_SYSREG(crn, crm, op0, op1, op2) }, + static struct hvf_sreg_match hvf_sreg_match[] =3D { - { HV_SYS_REG_DBGBVR0_EL1, HVF_SYSREG(0, 0, 2, 0, 4) }, - { HV_SYS_REG_DBGBCR0_EL1, HVF_SYSREG(0, 0, 2, 0, 5) }, - { HV_SYS_REG_DBGWVR0_EL1, HVF_SYSREG(0, 0, 2, 0, 6) }, - { HV_SYS_REG_DBGWCR0_EL1, HVF_SYSREG(0, 0, 2, 0, 7) }, - - { HV_SYS_REG_DBGBVR1_EL1, HVF_SYSREG(0, 1, 2, 0, 4) }, - { HV_SYS_REG_DBGBCR1_EL1, HVF_SYSREG(0, 1, 2, 0, 5) }, - { HV_SYS_REG_DBGWVR1_EL1, HVF_SYSREG(0, 1, 2, 0, 6) }, - { HV_SYS_REG_DBGWCR1_EL1, HVF_SYSREG(0, 1, 2, 0, 7) }, - - { HV_SYS_REG_DBGBVR2_EL1, HVF_SYSREG(0, 2, 2, 0, 4) }, - { HV_SYS_REG_DBGBCR2_EL1, HVF_SYSREG(0, 2, 2, 0, 5) }, - { HV_SYS_REG_DBGWVR2_EL1, HVF_SYSREG(0, 2, 2, 0, 6) }, - { HV_SYS_REG_DBGWCR2_EL1, HVF_SYSREG(0, 2, 2, 0, 7) }, - - { HV_SYS_REG_DBGBVR3_EL1, HVF_SYSREG(0, 3, 2, 0, 4) }, - { HV_SYS_REG_DBGBCR3_EL1, HVF_SYSREG(0, 3, 2, 0, 5) }, - { HV_SYS_REG_DBGWVR3_EL1, HVF_SYSREG(0, 3, 2, 0, 6) }, - { HV_SYS_REG_DBGWCR3_EL1, HVF_SYSREG(0, 3, 2, 0, 7) }, - - { HV_SYS_REG_DBGBVR4_EL1, HVF_SYSREG(0, 4, 2, 0, 4) }, - { HV_SYS_REG_DBGBCR4_EL1, HVF_SYSREG(0, 4, 2, 0, 5) }, - { HV_SYS_REG_DBGWVR4_EL1, HVF_SYSREG(0, 4, 2, 0, 6) }, - { HV_SYS_REG_DBGWCR4_EL1, HVF_SYSREG(0, 4, 2, 0, 7) }, - - { HV_SYS_REG_DBGBVR5_EL1, HVF_SYSREG(0, 5, 2, 0, 4) }, - { HV_SYS_REG_DBGBCR5_EL1, HVF_SYSREG(0, 5, 2, 0, 5) }, - { HV_SYS_REG_DBGWVR5_EL1, HVF_SYSREG(0, 5, 2, 0, 6) }, - { HV_SYS_REG_DBGWCR5_EL1, HVF_SYSREG(0, 5, 2, 0, 7) }, - - { HV_SYS_REG_DBGBVR6_EL1, HVF_SYSREG(0, 6, 2, 0, 4) }, - { HV_SYS_REG_DBGBCR6_EL1, HVF_SYSREG(0, 6, 2, 0, 5) }, - { HV_SYS_REG_DBGWVR6_EL1, HVF_SYSREG(0, 6, 2, 0, 6) }, - { HV_SYS_REG_DBGWCR6_EL1, HVF_SYSREG(0, 6, 2, 0, 7) }, - - { HV_SYS_REG_DBGBVR7_EL1, HVF_SYSREG(0, 7, 2, 0, 4) }, - { HV_SYS_REG_DBGBCR7_EL1, HVF_SYSREG(0, 7, 2, 0, 5) }, - { HV_SYS_REG_DBGWVR7_EL1, HVF_SYSREG(0, 7, 2, 0, 6) }, - { HV_SYS_REG_DBGWCR7_EL1, HVF_SYSREG(0, 7, 2, 0, 7) }, - - { HV_SYS_REG_DBGBVR8_EL1, HVF_SYSREG(0, 8, 2, 0, 4) }, - { HV_SYS_REG_DBGBCR8_EL1, HVF_SYSREG(0, 8, 2, 0, 5) }, - { HV_SYS_REG_DBGWVR8_EL1, HVF_SYSREG(0, 8, 2, 0, 6) }, - { HV_SYS_REG_DBGWCR8_EL1, HVF_SYSREG(0, 8, 2, 0, 7) }, - - { HV_SYS_REG_DBGBVR9_EL1, HVF_SYSREG(0, 9, 2, 0, 4) }, - { HV_SYS_REG_DBGBCR9_EL1, HVF_SYSREG(0, 9, 2, 0, 5) }, - { HV_SYS_REG_DBGWVR9_EL1, HVF_SYSREG(0, 9, 2, 0, 6) }, - { HV_SYS_REG_DBGWCR9_EL1, HVF_SYSREG(0, 9, 2, 0, 7) }, - - { HV_SYS_REG_DBGBVR10_EL1, HVF_SYSREG(0, 10, 2, 0, 4) }, - { HV_SYS_REG_DBGBCR10_EL1, HVF_SYSREG(0, 10, 2, 0, 5) }, - { HV_SYS_REG_DBGWVR10_EL1, HVF_SYSREG(0, 10, 2, 0, 6) }, - { HV_SYS_REG_DBGWCR10_EL1, HVF_SYSREG(0, 10, 2, 0, 7) }, - - { HV_SYS_REG_DBGBVR11_EL1, HVF_SYSREG(0, 11, 2, 0, 4) }, - { HV_SYS_REG_DBGBCR11_EL1, HVF_SYSREG(0, 11, 2, 0, 5) }, - { HV_SYS_REG_DBGWVR11_EL1, HVF_SYSREG(0, 11, 2, 0, 6) }, - { HV_SYS_REG_DBGWCR11_EL1, HVF_SYSREG(0, 11, 2, 0, 7) }, - - { HV_SYS_REG_DBGBVR12_EL1, HVF_SYSREG(0, 12, 2, 0, 4) }, - { HV_SYS_REG_DBGBCR12_EL1, HVF_SYSREG(0, 12, 2, 0, 5) }, - { HV_SYS_REG_DBGWVR12_EL1, HVF_SYSREG(0, 12, 2, 0, 6) }, - { HV_SYS_REG_DBGWCR12_EL1, HVF_SYSREG(0, 12, 2, 0, 7) }, - - { HV_SYS_REG_DBGBVR13_EL1, HVF_SYSREG(0, 13, 2, 0, 4) }, - { HV_SYS_REG_DBGBCR13_EL1, HVF_SYSREG(0, 13, 2, 0, 5) }, - { HV_SYS_REG_DBGWVR13_EL1, HVF_SYSREG(0, 13, 2, 0, 6) }, - { HV_SYS_REG_DBGWCR13_EL1, HVF_SYSREG(0, 13, 2, 0, 7) }, - - { HV_SYS_REG_DBGBVR14_EL1, HVF_SYSREG(0, 14, 2, 0, 4) }, - { HV_SYS_REG_DBGBCR14_EL1, HVF_SYSREG(0, 14, 2, 0, 5) }, - { HV_SYS_REG_DBGWVR14_EL1, HVF_SYSREG(0, 14, 2, 0, 6) }, - { HV_SYS_REG_DBGWCR14_EL1, HVF_SYSREG(0, 14, 2, 0, 7) }, - - { HV_SYS_REG_DBGBVR15_EL1, HVF_SYSREG(0, 15, 2, 0, 4) }, - { HV_SYS_REG_DBGBCR15_EL1, HVF_SYSREG(0, 15, 2, 0, 5) }, - { HV_SYS_REG_DBGWVR15_EL1, HVF_SYSREG(0, 15, 2, 0, 6) }, - { HV_SYS_REG_DBGWCR15_EL1, HVF_SYSREG(0, 15, 2, 0, 7) }, - -#ifdef SYNC_NO_RAW_REGS - /* - * The registers below are manually synced on init because they are - * marked as NO_RAW. We still list them to make number space sync easi= er. - */ - { HV_SYS_REG_MDCCINT_EL1, HVF_SYSREG(0, 2, 2, 0, 0) }, - { HV_SYS_REG_MIDR_EL1, HVF_SYSREG(0, 0, 3, 0, 0) }, - { HV_SYS_REG_MPIDR_EL1, HVF_SYSREG(0, 0, 3, 0, 5) }, - { HV_SYS_REG_ID_AA64PFR0_EL1, HVF_SYSREG(0, 4, 3, 0, 0) }, -#endif - { HV_SYS_REG_ID_AA64PFR1_EL1, HVF_SYSREG(0, 4, 3, 0, 1) }, - { HV_SYS_REG_ID_AA64DFR0_EL1, HVF_SYSREG(0, 5, 3, 0, 0) }, - { HV_SYS_REG_ID_AA64DFR1_EL1, HVF_SYSREG(0, 5, 3, 0, 1) }, - { HV_SYS_REG_ID_AA64ISAR0_EL1, HVF_SYSREG(0, 6, 3, 0, 0) }, - { HV_SYS_REG_ID_AA64ISAR1_EL1, HVF_SYSREG(0, 6, 3, 0, 1) }, -#ifdef SYNC_NO_MMFR0 - /* We keep the hardware MMFR0 around. HW limits are there anyway */ - { HV_SYS_REG_ID_AA64MMFR0_EL1, HVF_SYSREG(0, 7, 3, 0, 0) }, -#endif - { HV_SYS_REG_ID_AA64MMFR1_EL1, HVF_SYSREG(0, 7, 3, 0, 1) }, - { HV_SYS_REG_ID_AA64MMFR2_EL1, HVF_SYSREG(0, 7, 3, 0, 2) }, - /* Add ID_AA64MMFR3_EL1 here when HVF supports it */ - - { HV_SYS_REG_MDSCR_EL1, HVF_SYSREG(0, 2, 2, 0, 2) }, - { HV_SYS_REG_SCTLR_EL1, HVF_SYSREG(1, 0, 3, 0, 0) }, - { HV_SYS_REG_CPACR_EL1, HVF_SYSREG(1, 0, 3, 0, 2) }, - { HV_SYS_REG_TTBR0_EL1, HVF_SYSREG(2, 0, 3, 0, 0) }, - { HV_SYS_REG_TTBR1_EL1, HVF_SYSREG(2, 0, 3, 0, 1) }, - { HV_SYS_REG_TCR_EL1, HVF_SYSREG(2, 0, 3, 0, 2) }, - - { HV_SYS_REG_APIAKEYLO_EL1, HVF_SYSREG(2, 1, 3, 0, 0) }, - { HV_SYS_REG_APIAKEYHI_EL1, HVF_SYSREG(2, 1, 3, 0, 1) }, - { HV_SYS_REG_APIBKEYLO_EL1, HVF_SYSREG(2, 1, 3, 0, 2) }, - { HV_SYS_REG_APIBKEYHI_EL1, HVF_SYSREG(2, 1, 3, 0, 3) }, - { HV_SYS_REG_APDAKEYLO_EL1, HVF_SYSREG(2, 2, 3, 0, 0) }, - { HV_SYS_REG_APDAKEYHI_EL1, HVF_SYSREG(2, 2, 3, 0, 1) }, - { HV_SYS_REG_APDBKEYLO_EL1, HVF_SYSREG(2, 2, 3, 0, 2) }, - { HV_SYS_REG_APDBKEYHI_EL1, HVF_SYSREG(2, 2, 3, 0, 3) }, - { HV_SYS_REG_APGAKEYLO_EL1, HVF_SYSREG(2, 3, 3, 0, 0) }, - { HV_SYS_REG_APGAKEYHI_EL1, HVF_SYSREG(2, 3, 3, 0, 1) }, - - { HV_SYS_REG_SPSR_EL1, HVF_SYSREG(4, 0, 3, 0, 0) }, - { HV_SYS_REG_ELR_EL1, HVF_SYSREG(4, 0, 3, 0, 1) }, - { HV_SYS_REG_SP_EL0, HVF_SYSREG(4, 1, 3, 0, 0) }, - { HV_SYS_REG_AFSR0_EL1, HVF_SYSREG(5, 1, 3, 0, 0) }, - { HV_SYS_REG_AFSR1_EL1, HVF_SYSREG(5, 1, 3, 0, 1) }, - { HV_SYS_REG_ESR_EL1, HVF_SYSREG(5, 2, 3, 0, 0) }, - { HV_SYS_REG_FAR_EL1, HVF_SYSREG(6, 0, 3, 0, 0) }, - { HV_SYS_REG_PAR_EL1, HVF_SYSREG(7, 4, 3, 0, 0) }, - { HV_SYS_REG_MAIR_EL1, HVF_SYSREG(10, 2, 3, 0, 0) }, - { HV_SYS_REG_AMAIR_EL1, HVF_SYSREG(10, 3, 3, 0, 0) }, - { HV_SYS_REG_VBAR_EL1, HVF_SYSREG(12, 0, 3, 0, 0) }, - { HV_SYS_REG_CONTEXTIDR_EL1, HVF_SYSREG(13, 0, 3, 0, 1) }, - { HV_SYS_REG_TPIDR_EL1, HVF_SYSREG(13, 0, 3, 0, 4) }, - { HV_SYS_REG_CNTKCTL_EL1, HVF_SYSREG(14, 1, 3, 0, 0) }, - { HV_SYS_REG_CSSELR_EL1, HVF_SYSREG(0, 0, 3, 2, 0) }, - { HV_SYS_REG_TPIDR_EL0, HVF_SYSREG(13, 0, 3, 3, 2) }, - { HV_SYS_REG_TPIDRRO_EL0, HVF_SYSREG(13, 0, 3, 3, 3) }, - { HV_SYS_REG_CNTV_CTL_EL0, HVF_SYSREG(14, 3, 3, 3, 1) }, - { HV_SYS_REG_CNTV_CVAL_EL0, HVF_SYSREG(14, 3, 3, 3, 2) }, - { HV_SYS_REG_SP_EL1, HVF_SYSREG(4, 1, 3, 4, 0) }, +#include "sysreg.c.inc" }; =20 +#undef DEF_SYSREG + int hvf_get_registers(CPUState *cpu) { ARMCPU *arm_cpu =3D ARM_CPU(cpu); diff --git a/target/arm/hvf/sysreg.c.inc b/target/arm/hvf/sysreg.c.inc new file mode 100644 index 00000000000..222698f1d19 --- /dev/null +++ b/target/arm/hvf/sysreg.c.inc @@ -0,0 +1,146 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +DEF_SYSREG(HV_SYS_REG_DBGBVR0_EL1, 0, 0, 2, 0, 4) +DEF_SYSREG(HV_SYS_REG_DBGBCR0_EL1, 0, 0, 2, 0, 5) +DEF_SYSREG(HV_SYS_REG_DBGWVR0_EL1, 0, 0, 2, 0, 6) +DEF_SYSREG(HV_SYS_REG_DBGWCR0_EL1, 0, 0, 2, 0, 7) + +DEF_SYSREG(HV_SYS_REG_DBGBVR1_EL1, 0, 1, 2, 0, 4) +DEF_SYSREG(HV_SYS_REG_DBGBCR1_EL1, 0, 1, 2, 0, 5) +DEF_SYSREG(HV_SYS_REG_DBGWVR1_EL1, 0, 1, 2, 0, 6) +DEF_SYSREG(HV_SYS_REG_DBGWCR1_EL1, 0, 1, 2, 0, 7) + +DEF_SYSREG(HV_SYS_REG_DBGBVR2_EL1, 0, 2, 2, 0, 4) +DEF_SYSREG(HV_SYS_REG_DBGBCR2_EL1, 0, 2, 2, 0, 5) +DEF_SYSREG(HV_SYS_REG_DBGWVR2_EL1, 0, 2, 2, 0, 6) +DEF_SYSREG(HV_SYS_REG_DBGWCR2_EL1, 0, 2, 2, 0, 7) + +DEF_SYSREG(HV_SYS_REG_DBGBVR3_EL1, 0, 3, 2, 0, 4) +DEF_SYSREG(HV_SYS_REG_DBGBCR3_EL1, 0, 3, 2, 0, 5) +DEF_SYSREG(HV_SYS_REG_DBGWVR3_EL1, 0, 3, 2, 0, 6) +DEF_SYSREG(HV_SYS_REG_DBGWCR3_EL1, 0, 3, 2, 0, 7) + +DEF_SYSREG(HV_SYS_REG_DBGBVR4_EL1, 0, 4, 2, 0, 4) +DEF_SYSREG(HV_SYS_REG_DBGBCR4_EL1, 0, 4, 2, 0, 5) +DEF_SYSREG(HV_SYS_REG_DBGWVR4_EL1, 0, 4, 2, 0, 6) +DEF_SYSREG(HV_SYS_REG_DBGWCR4_EL1, 0, 4, 2, 0, 7) + +DEF_SYSREG(HV_SYS_REG_DBGBVR5_EL1, 0, 5, 2, 0, 4) +DEF_SYSREG(HV_SYS_REG_DBGBCR5_EL1, 0, 5, 2, 0, 5) +DEF_SYSREG(HV_SYS_REG_DBGWVR5_EL1, 0, 5, 2, 0, 6) +DEF_SYSREG(HV_SYS_REG_DBGWCR5_EL1, 0, 5, 2, 0, 7) + +DEF_SYSREG(HV_SYS_REG_DBGBVR6_EL1, 0, 6, 2, 0, 4) +DEF_SYSREG(HV_SYS_REG_DBGBCR6_EL1, 0, 6, 2, 0, 5) +DEF_SYSREG(HV_SYS_REG_DBGWVR6_EL1, 0, 6, 2, 0, 6) +DEF_SYSREG(HV_SYS_REG_DBGWCR6_EL1, 0, 6, 2, 0, 7) + +DEF_SYSREG(HV_SYS_REG_DBGBVR7_EL1, 0, 7, 2, 0, 4) +DEF_SYSREG(HV_SYS_REG_DBGBCR7_EL1, 0, 7, 2, 0, 5) +DEF_SYSREG(HV_SYS_REG_DBGWVR7_EL1, 0, 7, 2, 0, 6) +DEF_SYSREG(HV_SYS_REG_DBGWCR7_EL1, 0, 7, 2, 0, 7) + +DEF_SYSREG(HV_SYS_REG_DBGBVR8_EL1, 0, 8, 2, 0, 4) +DEF_SYSREG(HV_SYS_REG_DBGBCR8_EL1, 0, 8, 2, 0, 5) +DEF_SYSREG(HV_SYS_REG_DBGWVR8_EL1, 0, 8, 2, 0, 6) +DEF_SYSREG(HV_SYS_REG_DBGWCR8_EL1, 0, 8, 2, 0, 7) + +DEF_SYSREG(HV_SYS_REG_DBGBVR9_EL1, 0, 9, 2, 0, 4) +DEF_SYSREG(HV_SYS_REG_DBGBCR9_EL1, 0, 9, 2, 0, 5) +DEF_SYSREG(HV_SYS_REG_DBGWVR9_EL1, 0, 9, 2, 0, 6) +DEF_SYSREG(HV_SYS_REG_DBGWCR9_EL1, 0, 9, 2, 0, 7) + +DEF_SYSREG(HV_SYS_REG_DBGBVR10_EL1, 0, 10, 2, 0, 4) +DEF_SYSREG(HV_SYS_REG_DBGBCR10_EL1, 0, 10, 2, 0, 5) +DEF_SYSREG(HV_SYS_REG_DBGWVR10_EL1, 0, 10, 2, 0, 6) +DEF_SYSREG(HV_SYS_REG_DBGWCR10_EL1, 0, 10, 2, 0, 7) + +DEF_SYSREG(HV_SYS_REG_DBGBVR11_EL1, 0, 11, 2, 0, 4) +DEF_SYSREG(HV_SYS_REG_DBGBCR11_EL1, 0, 11, 2, 0, 5) +DEF_SYSREG(HV_SYS_REG_DBGWVR11_EL1, 0, 11, 2, 0, 6) +DEF_SYSREG(HV_SYS_REG_DBGWCR11_EL1, 0, 11, 2, 0, 7) + +DEF_SYSREG(HV_SYS_REG_DBGBVR12_EL1, 0, 12, 2, 0, 4) +DEF_SYSREG(HV_SYS_REG_DBGBCR12_EL1, 0, 12, 2, 0, 5) +DEF_SYSREG(HV_SYS_REG_DBGWVR12_EL1, 0, 12, 2, 0, 6) +DEF_SYSREG(HV_SYS_REG_DBGWCR12_EL1, 0, 12, 2, 0, 7) + +DEF_SYSREG(HV_SYS_REG_DBGBVR13_EL1, 0, 13, 2, 0, 4) +DEF_SYSREG(HV_SYS_REG_DBGBCR13_EL1, 0, 13, 2, 0, 5) +DEF_SYSREG(HV_SYS_REG_DBGWVR13_EL1, 0, 13, 2, 0, 6) +DEF_SYSREG(HV_SYS_REG_DBGWCR13_EL1, 0, 13, 2, 0, 7) + +DEF_SYSREG(HV_SYS_REG_DBGBVR14_EL1, 0, 14, 2, 0, 4) +DEF_SYSREG(HV_SYS_REG_DBGBCR14_EL1, 0, 14, 2, 0, 5) +DEF_SYSREG(HV_SYS_REG_DBGWVR14_EL1, 0, 14, 2, 0, 6) +DEF_SYSREG(HV_SYS_REG_DBGWCR14_EL1, 0, 14, 2, 0, 7) + +DEF_SYSREG(HV_SYS_REG_DBGBVR15_EL1, 0, 15, 2, 0, 4) +DEF_SYSREG(HV_SYS_REG_DBGBCR15_EL1, 0, 15, 2, 0, 5) +DEF_SYSREG(HV_SYS_REG_DBGWVR15_EL1, 0, 15, 2, 0, 6) +DEF_SYSREG(HV_SYS_REG_DBGWCR15_EL1, 0, 15, 2, 0, 7) + +#ifdef SYNC_NO_RAW_REGS +/* + * The registers below are manually synced on init because they are + * marked as NO_RAW. We still list them to make number space sync easier. + */ +DEF_SYSREG(HV_SYS_REG_MDCCINT_EL1, 0, 2, 2, 0, 0) +DEF_SYSREG(HV_SYS_REG_MIDR_EL1, 0, 0, 3, 0, 0) +DEF_SYSREG(HV_SYS_REG_MPIDR_EL1, 0, 0, 3, 0, 5) +DEF_SYSREG(HV_SYS_REG_ID_AA64PFR0_EL1, 0, 4, 3, 0, 0) +#endif + +DEF_SYSREG(HV_SYS_REG_ID_AA64PFR1_EL1, 0, 4, 3, 0, 1) +DEF_SYSREG(HV_SYS_REG_ID_AA64DFR0_EL1, 0, 5, 3, 0, 0) +DEF_SYSREG(HV_SYS_REG_ID_AA64DFR1_EL1, 0, 5, 3, 0, 1) +DEF_SYSREG(HV_SYS_REG_ID_AA64ISAR0_EL1, 0, 6, 3, 0, 0) +DEF_SYSREG(HV_SYS_REG_ID_AA64ISAR1_EL1, 0, 6, 3, 0, 1) + +#ifdef SYNC_NO_MMFR0 +/* We keep the hardware MMFR0 around. HW limits are there anyway */ +DEF_SYSREG(HV_SYS_REG_ID_AA64MMFR0_EL1, 0, 7, 3, 0, 0) +#endif + +DEF_SYSREG(HV_SYS_REG_ID_AA64MMFR1_EL1, 0, 7, 3, 0, 1) +DEF_SYSREG(HV_SYS_REG_ID_AA64MMFR2_EL1, 0, 7, 3, 0, 2) +/* Add ID_AA64MMFR3_EL1 here when HVF supports it */ + +DEF_SYSREG(HV_SYS_REG_MDSCR_EL1, 0, 2, 2, 0, 2) +DEF_SYSREG(HV_SYS_REG_SCTLR_EL1, 1, 0, 3, 0, 0) +DEF_SYSREG(HV_SYS_REG_CPACR_EL1, 1, 0, 3, 0, 2) +DEF_SYSREG(HV_SYS_REG_TTBR0_EL1, 2, 0, 3, 0, 0) +DEF_SYSREG(HV_SYS_REG_TTBR1_EL1, 2, 0, 3, 0, 1) +DEF_SYSREG(HV_SYS_REG_TCR_EL1, 2, 0, 3, 0, 2) + +DEF_SYSREG(HV_SYS_REG_APIAKEYLO_EL1, 2, 1, 3, 0, 0) +DEF_SYSREG(HV_SYS_REG_APIAKEYHI_EL1, 2, 1, 3, 0, 1) +DEF_SYSREG(HV_SYS_REG_APIBKEYLO_EL1, 2, 1, 3, 0, 2) +DEF_SYSREG(HV_SYS_REG_APIBKEYHI_EL1, 2, 1, 3, 0, 3) +DEF_SYSREG(HV_SYS_REG_APDAKEYLO_EL1, 2, 2, 3, 0, 0) +DEF_SYSREG(HV_SYS_REG_APDAKEYHI_EL1, 2, 2, 3, 0, 1) +DEF_SYSREG(HV_SYS_REG_APDBKEYLO_EL1, 2, 2, 3, 0, 2) +DEF_SYSREG(HV_SYS_REG_APDBKEYHI_EL1, 2, 2, 3, 0, 3) +DEF_SYSREG(HV_SYS_REG_APGAKEYLO_EL1, 2, 3, 3, 0, 0) +DEF_SYSREG(HV_SYS_REG_APGAKEYHI_EL1, 2, 3, 3, 0, 1) + +DEF_SYSREG(HV_SYS_REG_SPSR_EL1, 4, 0, 3, 0, 0) +DEF_SYSREG(HV_SYS_REG_ELR_EL1, 4, 0, 3, 0, 1) +DEF_SYSREG(HV_SYS_REG_SP_EL0, 4, 1, 3, 0, 0) +DEF_SYSREG(HV_SYS_REG_AFSR0_EL1, 5, 1, 3, 0, 0) +DEF_SYSREG(HV_SYS_REG_AFSR1_EL1, 5, 1, 3, 0, 1) +DEF_SYSREG(HV_SYS_REG_ESR_EL1, 5, 2, 3, 0, 0) +DEF_SYSREG(HV_SYS_REG_FAR_EL1, 6, 0, 3, 0, 0) +DEF_SYSREG(HV_SYS_REG_PAR_EL1, 7, 4, 3, 0, 0) +DEF_SYSREG(HV_SYS_REG_MAIR_EL1, 10, 2, 3, 0, 0) +DEF_SYSREG(HV_SYS_REG_AMAIR_EL1, 10, 3, 3, 0, 0) +DEF_SYSREG(HV_SYS_REG_VBAR_EL1, 12, 0, 3, 0, 0) +DEF_SYSREG(HV_SYS_REG_CONTEXTIDR_EL1, 13, 0, 3, 0, 1) +DEF_SYSREG(HV_SYS_REG_TPIDR_EL1, 13, 0, 3, 0, 4) +DEF_SYSREG(HV_SYS_REG_CNTKCTL_EL1, 14, 1, 3, 0, 0) +DEF_SYSREG(HV_SYS_REG_CSSELR_EL1, 0, 0, 3, 2, 0) +DEF_SYSREG(HV_SYS_REG_TPIDR_EL0, 13, 0, 3, 3, 2) +DEF_SYSREG(HV_SYS_REG_TPIDRRO_EL0, 13, 0, 3, 3, 3) +DEF_SYSREG(HV_SYS_REG_CNTV_CTL_EL0, 14, 3, 3, 3, 1) +DEF_SYSREG(HV_SYS_REG_CNTV_CVAL_EL0, 14, 3, 3, 3, 2) +DEF_SYSREG(HV_SYS_REG_SP_EL1, 4, 1, 3, 4, 0) --=20 2.43.0 From nobody Sun Sep 28 15:26:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758896111; cv=none; d=zohomail.com; s=zohoarc; b=DOY0IVw2//k74So8RZTbMl0Cpy2qtrd3PdtFHzNNqwBJB3As2/TOb3n2YDIdBX79LTzr6syzK4xJTzJcPvRJiIJJ4twjX+ovzxc7BNF9TfrTrgoyVeUlKPsDH8KrtbEoRmNX04THAg6GDI7cYa2hxBmcU0sdH0m2ln50XVYPm3Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758896111; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=b4EBqWxQdk+JIDg5eMqs4H05RLmTftPiIh75XqyWcMU=; b=h8YIvBrrQtBS0Owh/PA6ShnFPs6WtiQkCE9gJs4MgWC/QcJQIn1Oa7x7tBul1YzBk6M8q1o2rfLuLHwBej7Im7AUYtStYfCoy8KOrmGnpAXPYY4qckF+juZTpNcdUDTzj5zgiorPxtQ7e2AZGuDTHGtBQLgYDK8Fvxap7ymTAvY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1758896111878135.21597246354543; Fri, 26 Sep 2025 07:15:11 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v298Z-0007Sj-A5; Fri, 26 Sep 2025 10:09:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v298N-0007CL-TC for qemu-devel@nongnu.org; Fri, 26 Sep 2025 10:09:16 -0400 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1v2989-0005dk-KQ for qemu-devel@nongnu.org; Fri, 26 Sep 2025 10:09:15 -0400 Received: by mail-wr1-x42f.google.com with SMTP id ffacd0b85a97d-3f44000626bso1453133f8f.3 for ; Fri, 26 Sep 2025 07:08:57 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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Mechanical change to sysreg.c.inc using sed 's/\([^,]*\),\([^,]*\),\([^,]*\),\([^,]*\),\([^,]*\)/\1,\4,\5,\2,\3/' Reviewed-by: Manos Pitsidianakis Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- target/arm/hvf/hvf.c | 2 +- target/arm/hvf/sysreg.c.inc | 224 ++++++++++++++++++------------------ 2 files changed, 113 insertions(+), 113 deletions(-) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 9f8e3083b4f..f68924ba1f3 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -403,7 +403,7 @@ struct hvf_sreg_match { uint32_t cp_idx; }; =20 -#define DEF_SYSREG(HVF_ID, crn, crm, op0, op1, op2) \ +#define DEF_SYSREG(HVF_ID, op0, op1, crn, crm, op2) \ { HVF_ID, HVF_SYSREG(crn, crm, op0, op1, op2) }, =20 static struct hvf_sreg_match hvf_sreg_match[] =3D { diff --git a/target/arm/hvf/sysreg.c.inc b/target/arm/hvf/sysreg.c.inc index 222698f1d19..f2276d534e6 100644 --- a/target/arm/hvf/sysreg.c.inc +++ b/target/arm/hvf/sysreg.c.inc @@ -1,146 +1,146 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ =20 -DEF_SYSREG(HV_SYS_REG_DBGBVR0_EL1, 0, 0, 2, 0, 4) -DEF_SYSREG(HV_SYS_REG_DBGBCR0_EL1, 0, 0, 2, 0, 5) -DEF_SYSREG(HV_SYS_REG_DBGWVR0_EL1, 0, 0, 2, 0, 6) -DEF_SYSREG(HV_SYS_REG_DBGWCR0_EL1, 0, 0, 2, 0, 7) +DEF_SYSREG(HV_SYS_REG_DBGBVR0_EL1, 2, 0, 0, 0, 4) +DEF_SYSREG(HV_SYS_REG_DBGBCR0_EL1, 2, 0, 0, 0, 5) +DEF_SYSREG(HV_SYS_REG_DBGWVR0_EL1, 2, 0, 0, 0, 6) +DEF_SYSREG(HV_SYS_REG_DBGWCR0_EL1, 2, 0, 0, 0, 7) =20 -DEF_SYSREG(HV_SYS_REG_DBGBVR1_EL1, 0, 1, 2, 0, 4) -DEF_SYSREG(HV_SYS_REG_DBGBCR1_EL1, 0, 1, 2, 0, 5) -DEF_SYSREG(HV_SYS_REG_DBGWVR1_EL1, 0, 1, 2, 0, 6) -DEF_SYSREG(HV_SYS_REG_DBGWCR1_EL1, 0, 1, 2, 0, 7) +DEF_SYSREG(HV_SYS_REG_DBGBVR1_EL1, 2, 0, 0, 1, 4) +DEF_SYSREG(HV_SYS_REG_DBGBCR1_EL1, 2, 0, 0, 1, 5) +DEF_SYSREG(HV_SYS_REG_DBGWVR1_EL1, 2, 0, 0, 1, 6) +DEF_SYSREG(HV_SYS_REG_DBGWCR1_EL1, 2, 0, 0, 1, 7) =20 -DEF_SYSREG(HV_SYS_REG_DBGBVR2_EL1, 0, 2, 2, 0, 4) -DEF_SYSREG(HV_SYS_REG_DBGBCR2_EL1, 0, 2, 2, 0, 5) -DEF_SYSREG(HV_SYS_REG_DBGWVR2_EL1, 0, 2, 2, 0, 6) -DEF_SYSREG(HV_SYS_REG_DBGWCR2_EL1, 0, 2, 2, 0, 7) +DEF_SYSREG(HV_SYS_REG_DBGBVR2_EL1, 2, 0, 0, 2, 4) +DEF_SYSREG(HV_SYS_REG_DBGBCR2_EL1, 2, 0, 0, 2, 5) +DEF_SYSREG(HV_SYS_REG_DBGWVR2_EL1, 2, 0, 0, 2, 6) +DEF_SYSREG(HV_SYS_REG_DBGWCR2_EL1, 2, 0, 0, 2, 7) =20 -DEF_SYSREG(HV_SYS_REG_DBGBVR3_EL1, 0, 3, 2, 0, 4) -DEF_SYSREG(HV_SYS_REG_DBGBCR3_EL1, 0, 3, 2, 0, 5) -DEF_SYSREG(HV_SYS_REG_DBGWVR3_EL1, 0, 3, 2, 0, 6) -DEF_SYSREG(HV_SYS_REG_DBGWCR3_EL1, 0, 3, 2, 0, 7) +DEF_SYSREG(HV_SYS_REG_DBGBVR3_EL1, 2, 0, 0, 3, 4) +DEF_SYSREG(HV_SYS_REG_DBGBCR3_EL1, 2, 0, 0, 3, 5) +DEF_SYSREG(HV_SYS_REG_DBGWVR3_EL1, 2, 0, 0, 3, 6) +DEF_SYSREG(HV_SYS_REG_DBGWCR3_EL1, 2, 0, 0, 3, 7) =20 -DEF_SYSREG(HV_SYS_REG_DBGBVR4_EL1, 0, 4, 2, 0, 4) -DEF_SYSREG(HV_SYS_REG_DBGBCR4_EL1, 0, 4, 2, 0, 5) -DEF_SYSREG(HV_SYS_REG_DBGWVR4_EL1, 0, 4, 2, 0, 6) -DEF_SYSREG(HV_SYS_REG_DBGWCR4_EL1, 0, 4, 2, 0, 7) +DEF_SYSREG(HV_SYS_REG_DBGBVR4_EL1, 2, 0, 0, 4, 4) +DEF_SYSREG(HV_SYS_REG_DBGBCR4_EL1, 2, 0, 0, 4, 5) +DEF_SYSREG(HV_SYS_REG_DBGWVR4_EL1, 2, 0, 0, 4, 6) +DEF_SYSREG(HV_SYS_REG_DBGWCR4_EL1, 2, 0, 0, 4, 7) =20 -DEF_SYSREG(HV_SYS_REG_DBGBVR5_EL1, 0, 5, 2, 0, 4) -DEF_SYSREG(HV_SYS_REG_DBGBCR5_EL1, 0, 5, 2, 0, 5) -DEF_SYSREG(HV_SYS_REG_DBGWVR5_EL1, 0, 5, 2, 0, 6) -DEF_SYSREG(HV_SYS_REG_DBGWCR5_EL1, 0, 5, 2, 0, 7) +DEF_SYSREG(HV_SYS_REG_DBGBVR5_EL1, 2, 0, 0, 5, 4) +DEF_SYSREG(HV_SYS_REG_DBGBCR5_EL1, 2, 0, 0, 5, 5) +DEF_SYSREG(HV_SYS_REG_DBGWVR5_EL1, 2, 0, 0, 5, 6) +DEF_SYSREG(HV_SYS_REG_DBGWCR5_EL1, 2, 0, 0, 5, 7) =20 -DEF_SYSREG(HV_SYS_REG_DBGBVR6_EL1, 0, 6, 2, 0, 4) -DEF_SYSREG(HV_SYS_REG_DBGBCR6_EL1, 0, 6, 2, 0, 5) -DEF_SYSREG(HV_SYS_REG_DBGWVR6_EL1, 0, 6, 2, 0, 6) -DEF_SYSREG(HV_SYS_REG_DBGWCR6_EL1, 0, 6, 2, 0, 7) +DEF_SYSREG(HV_SYS_REG_DBGBVR6_EL1, 2, 0, 0, 6, 4) +DEF_SYSREG(HV_SYS_REG_DBGBCR6_EL1, 2, 0, 0, 6, 5) +DEF_SYSREG(HV_SYS_REG_DBGWVR6_EL1, 2, 0, 0, 6, 6) +DEF_SYSREG(HV_SYS_REG_DBGWCR6_EL1, 2, 0, 0, 6, 7) =20 -DEF_SYSREG(HV_SYS_REG_DBGBVR7_EL1, 0, 7, 2, 0, 4) -DEF_SYSREG(HV_SYS_REG_DBGBCR7_EL1, 0, 7, 2, 0, 5) -DEF_SYSREG(HV_SYS_REG_DBGWVR7_EL1, 0, 7, 2, 0, 6) -DEF_SYSREG(HV_SYS_REG_DBGWCR7_EL1, 0, 7, 2, 0, 7) +DEF_SYSREG(HV_SYS_REG_DBGBVR7_EL1, 2, 0, 0, 7, 4) +DEF_SYSREG(HV_SYS_REG_DBGBCR7_EL1, 2, 0, 0, 7, 5) +DEF_SYSREG(HV_SYS_REG_DBGWVR7_EL1, 2, 0, 0, 7, 6) +DEF_SYSREG(HV_SYS_REG_DBGWCR7_EL1, 2, 0, 0, 7, 7) =20 -DEF_SYSREG(HV_SYS_REG_DBGBVR8_EL1, 0, 8, 2, 0, 4) -DEF_SYSREG(HV_SYS_REG_DBGBCR8_EL1, 0, 8, 2, 0, 5) -DEF_SYSREG(HV_SYS_REG_DBGWVR8_EL1, 0, 8, 2, 0, 6) -DEF_SYSREG(HV_SYS_REG_DBGWCR8_EL1, 0, 8, 2, 0, 7) +DEF_SYSREG(HV_SYS_REG_DBGBVR8_EL1, 2, 0, 0, 8, 4) +DEF_SYSREG(HV_SYS_REG_DBGBCR8_EL1, 2, 0, 0, 8, 5) +DEF_SYSREG(HV_SYS_REG_DBGWVR8_EL1, 2, 0, 0, 8, 6) +DEF_SYSREG(HV_SYS_REG_DBGWCR8_EL1, 2, 0, 0, 8, 7) =20 -DEF_SYSREG(HV_SYS_REG_DBGBVR9_EL1, 0, 9, 2, 0, 4) -DEF_SYSREG(HV_SYS_REG_DBGBCR9_EL1, 0, 9, 2, 0, 5) -DEF_SYSREG(HV_SYS_REG_DBGWVR9_EL1, 0, 9, 2, 0, 6) -DEF_SYSREG(HV_SYS_REG_DBGWCR9_EL1, 0, 9, 2, 0, 7) +DEF_SYSREG(HV_SYS_REG_DBGBVR9_EL1, 2, 0, 0, 9, 4) +DEF_SYSREG(HV_SYS_REG_DBGBCR9_EL1, 2, 0, 0, 9, 5) +DEF_SYSREG(HV_SYS_REG_DBGWVR9_EL1, 2, 0, 0, 9, 6) +DEF_SYSREG(HV_SYS_REG_DBGWCR9_EL1, 2, 0, 0, 9, 7) =20 -DEF_SYSREG(HV_SYS_REG_DBGBVR10_EL1, 0, 10, 2, 0, 4) -DEF_SYSREG(HV_SYS_REG_DBGBCR10_EL1, 0, 10, 2, 0, 5) -DEF_SYSREG(HV_SYS_REG_DBGWVR10_EL1, 0, 10, 2, 0, 6) -DEF_SYSREG(HV_SYS_REG_DBGWCR10_EL1, 0, 10, 2, 0, 7) +DEF_SYSREG(HV_SYS_REG_DBGBVR10_EL1, 2, 0, 0, 10, 4) +DEF_SYSREG(HV_SYS_REG_DBGBCR10_EL1, 2, 0, 0, 10, 5) +DEF_SYSREG(HV_SYS_REG_DBGWVR10_EL1, 2, 0, 0, 10, 6) +DEF_SYSREG(HV_SYS_REG_DBGWCR10_EL1, 2, 0, 0, 10, 7) =20 -DEF_SYSREG(HV_SYS_REG_DBGBVR11_EL1, 0, 11, 2, 0, 4) -DEF_SYSREG(HV_SYS_REG_DBGBCR11_EL1, 0, 11, 2, 0, 5) -DEF_SYSREG(HV_SYS_REG_DBGWVR11_EL1, 0, 11, 2, 0, 6) -DEF_SYSREG(HV_SYS_REG_DBGWCR11_EL1, 0, 11, 2, 0, 7) +DEF_SYSREG(HV_SYS_REG_DBGBVR11_EL1, 2, 0, 0, 11, 4) +DEF_SYSREG(HV_SYS_REG_DBGBCR11_EL1, 2, 0, 0, 11, 5) +DEF_SYSREG(HV_SYS_REG_DBGWVR11_EL1, 2, 0, 0, 11, 6) +DEF_SYSREG(HV_SYS_REG_DBGWCR11_EL1, 2, 0, 0, 11, 7) =20 -DEF_SYSREG(HV_SYS_REG_DBGBVR12_EL1, 0, 12, 2, 0, 4) -DEF_SYSREG(HV_SYS_REG_DBGBCR12_EL1, 0, 12, 2, 0, 5) -DEF_SYSREG(HV_SYS_REG_DBGWVR12_EL1, 0, 12, 2, 0, 6) -DEF_SYSREG(HV_SYS_REG_DBGWCR12_EL1, 0, 12, 2, 0, 7) +DEF_SYSREG(HV_SYS_REG_DBGBVR12_EL1, 2, 0, 0, 12, 4) +DEF_SYSREG(HV_SYS_REG_DBGBCR12_EL1, 2, 0, 0, 12, 5) +DEF_SYSREG(HV_SYS_REG_DBGWVR12_EL1, 2, 0, 0, 12, 6) +DEF_SYSREG(HV_SYS_REG_DBGWCR12_EL1, 2, 0, 0, 12, 7) =20 -DEF_SYSREG(HV_SYS_REG_DBGBVR13_EL1, 0, 13, 2, 0, 4) -DEF_SYSREG(HV_SYS_REG_DBGBCR13_EL1, 0, 13, 2, 0, 5) -DEF_SYSREG(HV_SYS_REG_DBGWVR13_EL1, 0, 13, 2, 0, 6) -DEF_SYSREG(HV_SYS_REG_DBGWCR13_EL1, 0, 13, 2, 0, 7) +DEF_SYSREG(HV_SYS_REG_DBGBVR13_EL1, 2, 0, 0, 13, 4) +DEF_SYSREG(HV_SYS_REG_DBGBCR13_EL1, 2, 0, 0, 13, 5) +DEF_SYSREG(HV_SYS_REG_DBGWVR13_EL1, 2, 0, 0, 13, 6) +DEF_SYSREG(HV_SYS_REG_DBGWCR13_EL1, 2, 0, 0, 13, 7) =20 -DEF_SYSREG(HV_SYS_REG_DBGBVR14_EL1, 0, 14, 2, 0, 4) -DEF_SYSREG(HV_SYS_REG_DBGBCR14_EL1, 0, 14, 2, 0, 5) -DEF_SYSREG(HV_SYS_REG_DBGWVR14_EL1, 0, 14, 2, 0, 6) -DEF_SYSREG(HV_SYS_REG_DBGWCR14_EL1, 0, 14, 2, 0, 7) +DEF_SYSREG(HV_SYS_REG_DBGBVR14_EL1, 2, 0, 0, 14, 4) +DEF_SYSREG(HV_SYS_REG_DBGBCR14_EL1, 2, 0, 0, 14, 5) +DEF_SYSREG(HV_SYS_REG_DBGWVR14_EL1, 2, 0, 0, 14, 6) +DEF_SYSREG(HV_SYS_REG_DBGWCR14_EL1, 2, 0, 0, 14, 7) =20 -DEF_SYSREG(HV_SYS_REG_DBGBVR15_EL1, 0, 15, 2, 0, 4) -DEF_SYSREG(HV_SYS_REG_DBGBCR15_EL1, 0, 15, 2, 0, 5) -DEF_SYSREG(HV_SYS_REG_DBGWVR15_EL1, 0, 15, 2, 0, 6) -DEF_SYSREG(HV_SYS_REG_DBGWCR15_EL1, 0, 15, 2, 0, 7) +DEF_SYSREG(HV_SYS_REG_DBGBVR15_EL1, 2, 0, 0, 15, 4) +DEF_SYSREG(HV_SYS_REG_DBGBCR15_EL1, 2, 0, 0, 15, 5) +DEF_SYSREG(HV_SYS_REG_DBGWVR15_EL1, 2, 0, 0, 15, 6) +DEF_SYSREG(HV_SYS_REG_DBGWCR15_EL1, 2, 0, 0, 15, 7) =20 #ifdef SYNC_NO_RAW_REGS /* * The registers below are manually synced on init because they are * marked as NO_RAW. We still list them to make number space sync easier. */ -DEF_SYSREG(HV_SYS_REG_MDCCINT_EL1, 0, 2, 2, 0, 0) -DEF_SYSREG(HV_SYS_REG_MIDR_EL1, 0, 0, 3, 0, 0) -DEF_SYSREG(HV_SYS_REG_MPIDR_EL1, 0, 0, 3, 0, 5) -DEF_SYSREG(HV_SYS_REG_ID_AA64PFR0_EL1, 0, 4, 3, 0, 0) +DEF_SYSREG(HV_SYS_REG_MDCCINT_EL1, 2, 0, 0, 2, 0) +DEF_SYSREG(HV_SYS_REG_MIDR_EL1, 3, 0, 0, 0, 0) +DEF_SYSREG(HV_SYS_REG_MPIDR_EL1, 3, 0, 0, 0, 5) +DEF_SYSREG(HV_SYS_REG_ID_AA64PFR0_EL1, 3, 0, 0, 4, 0) #endif =20 -DEF_SYSREG(HV_SYS_REG_ID_AA64PFR1_EL1, 0, 4, 3, 0, 1) -DEF_SYSREG(HV_SYS_REG_ID_AA64DFR0_EL1, 0, 5, 3, 0, 0) -DEF_SYSREG(HV_SYS_REG_ID_AA64DFR1_EL1, 0, 5, 3, 0, 1) -DEF_SYSREG(HV_SYS_REG_ID_AA64ISAR0_EL1, 0, 6, 3, 0, 0) -DEF_SYSREG(HV_SYS_REG_ID_AA64ISAR1_EL1, 0, 6, 3, 0, 1) +DEF_SYSREG(HV_SYS_REG_ID_AA64PFR1_EL1, 3, 0, 0, 4, 1) +DEF_SYSREG(HV_SYS_REG_ID_AA64DFR0_EL1, 3, 0, 0, 5, 0) +DEF_SYSREG(HV_SYS_REG_ID_AA64DFR1_EL1, 3, 0, 0, 5, 1) +DEF_SYSREG(HV_SYS_REG_ID_AA64ISAR0_EL1, 3, 0, 0, 6, 0) +DEF_SYSREG(HV_SYS_REG_ID_AA64ISAR1_EL1, 3, 0, 0, 6, 1) =20 #ifdef SYNC_NO_MMFR0 /* We keep the hardware MMFR0 around. HW limits are there anyway */ -DEF_SYSREG(HV_SYS_REG_ID_AA64MMFR0_EL1, 0, 7, 3, 0, 0) +DEF_SYSREG(HV_SYS_REG_ID_AA64MMFR0_EL1, 3, 0, 0, 7, 0) #endif =20 -DEF_SYSREG(HV_SYS_REG_ID_AA64MMFR1_EL1, 0, 7, 3, 0, 1) -DEF_SYSREG(HV_SYS_REG_ID_AA64MMFR2_EL1, 0, 7, 3, 0, 2) +DEF_SYSREG(HV_SYS_REG_ID_AA64MMFR1_EL1, 3, 0, 0, 7, 1) +DEF_SYSREG(HV_SYS_REG_ID_AA64MMFR2_EL1, 3, 0, 0, 7, 2) /* Add ID_AA64MMFR3_EL1 here when HVF supports it */ =20 -DEF_SYSREG(HV_SYS_REG_MDSCR_EL1, 0, 2, 2, 0, 2) -DEF_SYSREG(HV_SYS_REG_SCTLR_EL1, 1, 0, 3, 0, 0) -DEF_SYSREG(HV_SYS_REG_CPACR_EL1, 1, 0, 3, 0, 2) -DEF_SYSREG(HV_SYS_REG_TTBR0_EL1, 2, 0, 3, 0, 0) -DEF_SYSREG(HV_SYS_REG_TTBR1_EL1, 2, 0, 3, 0, 1) -DEF_SYSREG(HV_SYS_REG_TCR_EL1, 2, 0, 3, 0, 2) +DEF_SYSREG(HV_SYS_REG_MDSCR_EL1, 2, 0, 0, 2, 2) +DEF_SYSREG(HV_SYS_REG_SCTLR_EL1, 3, 0, 1, 0, 0) +DEF_SYSREG(HV_SYS_REG_CPACR_EL1, 3, 0, 1, 0, 2) +DEF_SYSREG(HV_SYS_REG_TTBR0_EL1, 3, 0, 2, 0, 0) +DEF_SYSREG(HV_SYS_REG_TTBR1_EL1, 3, 0, 2, 0, 1) +DEF_SYSREG(HV_SYS_REG_TCR_EL1, 3, 0, 2, 0, 2) =20 -DEF_SYSREG(HV_SYS_REG_APIAKEYLO_EL1, 2, 1, 3, 0, 0) -DEF_SYSREG(HV_SYS_REG_APIAKEYHI_EL1, 2, 1, 3, 0, 1) -DEF_SYSREG(HV_SYS_REG_APIBKEYLO_EL1, 2, 1, 3, 0, 2) -DEF_SYSREG(HV_SYS_REG_APIBKEYHI_EL1, 2, 1, 3, 0, 3) -DEF_SYSREG(HV_SYS_REG_APDAKEYLO_EL1, 2, 2, 3, 0, 0) -DEF_SYSREG(HV_SYS_REG_APDAKEYHI_EL1, 2, 2, 3, 0, 1) -DEF_SYSREG(HV_SYS_REG_APDBKEYLO_EL1, 2, 2, 3, 0, 2) -DEF_SYSREG(HV_SYS_REG_APDBKEYHI_EL1, 2, 2, 3, 0, 3) -DEF_SYSREG(HV_SYS_REG_APGAKEYLO_EL1, 2, 3, 3, 0, 0) -DEF_SYSREG(HV_SYS_REG_APGAKEYHI_EL1, 2, 3, 3, 0, 1) +DEF_SYSREG(HV_SYS_REG_APIAKEYLO_EL1, 3, 0, 2, 1, 0) +DEF_SYSREG(HV_SYS_REG_APIAKEYHI_EL1, 3, 0, 2, 1, 1) +DEF_SYSREG(HV_SYS_REG_APIBKEYLO_EL1, 3, 0, 2, 1, 2) +DEF_SYSREG(HV_SYS_REG_APIBKEYHI_EL1, 3, 0, 2, 1, 3) +DEF_SYSREG(HV_SYS_REG_APDAKEYLO_EL1, 3, 0, 2, 2, 0) +DEF_SYSREG(HV_SYS_REG_APDAKEYHI_EL1, 3, 0, 2, 2, 1) +DEF_SYSREG(HV_SYS_REG_APDBKEYLO_EL1, 3, 0, 2, 2, 2) +DEF_SYSREG(HV_SYS_REG_APDBKEYHI_EL1, 3, 0, 2, 2, 3) +DEF_SYSREG(HV_SYS_REG_APGAKEYLO_EL1, 3, 0, 2, 3, 0) +DEF_SYSREG(HV_SYS_REG_APGAKEYHI_EL1, 3, 0, 2, 3, 1) =20 -DEF_SYSREG(HV_SYS_REG_SPSR_EL1, 4, 0, 3, 0, 0) -DEF_SYSREG(HV_SYS_REG_ELR_EL1, 4, 0, 3, 0, 1) -DEF_SYSREG(HV_SYS_REG_SP_EL0, 4, 1, 3, 0, 0) -DEF_SYSREG(HV_SYS_REG_AFSR0_EL1, 5, 1, 3, 0, 0) -DEF_SYSREG(HV_SYS_REG_AFSR1_EL1, 5, 1, 3, 0, 1) -DEF_SYSREG(HV_SYS_REG_ESR_EL1, 5, 2, 3, 0, 0) -DEF_SYSREG(HV_SYS_REG_FAR_EL1, 6, 0, 3, 0, 0) -DEF_SYSREG(HV_SYS_REG_PAR_EL1, 7, 4, 3, 0, 0) -DEF_SYSREG(HV_SYS_REG_MAIR_EL1, 10, 2, 3, 0, 0) -DEF_SYSREG(HV_SYS_REG_AMAIR_EL1, 10, 3, 3, 0, 0) -DEF_SYSREG(HV_SYS_REG_VBAR_EL1, 12, 0, 3, 0, 0) -DEF_SYSREG(HV_SYS_REG_CONTEXTIDR_EL1, 13, 0, 3, 0, 1) -DEF_SYSREG(HV_SYS_REG_TPIDR_EL1, 13, 0, 3, 0, 4) -DEF_SYSREG(HV_SYS_REG_CNTKCTL_EL1, 14, 1, 3, 0, 0) -DEF_SYSREG(HV_SYS_REG_CSSELR_EL1, 0, 0, 3, 2, 0) -DEF_SYSREG(HV_SYS_REG_TPIDR_EL0, 13, 0, 3, 3, 2) -DEF_SYSREG(HV_SYS_REG_TPIDRRO_EL0, 13, 0, 3, 3, 3) -DEF_SYSREG(HV_SYS_REG_CNTV_CTL_EL0, 14, 3, 3, 3, 1) -DEF_SYSREG(HV_SYS_REG_CNTV_CVAL_EL0, 14, 3, 3, 3, 2) -DEF_SYSREG(HV_SYS_REG_SP_EL1, 4, 1, 3, 4, 0) +DEF_SYSREG(HV_SYS_REG_SPSR_EL1, 3, 0, 4, 0, 0) +DEF_SYSREG(HV_SYS_REG_ELR_EL1, 3, 0, 4, 0, 1) +DEF_SYSREG(HV_SYS_REG_SP_EL0, 3, 0, 4, 1, 0) +DEF_SYSREG(HV_SYS_REG_AFSR0_EL1, 3, 0, 5, 1, 0) +DEF_SYSREG(HV_SYS_REG_AFSR1_EL1, 3, 0, 5, 1, 1) +DEF_SYSREG(HV_SYS_REG_ESR_EL1, 3, 0, 5, 2, 0) +DEF_SYSREG(HV_SYS_REG_FAR_EL1, 3, 0, 6, 0, 0) +DEF_SYSREG(HV_SYS_REG_PAR_EL1, 3, 0, 7, 4, 0) +DEF_SYSREG(HV_SYS_REG_MAIR_EL1, 3, 0, 10, 2, 0) +DEF_SYSREG(HV_SYS_REG_AMAIR_EL1, 3, 0, 10, 3, 0) +DEF_SYSREG(HV_SYS_REG_VBAR_EL1, 3, 0, 12, 0, 0) +DEF_SYSREG(HV_SYS_REG_CONTEXTIDR_EL1, 3, 0, 13, 0, 1) +DEF_SYSREG(HV_SYS_REG_TPIDR_EL1, 3, 0, 13, 0, 4) +DEF_SYSREG(HV_SYS_REG_CNTKCTL_EL1, 3, 0, 14, 1, 0) +DEF_SYSREG(HV_SYS_REG_CSSELR_EL1, 3, 2, 0, 0, 0) +DEF_SYSREG(HV_SYS_REG_TPIDR_EL0, 3, 3, 13, 0, 2) +DEF_SYSREG(HV_SYS_REG_TPIDRRO_EL0, 3, 3, 13, 0, 3) +DEF_SYSREG(HV_SYS_REG_CNTV_CTL_EL0, 3, 3, 14, 3, 1) +DEF_SYSREG(HV_SYS_REG_CNTV_CVAL_EL0, 3, 3, 14, 3, 2) +DEF_SYSREG(HV_SYS_REG_SP_EL1, 3, 4, 4, 1, 0) --=20 2.43.0 From nobody Sun Sep 28 15:26:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-410f2007372sm6338315f8f.16.2025.09.26.07.08.53 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Sep 2025 07:08:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758895734; x=1759500534; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=XeUKkMJnd9x6RuIEqbezgHWnfk6CHPapq1x+ZqRbw18=; b=PTDmU8lbmJ5ZAbhP2OeoAK2K5ZFBaKGwy7PtmuucPKagJ9GGvZL1O9gThHh8TZMUSQ tIwmReYjyj8qDPlmBpTXnEZKAzSdzLlPlPSgt2AaCYKIhEvTdLQI51O75Y31QE+oD2bx 8EY/3rQAavQHlcPD3HgW+j0I5Dk9dxEf0Sa13JsHgt7uxRVYBQGOVPSkYKaPEO9/8Gnp bwLEr7lRXDNTRnpqDki3UCDtQEEmt5j6jbcH/NxfCRvTiC77SWC+CmUtOh8w552KQ0rT +LCe8ssdlOiPraLWXbRWKBpueESjXPfGMs8mXWXDqyJ/ws9geITfs6xqR5ulzzGvjQh4 xFBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758895734; x=1759500534; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XeUKkMJnd9x6RuIEqbezgHWnfk6CHPapq1x+ZqRbw18=; b=ApBdLEiPfRR8IYxonDch2R8MFhc9YQubL9FiwpkWMzM4HE0YHx1ZIw4fq2/8idgBU3 B4gM/ZZzzCLSsRFuYJ2R1E/Yvht/yqlKN4Ujsgq4NXYRWbI/PT/VruRc9TIe5zcjeRE4 WLtARRkD1/RfBIqZ6+sZeIWB2AM7JSXns514KFjz+6uaqah5LRAKn73C3+0jr3rddA3l K9MIgm4gnnVsKf1K/OuT+dOoMMbWPQk4FM0/cHxXDaZLX01hy/PBfw+dZe2FiO0drpJ/ y3kvPtXGw7Q4D6ZmIzDnhlvi2VR5Apok1KwdqL6NFp6kgPy0+7gED6wVfTzDsslqy4eb FVFw== X-Gm-Message-State: AOJu0YyOzaokYfVW0FlPItP2K3CJh8qABQCvVwJhElkF+vjM4M8oHRoE XxGz1pPKnDo+ycfFla39rQpLGziN3QS7W11hO/FelPbTayRG/8yNT3dh+rLf6FYMwWkrjAvaL5J T4WTQ X-Gm-Gg: ASbGncsjIPqbu/e4Dy4N8nenSqEGPjfx+ZFXcX7iDNVlAi2bIftxY43QrtgET1S9Nbg JQDOp7LwKqyw+mfOteQ2pcGO6KtR4PM/5YsFT3sbaZfUu62BZ89J+HOeEcIazetZh9o3mUgeeMc o37RH5CLNNfddZg8n3ammhyPLvWEED+kMEO2wjVhQ8ejtUS8O0urtMN7Ap8T3Y33jP4u9bzSinM P+KmovYtWleyV0QcIUICOjGrybukYILky8szKs7KfX4uRZEgxUgJHxwk7jutiSZ9UAX5D1QB8BT l6FHAjl4HpM+W36sKqEpHvyye9rbwEOxMdViakTklIwRwsysJoR/tTXxx8IX7vFvgdtBSiiLYc/ 5D0Ax5x9X0Bqo29OxJVxVLfb7+qIl X-Google-Smtp-Source: AGHT+IGF+DW7G9VqR5kXo3kmCyj0Wu4QklrJxmwsdpbD8Xwp0R4zHZK0m0xDG0F4pU5oX1uKwPRvxQ== X-Received: by 2002:a05:6000:2c10:b0:3d9:7021:fff0 with SMTP id ffacd0b85a97d-40e4adce713mr6517541f8f.37.1758895734395; Fri, 26 Sep 2025 07:08:54 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/44] target/arm/hvf: Add KVMID_TO_HVF, HVF_TO_KVMID Date: Fri, 26 Sep 2025 15:08:07 +0100 Message-ID: <20250926140844.1493020-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250926140844.1493020-1-peter.maydell@linaro.org> References: <20250926140844.1493020-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758895841852116600 From: Richard Henderson Conversion between KVM system registers ids and the HVF system register ids is trivial. Reviewed-by: Manos Pitsidianakis Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- target/arm/hvf/hvf.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index f68924ba1f3..7515e59c56d 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -403,6 +403,26 @@ struct hvf_sreg_match { uint32_t cp_idx; }; =20 +/* + * QEMU uses KVM system register ids in the migration format. + * Conveniently, HVF uses the same encoding of the op* and cr* parameters + * within the low 16 bits of the ids. Thus conversion between the + * formats is trivial. + */ + +#define KVMID_TO_HVF(KVM) ((KVM) & 0xffff) +#define HVF_TO_KVMID(HVF) \ + (CP_REG_ARM64 | CP_REG_SIZE_U64 | CP_REG_ARM64_SYSREG | (HVF)) + +/* Verify this at compile-time. */ + +#define DEF_SYSREG(HVF_ID, ...) \ + QEMU_BUILD_BUG_ON(HVF_ID !=3D KVMID_TO_HVF(KVMID_AA64_SYS_REG64(__VA_ARG= S__))); + +#include "sysreg.c.inc" + +#undef DEF_SYSREG + #define DEF_SYSREG(HVF_ID, op0, op1, crn, crm, op2) \ { HVF_ID, HVF_SYSREG(crn, crm, op0, op1, op2) }, =20 --=20 2.43.0 From nobody Sun Sep 28 15:26:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758896385; cv=none; d=zohomail.com; s=zohoarc; b=YNYfLwgsC+u4ESVv94orOx6rcq8XsfA+2Jx2dOHDg/FoaJzR49cXMDalw7z4Yz/Hy/V8jPjYJLS1FsBcgXwqPXUobNJH/wLr4uwv6slFgLZd/LIq/JEh5JD08Hy9JX5JJ0wbwuN88HOSzI+e9TCa9z7+spbr1hIBjWTpn+5bVAU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758896385; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=cBibtUZWXpQ+45X6TP72VZdFkcxeDblm6hizC7gDVac=; b=IBfn4U3L85GvG3Fj2/lVkaV27aNn2yfxcNHoKktHTB74hjg41vTtlPpfdaQCi2bl0/ZKE/5HGVpODOJpHK+nDhCaD5lrg5/A4gKt5jGWS6Z4XsNqoj8nTRy0GmEWk8XMCU5EKW0/5gfUxUgN3YklnVdMfNKkU43gcy104nlKKlU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1758896384804808.4658797427384; Fri, 26 Sep 2025 07:19:44 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v298l-0007cw-K0; Fri, 26 Sep 2025 10:09:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v298N-0007CJ-TI for qemu-devel@nongnu.org; Fri, 26 Sep 2025 10:09:16 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1v2988-0005eF-OC for qemu-devel@nongnu.org; Fri, 26 Sep 2025 10:09:13 -0400 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-46de78b595dso11290045e9.1 for ; Fri, 26 Sep 2025 07:08:57 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-410f2007372sm6338315f8f.16.2025.09.26.07.08.54 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Sep 2025 07:08:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758895735; x=1759500535; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=cBibtUZWXpQ+45X6TP72VZdFkcxeDblm6hizC7gDVac=; b=ZuFBLVRJ04lKbZupy7u7kWpU1vmv9ECRIkJPmkCy8CQEEOkC2wn7Esg3SkmiLrm5rs Vn1hN3+ISdxaOd2BvbolH1Osj8QBQxq22ieIgCQGKmABK692dy5rYUhCX3Qi5TgVwnuc D+Pu9DbnWIQrGXhX1QbgXV3NoMy1voja5yMnfBrb9uIgNpIOPcKBrbibvKLajGqVzMpQ ldPHKI7TgWHqd4qOi89o+AHzoX55ECcKwBw1rpfOfpSUz3Rj3B4q4CQaVVMj2N0om1uI SYdSsGRoQZKwGAa/yR9ykBjVJaSjrbsL831L4a0evtS1q4wjwWuC0aHFfyNNhr4WNTJJ tkzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758895735; x=1759500535; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cBibtUZWXpQ+45X6TP72VZdFkcxeDblm6hizC7gDVac=; b=htVXmv2vECODrRJNCbTT5ygcc0gCBcFk5qVtANGDKPK/ObRpengjlFlMC6iy69RLTQ 1DMSbrVe9dXShbq/jAEG9laDRTJGJxt7B00te0wO5qYR1+ooSPILkYGweB0fn43N/rzt cFW3LzuWeMVqy2mKYVW0twfrBEPQZJCNRgm956Cl+tHq7y4nn9AriLh0g0eDg9QXIXbf qQ2NXJERu4ejxURgFkMjbJCEEEDy7d/zbdfpoz6K87PTanubr1MRcfqk13e94rQS8N9E 6uUQxcXbPvfRVmq2t3ZtZp6OMawkjmfrvBam6RGvBfs/E6iV7wwQyGGY0Cq8VDMQQctd ed6w== X-Gm-Message-State: AOJu0YyEtpCh2rC5zDYTTbzn1WFY3RWGMXJq6XjB34XQERC8f6HKY/nX k2WDlkaLb+hWXkegNA7Blkr338H2wiNQkTGkg+U2O/yDp+mklHb4Oy6+RINuRPM2GYGYXhZiPo7 +Fqk6 X-Gm-Gg: ASbGncullZPdvba4izGPSccYb4e9xQjgdIsnjqqJkRk83EjVKSLGHL8ZN8P0Ycz2dNS JSb2Pyezy/p4JgAp9M9Uj8BwYGIdkC8yTiU6J8XRVhmeHUovDYRprBHQi481Ya7p50STXwLygxf gxPMFE7fQ0iCpCjT0Eh6Cwsmwks1ZKDImYqJyoeuetyCGnCZmNoP+swwMYoa8z/7//2ZsihXmjC m679++/QBQ2S044IDw77SEzFU1Q0VyZcwu5hCaNSSZZEtsIcMNVm3Kdp+rgWnsOTzhYFaT6Bds0 fj7v4fs5GOcuZlhbTHpCnYAxUFyYnmDihwq8T7Pa6L0X6anBbL0em5WEZluANg/OsOizCwMfyi9 9o8HjbLBLMVgM0MHGtlylUVNSgAUl X-Google-Smtp-Source: AGHT+IE5ziMkQkxF6U9OUEMoCijHZ4GRovQcdg0TfIc9wZPHA8C5HJD578toBMsFfq9QsurmX1L1pw== X-Received: by 2002:a05:600c:19c9:b0:46e:3700:67b1 with SMTP id 5b1f17b1804b1-46e37006e40mr52640145e9.4.1758895735298; Fri, 26 Sep 2025 07:08:55 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/44] target/arm/hvf: Remove hvf_sreg_match.key Date: Fri, 26 Sep 2025 15:08:08 +0100 Message-ID: <20250926140844.1493020-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250926140844.1493020-1-peter.maydell@linaro.org> References: <20250926140844.1493020-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758896386768116600 From: Richard Henderson Use conversion functions instead of table lookup. Reviewed-by: Manos Pitsidianakis Signed-off-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- target/arm/hvf/hvf.c | 35 +++++++++++++++++++---------------- 1 file changed, 19 insertions(+), 16 deletions(-) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 7515e59c56d..98f49ce33a4 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -152,9 +152,6 @@ void hvf_arm_init_debug(void) g_array_sized_new(true, true, sizeof(HWWatchpoint), max_hw_wps); } =20 -#define HVF_SYSREG(crn, crm, op0, op1, op2) \ - ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2) - #define SYSREG_OP0_SHIFT 20 #define SYSREG_OP0_MASK 0x3 #define SYSREG_OP0(sysreg) ((sysreg >> SYSREG_OP0_SHIFT) & SYSREG_OP0_M= ASK) @@ -399,7 +396,6 @@ static const struct hvf_reg_match hvf_fpreg_match[] =3D= { =20 struct hvf_sreg_match { int reg; - uint32_t key; uint32_t cp_idx; }; =20 @@ -423,8 +419,7 @@ struct hvf_sreg_match { =20 #undef DEF_SYSREG =20 -#define DEF_SYSREG(HVF_ID, op0, op1, crn, crm, op2) \ - { HVF_ID, HVF_SYSREG(crn, crm, op0, op1, op2) }, +#define DEF_SYSREG(HVF_ID, op0, op1, crn, crm, op2) { HVF_ID }, =20 static struct hvf_sreg_match hvf_sreg_match[] =3D { #include "sysreg.c.inc" @@ -469,13 +464,16 @@ int hvf_get_registers(CPUState *cpu) pstate_write(env, val); =20 for (i =3D 0; i < ARRAY_SIZE(hvf_sreg_match); i++) { + int hvf_id =3D hvf_sreg_match[i].reg; + uint64_t kvm_id =3D HVF_TO_KVMID(hvf_id); + if (hvf_sreg_match[i].cp_idx =3D=3D -1) { continue; } =20 if (cpu->accel->guest_debug_enabled) { /* Handle debug registers */ - switch (hvf_sreg_match[i].reg) { + switch (hvf_id) { case HV_SYS_REG_DBGBVR0_EL1: case HV_SYS_REG_DBGBCR0_EL1: case HV_SYS_REG_DBGWVR0_EL1: @@ -549,8 +547,10 @@ int hvf_get_registers(CPUState *cpu) * vCPU but simply keep the values from the previous * environment. */ - const ARMCPRegInfo *ri; - ri =3D get_arm_cp_reginfo(arm_cpu->cp_regs, hvf_sreg_match= [i].key); + uint32_t key =3D kvm_to_cpreg_id(kvm_id); + const ARMCPRegInfo *ri =3D + get_arm_cp_reginfo(arm_cpu->cp_regs, key); + val =3D read_raw_cp_reg(env, ri); =20 arm_cpu->cpreg_values[hvf_sreg_match[i].cp_idx] =3D val; @@ -559,7 +559,7 @@ int hvf_get_registers(CPUState *cpu) } } =20 - ret =3D hv_vcpu_get_sys_reg(cpu->accel->fd, hvf_sreg_match[i].reg,= &val); + ret =3D hv_vcpu_get_sys_reg(cpu->accel->fd, hvf_id, &val); assert_hvf_ok(ret); =20 arm_cpu->cpreg_values[hvf_sreg_match[i].cp_idx] =3D val; @@ -606,13 +606,15 @@ int hvf_put_registers(CPUState *cpu) =20 assert(write_cpustate_to_list(arm_cpu, false)); for (i =3D 0; i < ARRAY_SIZE(hvf_sreg_match); i++) { + int hvf_id =3D hvf_sreg_match[i].reg; + if (hvf_sreg_match[i].cp_idx =3D=3D -1) { continue; } =20 if (cpu->accel->guest_debug_enabled) { /* Handle debug registers */ - switch (hvf_sreg_match[i].reg) { + switch (hvf_id) { case HV_SYS_REG_DBGBVR0_EL1: case HV_SYS_REG_DBGBCR0_EL1: case HV_SYS_REG_DBGWVR0_EL1: @@ -687,7 +689,7 @@ int hvf_put_registers(CPUState *cpu) } =20 val =3D arm_cpu->cpreg_values[hvf_sreg_match[i].cp_idx]; - ret =3D hv_vcpu_set_sys_reg(cpu->accel->fd, hvf_sreg_match[i].reg,= val); + ret =3D hv_vcpu_set_sys_reg(cpu->accel->fd, hvf_id, val); assert_hvf_ok(ret); } =20 @@ -922,14 +924,15 @@ int hvf_arch_init_vcpu(CPUState *cpu) =20 /* Populate cp list for all known sysregs */ for (i =3D 0; i < sregs_match_len; i++) { - const ARMCPRegInfo *ri; - uint32_t key =3D hvf_sreg_match[i].key; + int hvf_id =3D hvf_sreg_match[i].reg; + uint64_t kvm_id =3D HVF_TO_KVMID(hvf_id); + uint32_t key =3D kvm_to_cpreg_id(kvm_id); + const ARMCPRegInfo *ri =3D get_arm_cp_reginfo(arm_cpu->cp_regs, ke= y); =20 - ri =3D get_arm_cp_reginfo(arm_cpu->cp_regs, key); if (ri) { assert(!(ri->type & ARM_CP_NO_RAW)); hvf_sreg_match[i].cp_idx =3D sregs_cnt; - arm_cpu->cpreg_indexes[sregs_cnt++] =3D cpreg_to_kvm_id(key); + arm_cpu->cpreg_indexes[sregs_cnt++] =3D kvm_id; } else { hvf_sreg_match[i].cp_idx =3D -1; } --=20 2.43.0 From nobody Sun Sep 28 15:26:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758896049; cv=none; d=zohomail.com; s=zohoarc; b=jF8kqhh+qIve6yJD5Ggq5zr/QG5162jAhPC28e/WhTPirrq/Lm979bewegYQojmG2M/8vaUBW3H0xPZAaOCcYuLSs43/NjKm6rbuApDmbSV6Dqj9HrZaeczEZnVMEy/gjx26p985mOr2j7KV26OS/RL+vtczOBUuZdypQCrGlSU= ARC-Message-Signature: i=1; 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This lets us drop the cp_idx member of hvf_sreg_match, which leaves only one member in the struct. Replace the struct with a const array. Instead of int, use the proper enum type: hv_sys_reg_t. Rename from hvf_sreg_match to hvf_sreg_list because there is no longer any matching going on. Signed-off-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- target/arm/hvf/hvf.c | 45 +++++++++++++++----------------------------- 1 file changed, 15 insertions(+), 30 deletions(-) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 98f49ce33a4..b043eac8c62 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -394,11 +394,6 @@ static const struct hvf_reg_match hvf_fpreg_match[] = =3D { { HV_SIMD_FP_REG_Q31, offsetof(CPUARMState, vfp.zregs[31]) }, }; =20 -struct hvf_sreg_match { - int reg; - uint32_t cp_idx; -}; - /* * QEMU uses KVM system register ids in the migration format. * Conveniently, HVF uses the same encoding of the op* and cr* parameters @@ -419,9 +414,9 @@ struct hvf_sreg_match { =20 #undef DEF_SYSREG =20 -#define DEF_SYSREG(HVF_ID, op0, op1, crn, crm, op2) { HVF_ID }, +#define DEF_SYSREG(HVF_ID, op0, op1, crn, crm, op2) HVF_ID, =20 -static struct hvf_sreg_match hvf_sreg_match[] =3D { +static const hv_sys_reg_t hvf_sreg_list[] =3D { #include "sysreg.c.inc" }; =20 @@ -434,7 +429,7 @@ int hvf_get_registers(CPUState *cpu) hv_return_t ret; uint64_t val; hv_simd_fp_uchar16_t fpval; - int i; + int i, n; =20 for (i =3D 0; i < ARRAY_SIZE(hvf_reg_match); i++) { ret =3D hv_vcpu_get_reg(cpu->accel->fd, hvf_reg_match[i].reg, &val= ); @@ -463,13 +458,9 @@ int hvf_get_registers(CPUState *cpu) assert_hvf_ok(ret); pstate_write(env, val); =20 - for (i =3D 0; i < ARRAY_SIZE(hvf_sreg_match); i++) { - int hvf_id =3D hvf_sreg_match[i].reg; - uint64_t kvm_id =3D HVF_TO_KVMID(hvf_id); - - if (hvf_sreg_match[i].cp_idx =3D=3D -1) { - continue; - } + for (i =3D 0, n =3D arm_cpu->cpreg_array_len; i < n; i++) { + uint64_t kvm_id =3D arm_cpu->cpreg_indexes[i]; + int hvf_id =3D KVMID_TO_HVF(kvm_id); =20 if (cpu->accel->guest_debug_enabled) { /* Handle debug registers */ @@ -553,7 +544,7 @@ int hvf_get_registers(CPUState *cpu) =20 val =3D read_raw_cp_reg(env, ri); =20 - arm_cpu->cpreg_values[hvf_sreg_match[i].cp_idx] =3D val; + arm_cpu->cpreg_values[i] =3D val; continue; } } @@ -562,7 +553,7 @@ int hvf_get_registers(CPUState *cpu) ret =3D hv_vcpu_get_sys_reg(cpu->accel->fd, hvf_id, &val); assert_hvf_ok(ret); =20 - arm_cpu->cpreg_values[hvf_sreg_match[i].cp_idx] =3D val; + arm_cpu->cpreg_values[i] =3D val; } assert(write_list_to_cpustate(arm_cpu)); =20 @@ -578,7 +569,7 @@ int hvf_put_registers(CPUState *cpu) hv_return_t ret; uint64_t val; hv_simd_fp_uchar16_t fpval; - int i; + int i, n; =20 for (i =3D 0; i < ARRAY_SIZE(hvf_reg_match); i++) { val =3D *(uint64_t *)((void *)env + hvf_reg_match[i].offset); @@ -605,12 +596,9 @@ int hvf_put_registers(CPUState *cpu) aarch64_save_sp(env, arm_current_el(env)); =20 assert(write_cpustate_to_list(arm_cpu, false)); - for (i =3D 0; i < ARRAY_SIZE(hvf_sreg_match); i++) { - int hvf_id =3D hvf_sreg_match[i].reg; - - if (hvf_sreg_match[i].cp_idx =3D=3D -1) { - continue; - } + for (i =3D 0, n =3D arm_cpu->cpreg_array_len; i < n; i++) { + uint64_t kvm_id =3D arm_cpu->cpreg_indexes[i]; + int hvf_id =3D KVMID_TO_HVF(kvm_id); =20 if (cpu->accel->guest_debug_enabled) { /* Handle debug registers */ @@ -688,7 +676,7 @@ int hvf_put_registers(CPUState *cpu) } } =20 - val =3D arm_cpu->cpreg_values[hvf_sreg_match[i].cp_idx]; + val =3D arm_cpu->cpreg_values[i]; ret =3D hv_vcpu_set_sys_reg(cpu->accel->fd, hvf_id, val); assert_hvf_ok(ret); } @@ -899,7 +887,7 @@ int hvf_arch_init_vcpu(CPUState *cpu) { ARMCPU *arm_cpu =3D ARM_CPU(cpu); CPUARMState *env =3D &arm_cpu->env; - uint32_t sregs_match_len =3D ARRAY_SIZE(hvf_sreg_match); + uint32_t sregs_match_len =3D ARRAY_SIZE(hvf_sreg_list); uint32_t sregs_cnt =3D 0; uint64_t pfr; hv_return_t ret; @@ -924,17 +912,14 @@ int hvf_arch_init_vcpu(CPUState *cpu) =20 /* Populate cp list for all known sysregs */ for (i =3D 0; i < sregs_match_len; i++) { - int hvf_id =3D hvf_sreg_match[i].reg; + hv_sys_reg_t hvf_id =3D hvf_sreg_list[i]; uint64_t kvm_id =3D HVF_TO_KVMID(hvf_id); uint32_t key =3D kvm_to_cpreg_id(kvm_id); const ARMCPRegInfo *ri =3D get_arm_cp_reginfo(arm_cpu->cp_regs, ke= y); =20 if (ri) { assert(!(ri->type & ARM_CP_NO_RAW)); - hvf_sreg_match[i].cp_idx =3D sregs_cnt; arm_cpu->cpreg_indexes[sregs_cnt++] =3D kvm_id; - } else { - hvf_sreg_match[i].cp_idx =3D -1; } } arm_cpu->cpreg_array_len =3D sregs_cnt; --=20 2.43.0 From nobody Sun Sep 28 15:26:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758896044; cv=none; d=zohomail.com; s=zohoarc; b=a9xenrThfxFJaLMJGqlPWhZhg4AaCMViREhPmfTbH44AFJuMyI9td6tqa3kZ15GdT0JfCxq3+ZWNIuZn0EGVUL5prw7gOIcPfR+NrZqh276e/k8tuK63dNxCGB8VuDF5Q73gmzXY5Iur+XRnO38S2kTGXvQP6zOWCWsO3+dJkko= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758896044; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; 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Fri, 26 Sep 2025 07:08:57 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/44] target/arm/hvf: Sort the cpreg_indexes array Date: Fri, 26 Sep 2025 15:08:10 +0100 Message-ID: <20250926140844.1493020-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250926140844.1493020-1-peter.maydell@linaro.org> References: <20250926140844.1493020-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758896045683116600 From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- target/arm/hvf/hvf.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index b043eac8c62..99d8672b9bc 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -925,6 +925,9 @@ int hvf_arch_init_vcpu(CPUState *cpu) arm_cpu->cpreg_array_len =3D sregs_cnt; arm_cpu->cpreg_vmstate_array_len =3D sregs_cnt; =20 + /* cpreg tuples must be in strictly ascending order */ + qsort(arm_cpu->cpreg_indexes, sregs_cnt, sizeof(uint64_t), compare_u64= ); + assert(write_cpustate_to_list(arm_cpu, false)); =20 /* Set CP_NO_RAW system registers on init */ --=20 2.43.0 From nobody Sun Sep 28 15:26:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758896375; cv=none; d=zohomail.com; s=zohoarc; b=caT+dmpGOWkrdUu9DOS0MCtPOfmsMZXoQLDlGGpD5oxX70NOGwfooRf6lX2XsLJUT2RhmiGS3aNQpQhWlVJxQIx3KPHc2LZfbjIsxsCPUHnmHdTBQtKcAfADqCYo48g1HcbT5q1aGgIYP3vbryBIFlNIfazaDVpa4ilLC9MStOY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758896375; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-410f2007372sm6338315f8f.16.2025.09.26.07.08.57 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Sep 2025 07:08:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758895738; x=1759500538; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=N4ZfhBUIPLSIJELQ+q97VJqf+RX7DXJlqzbKKdi+6D4=; b=Q5WJnyk4uMDG3gtLUI0JxkKLfoIA9Yh5RTC1LFSABDis3f2wERZBYGNwBq5M7kqn7u eO2Fx/ZaxWp/SvOU0oRqr5RAS/RIcXhYM5ip8So6u7PFw+BFIoL6ByQHc2O32cMx3R5n LEo2P640c/gR2E1zSKkrbsLpH23RpCvRv9kJrrdsUd9iowDPzf6baNbXyZJweO2b/hd7 u7JBMG5mN0A2JJFu2KmemsSK1pl3pJTAxoCyrf0CNOQJPN5aTuFkoY8xzQvzzESCN1MY YzClbjyshNSyPkILlq22bMSr1eTIhQ6ES8yVNUQvQQRXGn1gm30v3V2CPKo29snY1Oz7 rJVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758895738; x=1759500538; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=N4ZfhBUIPLSIJELQ+q97VJqf+RX7DXJlqzbKKdi+6D4=; b=bnMCGkrrrftrWCVDRBhTpYvpsFmYp/XleL4IzqNUJv060swdMSkFdy6hN9zViouEY9 6KsqWk1B3DNN416i+H9to05nLcdMBuc1MifY6HYMN6lRQY7MO0OkAAaSjcaIXzi+bipV S603RTabSzFZQqRdnIDkMtC2S6FFwB9f4FlH+rhoKwapwh8U91l1YR2HWJ3DquyAEfJd zF+riJB5GX7yseLvFmiDgTOvD8tFXO0E/FaB1YUdajAMmq6MFii2SksX10+uzEpiLXq+ E8qcCmuYHNdEP9Wddm3MKa7H4OwKZGkaQoIwX+qB4QPxBpo9WJ6N/H760JYL9TGs9nih up7Q== X-Gm-Message-State: AOJu0Yxg/ELsK4e7A/vK/x78eyxzqTnF7eCz+7g/R6f5pnB4FTLoq6EG K+TFDSbM/cxQuWJ991bMQ1ueI/9NBuNM8IXcViJytDJ11BGmMvu6TEgPNzcKysmDa/ntzS6qlyM lS63h X-Gm-Gg: ASbGncuSiHSz8sd8yDY9M8Mr0od1PjXNcCzqEz0hKIoZRQIiqGMnG9fGS7qphsyK6Ni GXFHiAHmpX268xQDiO7by3kb40RoV8xr0uNPbyVf1ODyGmI+5Z1536URvNWqNu51iTgZ8k+qVuc TZeTdMrI9ZaWWo7XWtXhuDnclc9P/dWXHfOlIIjeftgwPhsim3GFP3tm/02mj+6oiGS19onnBO8 wLs+f/cKh7CVH4lYfj+Ic6NvClHOtu8IxhMsusbyy0Rlv7/ap4P0D4SDMZBJ0oyFSkBGX/CPHl1 Fh+i7Iv8c45rEGvb2PtU3C03WuUgFkASLpKnWbMBBiyB9GxVOGllF23loteP5+7TkzT/Wgm6yjw Snqp8/avjEThaUCEKzOlBd5rjbX87 X-Google-Smtp-Source: AGHT+IEe6MTp+lrHL34N62sJ5CYEebmLwasOrj4vHHBELxWo7esdHuDCPKszHCk6rVohTFYQqlnV/w== X-Received: by 2002:a05:6000:288d:b0:3d1:61f0:d26c with SMTP id ffacd0b85a97d-40e4abd7c93mr7112487f8f.54.1758895738175; Fri, 26 Sep 2025 07:08:58 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/44] target/arm/hvf: Use raw_read, raw_write to access Date: Fri, 26 Sep 2025 15:08:11 +0100 Message-ID: <20250926140844.1493020-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250926140844.1493020-1-peter.maydell@linaro.org> References: <20250926140844.1493020-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758896376411116600 From: Richard Henderson Reduce the places that know about field types by 2. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- target/arm/hvf/hvf.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 99d8672b9bc..694584cc130 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -1153,7 +1153,7 @@ static bool hvf_sysreg_read_cp(CPUState *cpu, uint32_= t reg, uint64_t *val) } else if (ri->readfn) { *val =3D ri->readfn(env, ri); } else { - *val =3D CPREG_FIELD64(env, ri); + *val =3D raw_read(env, ri); } trace_hvf_vgic_read(ri->name, *val); return true; @@ -1435,7 +1435,7 @@ static bool hvf_sysreg_write_cp(CPUState *cpu, uint32= _t reg, uint64_t val) if (ri->writefn) { ri->writefn(env, ri, val); } else { - CPREG_FIELD64(env, ri) =3D val; + raw_write(env, ri, val); } =20 trace_hvf_vgic_write(ri->name, val); --=20 2.43.0 From nobody Sun Sep 28 15:26:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758895931; cv=none; d=zohomail.com; s=zohoarc; b=SmdV1iyXzPwnUe0CDEc3kFgdu/quZCX9lXADHtRlub3UvIJ92ZN9++DdWKOyiP/pdYe+E7dE+c7ZmxBiSdpWkEvU1wPNZ++66FU1WHNExh3dwkhSV3rQjIqG4FuDiV/dFdY/JhWt0HUTwkyDqypOV7LaANsH6wJxuH5JAT+MXB8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758895931; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=khGd2vyM0LqffZpI9eeao31QS+mzqXWFdrP3S+/byUk=; b=l7IOo4OeQ0sqIaYToUNQdH1nQrSd6cTUfl+sKuopM2iWEQdmO3VGTw5q/DuOUQp8cTHOOv3p132qDYKR/RIYnbvPA3RJSzUZk+lm5d8ptXK6dKw1BBSagPoXua9U+fMdOgGAly32BpJdwTAV43dnq5ZzjRWnDbosPm3+8CCLFSk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1758895931382338.282699117647; Fri, 26 Sep 2025 07:12:11 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v298Z-0007Sk-I0; Fri, 26 Sep 2025 10:09:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v298T-0007JZ-PY for qemu-devel@nongnu.org; Fri, 26 Sep 2025 10:09:22 -0400 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1v298E-0005fJ-DR for qemu-devel@nongnu.org; Fri, 26 Sep 2025 10:09:19 -0400 Received: by mail-wr1-x42b.google.com with SMTP id ffacd0b85a97d-3f99ac9acc4so1874772f8f.3 for ; Fri, 26 Sep 2025 07:09:01 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-410f2007372sm6338315f8f.16.2025.09.26.07.08.58 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Sep 2025 07:08:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758895739; x=1759500539; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=khGd2vyM0LqffZpI9eeao31QS+mzqXWFdrP3S+/byUk=; b=a2d9FwnH66FQnQvFi+TlDOaKjwLpHPQm2BTDhb0XtKpdlQblEmmT65hrXqQqp3ZtbP uTwAwzz4yar4NCl9UPILRHzM5rD7mvaZIX6LEdded1Rra5gnbnhTZth/Jyf8CXGspVHc aLJzMSbxeApKgoPXTgsx8zieRw6kruPbzMlhu8XOU0XV0B5DLQJXDL3pYJO5b6uf8h5Q 75JVed+yyvfFDHYCqylIHPBa7p7FjBRlRNIjPTvtivElb9y0wEt+jcaEfo7wRVkWbmq8 ttEw8h00q6N9mfHz0sIkpmqfFGNZKJ5ei8Xaar9xTYjs9yhy1Y9fJyDKrrFPlgcgJl0x HMjw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758895739; x=1759500539; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=khGd2vyM0LqffZpI9eeao31QS+mzqXWFdrP3S+/byUk=; b=rCLajvcfgQS0GqPsTpCt9bKpOBEn1K39BEzcn/4D9/4zL/b4OS4D/dDdcv+n8YccWb o4rWySin4Fzox0SX/9uZAADcgHp1jeGEIh/LbaasA/MohnPukPFizqrcE+s17Gh5GGhN 6lK/rC7utjln/Ed2rWdhK76PcQE87xUqokzdpoY67p6nCjobW4Re7hSSMKmGU9crX1F1 8sSsjBTw6MgNQMhGIDPfaIzt1pVEhMNrQ1e+o1awLEDdodDADq9Ra+znTEES32PBsDda bfDLaF2ptLElEQiHxmTkRh8vss4lfMKMPqeHFavuKMLDP8w+onOHWMitj52ISW62Yy4G FX9w== X-Gm-Message-State: AOJu0Yxw7Zqn0avAFD6nVPipOT3r/CD+jj2Y1rxOu9VXDW/2l2KQu1Eq EW0R1cFlLlQ0891X3g/noifQ5tnksPBpYfEQrco3h2v4zfujhiRtXAEUHdTiMiqlHdh3Qgm5RTx IJ3jb X-Gm-Gg: ASbGncvZeZz48qZYiyPOiMRqfCJfi8tdILje8SylnZ3NGyajJD0kSD6GlD8VsulIve1 iGJDTTuM7lwSwZf6e9Pm22eNU0PACrhgNpB4aRY76ri0sA6+2fAspqF93F2WUa11xgquxyYd3vB evkMyXDX5wK/0onBPVm1RiUkpG4GEKCkfQhsn/wb4lyVL2wkFJ0TMarpkvWUlZjnVW2raGi7+I6 zpAo39hpph/4yVcoOFa+QPpWKN4j5K0n+rizEItgxwhMgczz8o4ohENtk0RSSdXSN88eHka51yL Ar0Zzi2o0h5R9k3j6yOpR9WtlO8rdSMMiSyTJRiFH3s1/cdNumU1Bk+9AqiXTjtPHINIaeChzyD eVTi++6J1q6hP0XFwAVNL78EiYVBBlXUblaanJekYn3/q4Jbh9w== X-Google-Smtp-Source: AGHT+IHslPOYx0lwfX8wo0b/kTZjIkOZ2QkWI8vmlCmLEw6vmluthLj8heE3PzcY/gSzqXQCkSdb8Q== X-Received: by 2002:a05:6000:40e0:b0:3e1:9b75:f0b8 with SMTP id ffacd0b85a97d-40e499acc26mr6216180f8f.47.1758895739173; Fri, 26 Sep 2025 07:08:59 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/44] target/arm: Use raw_write in cp_reg_reset Date: Fri, 26 Sep 2025 15:08:12 +0100 Message-ID: <20250926140844.1493020-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250926140844.1493020-1-peter.maydell@linaro.org> References: <20250926140844.1493020-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758895932878116600 From: Richard Henderson Reduce the places that know about field types by 1. Reviewed-by: Manos Pitsidianakis Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- target/arm/cpu.c | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index c65af7e7614..91ae56dddb2 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -192,14 +192,8 @@ static void cp_reg_reset(gpointer key, gpointer value,= gpointer opaque) * This is basically only used for fields in non-core coprocessors * (like the pxa2xx ones). */ - if (!ri->fieldoffset) { - return; - } - - if (cpreg_field_is_64bit(ri)) { - CPREG_FIELD64(&cpu->env, ri) =3D ri->resetvalue; - } else { - CPREG_FIELD32(&cpu->env, ri) =3D ri->resetvalue; + if (ri->fieldoffset) { + raw_write(&cpu->env, ri, ri->resetvalue); } } =20 --=20 2.43.0 From nobody Sun Sep 28 15:26:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758896169; cv=none; d=zohomail.com; s=zohoarc; b=dee/fxqzD5pzASX2ohRGfg7ptw+yeUYNq5DWNkBkh6WtIpxWMx27xtySQyd3z2v8AgnkjegNHoqZukCb15IaHJvJLH45zyJTC9HQzpF9yYxBvG+rdjItEjzA2N9ZfUsQ6U+T1rkUlUXx5X7zr1njYj58Hx5ptU5OUQQSjRxbcN0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758896169; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=Q3RNZ4P3Tq3zjqcHANGsM138DWjS8vi9+XNzo2XY8fw=; b=BQndr62IMCbfTh7JDyLhGPFih7zZOAX3yRlik2c1LaMzQlgwrO2zAsvmxUqfs7N0Z9HVCueZiRj2BptAYkqUGiomkn/UA9lvaZyw/wOnWriWG5bwGtCoofQTP8xRtJk6cIJR6KyJ+d05D1OHsbME/4ndFPEB8Tsv/42wl7BdLc4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1758896169297104.33709264582637; Fri, 26 Sep 2025 07:16:09 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v2990-00087O-FG; Fri, 26 Sep 2025 10:09:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v298W-0007NU-KV for qemu-devel@nongnu.org; Fri, 26 Sep 2025 10:09:25 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1v298E-0005fh-D7 for qemu-devel@nongnu.org; Fri, 26 Sep 2025 10:09:24 -0400 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-46cf7bbfda8so12136035e9.2 for ; Fri, 26 Sep 2025 07:09:03 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-410f2007372sm6338315f8f.16.2025.09.26.07.08.59 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Sep 2025 07:08:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758895740; x=1759500540; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Q3RNZ4P3Tq3zjqcHANGsM138DWjS8vi9+XNzo2XY8fw=; b=n7zU10VQNlHtoILDgw07275e0A52IdeTHOGWa6qSn4lxvscvYLIz1ZX7K1Offt1KBY yWZgoxRYq3LLm3jHlm7VI4zU5ehQ4/yTmQfKeh+LrmnOcNZ6Hqo/sBekfZfXfbOoHoTm sB/LzB8oRbkDxNYPm18PGTsyI3EyuS418DDhmzkJLR/olL6YBoCae2QrlNsGEa5i8Yds AKKA/fL8xPIdjM6MRCvfOr9dpokrEvdZ7VCmCgUxcoI62gB+IA1NVU/AjDRIbOKsOYCk pMN3/p1GWeZZ+Wcskh0/vBfefbJhM6snFTLlflMjpG35RBk/gldIrTJ6ZGb4bTQQ20Ws UZdg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758895740; x=1759500540; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Q3RNZ4P3Tq3zjqcHANGsM138DWjS8vi9+XNzo2XY8fw=; b=hI7YxXc4cPk4OMl4SVybqtfFsxBhBW1rTL+rfHeNSUg+OaM/XvW5JrMVhB4QbsnMYI 3QBmDFzsyvvkEwLEt2h6OcL7EezVcqGjpWVvTUK6YmONc9NSmjALHUbpBr7L7B3ln60O AhhsX2xRKGYO/9LZXcdgmzvQnYp+xts16Vy5VUe3eILOa3RIuqSjlMG4zsBqXDqioDXN cFeczCAQ3CmTGKjADlm+uE1mPG6Q/W3whdThJuLGWP115UmE2s0uKkw3wwTGRDsPrGKR MEAjdFxaaievYyhEV0o61UjT4+nXnY6Kj+xB8spOykwv7Uc1/XtRTE5lUtg73ODBCklS viSQ== X-Gm-Message-State: AOJu0YxiT4ON+lQwgcHRFgJBMrAQzhtWNSm3QW1p1PGQ9Xlgh2BvNCW/ vuXeqzwuIvdG+ix5/AFoeI2ve8sZfHuSB6y2tkzWhwKBkLzDqncXlFdh3H+/2+8kTo2kV/kkb6K Oc/8o X-Gm-Gg: ASbGncuoptICyEEfKJ/W5SGfzM8kIM4Yg64XHQS39ygMXmeZLhPMi8NyDuGNFhDEnkf 0UWyQvL4HRP5igSXsousriP7ueHsJhZReTCL41GM2NeZ9dE+vYjzkmOTPrxlsKo0hdj93pTn+1H lmgRn9fDGlZSFvcnNl/ruLRa1ShI8UP3NTM/pZVuCISdewL7CRfLkIGkrV4SOKFtvyjvn3ijrzw M3qP/Iy+ftsZp/VzSZYxcwz4v4mZVmwLRvgQ9TyCmoR9Tk8g0hq+C0ijjhVGnIfgHF5Imzg8hWh TUXey6zsSlrG/KOzNS4eNFbE6IW7ui4FCXu/sp6vZ96b5JDHAYmPxJCavi+kON1RMAjvoIof+Hm 9HwPYSzm5yuaVsL+OJ2OdhLErk3zB0RPFzOUB3GU= X-Google-Smtp-Source: AGHT+IFRcgRb8fY8Vo9zR2iQtE7cg1FfM5Ytvevipl4wSITKKtlU/yZh03r+Lj25NQim8D4JrLxFuw== X-Received: by 2002:a05:600c:4816:b0:46e:3287:57d6 with SMTP id 5b1f17b1804b1-46e32a0bd2amr44971485e9.27.1758895740090; Fri, 26 Sep 2025 07:09:00 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/44] target/arm: Rename all ARMCPRegInfo from opaque to ri Date: Fri, 26 Sep 2025 15:08:13 +0100 Message-ID: <20250926140844.1493020-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250926140844.1493020-1-peter.maydell@linaro.org> References: <20250926140844.1493020-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, T_SPF_HELO_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758896171508116600 From: Richard Henderson These pointers are no opaque, they have a specific type. Reviewed-by: Manos Pitsidianakis Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- target/arm/cpregs.h | 10 +++++----- target/arm/helper.c | 6 +++--- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 2a4826f5c4f..8f3e728d8ed 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -866,15 +866,15 @@ typedef struct ARMCPRegInfo ARMCPRegInfo; * Access functions for coprocessor registers. These cannot fail and * may not raise exceptions. */ -typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque); -typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque, +typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *ri); +typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value); /* Access permission check functions for coprocessor registers. */ typedef CPAccessResult CPAccessFn(CPUARMState *env, - const ARMCPRegInfo *opaque, + const ARMCPRegInfo *ri, bool isread); /* Hook function for register reset */ -typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque); +typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *ri); =20 #define CP_ANY 0xff =20 @@ -1100,7 +1100,7 @@ void raw_write(CPUARMState *env, const ARMCPRegInfo *= ri, uint64_t value); * CPResetFn that does nothing, for use if no reset is required even * if fieldoffset is non zero. */ -void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque); +void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *ri); =20 /* * Return true if this reginfo struct's field in the cpu state struct diff --git a/target/arm/helper.c b/target/arm/helper.c index 009f8d6fa1c..7b23e7e5889 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1073,7 +1073,7 @@ static const ARMCPRegInfo v6k_cp_reginfo[] =3D { .resetvalue =3D 0 }, }; =20 -static void arm_gt_cntfrq_reset(CPUARMState *env, const ARMCPRegInfo *opaq= ue) +static void arm_gt_cntfrq_reset(CPUARMState *env, const ARMCPRegInfo *ri) { ARMCPU *cpu =3D env_archcpu(env); =20 @@ -5382,7 +5382,7 @@ static const ARMCPRegInfo rndr_reginfo[] =3D { .access =3D PL0_R, .readfn =3D rndr_readfn }, }; =20 -static void dccvap_writefn(CPUARMState *env, const ARMCPRegInfo *opaque, +static void dccvap_writefn(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { #ifdef CONFIG_TCG @@ -7829,7 +7829,7 @@ uint64_t arm_cp_read_zero(CPUARMState *env, const ARM= CPRegInfo *ri) return 0; } =20 -void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque) +void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *ri) { /* Helper coprocessor reset function for do-nothing-on-reset registers= */ } --=20 2.43.0 From nobody Sun Sep 28 15:26:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758896350; cv=none; d=zohomail.com; s=zohoarc; b=fw6ikMF16T9t1122MjtwuVtzEDxad9YMZKcApdA4Bvx0xHr2JgDpsWxHMxTC4QPJpjDc5HU4Xky7U5I5nsnalcnmAY0fRMfcUQ48tgk3CQLYjTc8FkgnpQJ98SFsvQX9LgE/CVcvRN4YQvy8/oin254hi4i9nnv51w+B9i8XEHw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758896350; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=apLLASp4weKyN7zWsCtf8AKJ98rMJgUXlQ4z+73SGew=; b=RSVLvrrdD4FBNkUnXee+HCTH8iPmEFS6iq41PSyWVkhNo6AHyYejgbAgLO6LvLXKa2DrMqa0y4iP08A5enLgJlqVokYMX53HcNR8/pjoOSpsut2RqoXNIWD5vlHsXUouNye8PzIDX074N+YcswrvVSMfcvcSveDlDKX8IOzjFEo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1758896350070305.6713860592149; Fri, 26 Sep 2025 07:19:10 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v298g-0007XX-ON; Fri, 26 Sep 2025 10:09:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v298V-0007Ko-MF for qemu-devel@nongnu.org; Fri, 26 Sep 2025 10:09:23 -0400 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1v298E-0005fl-CY for qemu-devel@nongnu.org; Fri, 26 Sep 2025 10:09:22 -0400 Received: by mail-wr1-x42c.google.com with SMTP id ffacd0b85a97d-3ee13baf2e1so1766998f8f.3 for ; Fri, 26 Sep 2025 07:09:03 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-410f2007372sm6338315f8f.16.2025.09.26.07.09.00 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Sep 2025 07:09:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758895741; x=1759500541; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=apLLASp4weKyN7zWsCtf8AKJ98rMJgUXlQ4z+73SGew=; b=elcBGXhfoWk1ca29fCqpJibV/D/E9i9Us78O38eMEexmetDZo6XrBPsl2CGMGzBHFK 77yywEfjgP5bZdJMjBsELRcoTUaoCtGJUm6NlZ87mtmR+Y3+xaQjJDTZlPFC1i2r0R/I 88yW71QBtDj+hWboM0idBfliGIgxIlrpjZTqsvM8W32yMJlZzMNp/7v6BJBHbR2gNoB3 qumk+g5V8o+zULFhq4cbJuRAZDwV3oqeTfpVlWTaEWGbbXWo6jjCp1JnJuUbh3HyQUwI 8RJWg5zjZIyukV5q5jw0BlC+m6Jm6dGILO8+HCZSEWa+gvgccfj76bAB/9alsdNaYaGF KcPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758895741; x=1759500541; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=apLLASp4weKyN7zWsCtf8AKJ98rMJgUXlQ4z+73SGew=; b=dXgmWHDDceuEgdHmLmJKkJ4NXmqk6hMuK5cVIVJYmq/17OlyACq4Qf92Oex4FBylpS vJm/UaMkoeu+w6Q/irV8eIG+GnnC0tLjNxmD/+jXCmnrmodh/HjzAFhk7jp2PcUM27iA n0saqSmSqm2eGrPM30te4t4i0vG+BUo79YP6QXjZlmkuuCgjvkGc/DeZoKH/DXLra8UH hN9junAj7abxuzvu+jPbOWGUO+SoKi9SA1nncDBS8XXBX1QbjrDQBINrSsLHjyfZYhHE lVBfuFGhR3VO9hC5yqOgvv63ZUECFVWRhNP5l+aZk+hyBY9TdeazfW4MfM2DtsEKU3DN oLNQ== X-Gm-Message-State: AOJu0YwbGCLO4z++ngCu2IidS8L0Mcd0z82rf18kytE9v/1JhAgswe1Q axeB5sMm+FU2WKFYIItXCnEToVxhWWnH4VgbFfxfYpcG7t2iTEZbt3ijAkfAkcw8ny5yXX7/83l zy9TQ X-Gm-Gg: ASbGncsCH8DVPow6/9BIQ6aYfOksyZ1Nj/rp4pFoz36R2Exu0cQ3z7YCMbEhShWXndh 6gPIGNBM6JHblNJbouR9i4JZNLGbh391BhadFipsQJtF5dxON6v1bX/C7xsEXn/dEneJkop6XSw 2s+CuJUhUTGi/KnsPe+0UFa5RQUOBd10WNodk0JKN6e8STv51OJ4ohoET7k1ykYsUx6hqikc2Kv X3VbZqV5PDMR36jpfhPnyWwVGv6vfBUZVPHEnSH5+q2xvBTumxBQCkxH4T/czuXTPe/VE9XDDBy dhQQmciU8hhGF0/OqrsyApRipVrh5XHoYDU8By928TiT4Zw4+MpsVlgUroh0v/uEYRpAoy4cC2T ajdJ//lu4nncb0lVX0SpSx2X2O4wx X-Google-Smtp-Source: AGHT+IES8WEcjchgptnlNTXXyi+JNRvV3wB2zq3FdRYGmusigJEa5Ei31F+5Xv6dsypfAr4ChKFRpg== X-Received: by 2002:a05:6000:26cf:b0:3ee:1125:5250 with SMTP id ffacd0b85a97d-40e46ad0128mr7048187f8f.24.1758895741139; Fri, 26 Sep 2025 07:09:01 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/44] target/arm: Drop define_one_arm_cp_reg_with_opaque Date: Fri, 26 Sep 2025 15:08:14 +0100 Message-ID: <20250926140844.1493020-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250926140844.1493020-1-peter.maydell@linaro.org> References: <20250926140844.1493020-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758896352391116600 From: Richard Henderson The last use of this interface was removed in 603bc048a27f ("hw/arm: Remove pxa2xx_pic"). As the comment in gicv3 stated, keeping pointer references to cpregs has SMP issues, so avoid future temptation by removing the interface. Reviewed-by: Manos Pitsidianakis Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- target/arm/cpregs.h | 32 ++++++++------------------------ hw/intc/arm_gicv3_cpuif.c | 10 +--------- target/arm/helper.c | 29 +++++++++++------------------ 3 files changed, 20 insertions(+), 51 deletions(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 8f3e728d8ed..d02d74f1f5d 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -931,11 +931,7 @@ struct ARMCPRegInfo { */ uint32_t nv2_redirect_offset; =20 - /* - * The opaque pointer passed to define_arm_cp_regs_with_opaque() when - * this register was defined: can be used to hand data through to the - * register read/write functions, since they are passed the ARMCPRegIn= fo*. - */ + /* This is used only by VHE. */ void *opaque; /* * Value of this register, if it is ARM_CP_CONST. Otherwise, if @@ -1029,27 +1025,15 @@ struct ARMCPRegInfo { #define CPREG_FIELD64(env, ri) \ (*(uint64_t *)((char *)(env) + (ri)->fieldoffset)) =20 -void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, const ARMCPRegInfo *re= g, - void *opaque); +void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs); +void define_arm_cp_regs_len(ARMCPU *cpu, const ARMCPRegInfo *regs, size_t = len); =20 -static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *= regs) -{ - define_one_arm_cp_reg_with_opaque(cpu, regs, NULL); -} - -void define_arm_cp_regs_with_opaque_len(ARMCPU *cpu, const ARMCPRegInfo *r= egs, - void *opaque, size_t len); - -#define define_arm_cp_regs_with_opaque(CPU, REGS, OPAQUE) \ - do { \ - QEMU_BUILD_BUG_ON(ARRAY_SIZE(REGS) =3D=3D 0); = \ - define_arm_cp_regs_with_opaque_len(CPU, REGS, OPAQUE, \ - ARRAY_SIZE(REGS)); \ +#define define_arm_cp_regs(CPU, REGS) \ + do { \ + QEMU_BUILD_BUG_ON(ARRAY_SIZE(REGS) =3D=3D 0); \ + define_arm_cp_regs_len(CPU, REGS, ARRAY_SIZE(REGS)); \ } while (0) =20 -#define define_arm_cp_regs(CPU, REGS) \ - define_arm_cp_regs_with_opaque(CPU, REGS, NULL) - const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encode= d_cp); =20 /* @@ -1168,7 +1152,7 @@ static inline bool arm_cpreg_traps_in_nv(const ARMCPR= egInfo *ri) * means that the right set of registers is exactly those where * the opc1 field is 4 or 5. (You can see this also in the assert * we do that the opc1 field and the permissions mask line up in - * define_one_arm_cp_reg_with_opaque().) + * define_one_arm_cp_reg().) * Checking the opc1 field is easier for us and avoids the problem * that we do not consistently use the right architectural names * for all sysregs, since we treat the name field as largely for debug. diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index 4b4cf091570..72e91f971a4 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -3037,15 +3037,7 @@ void gicv3_init_cpuif(GICv3State *s) * cpu->gic_pribits */ =20 - /* Note that we can't just use the GICv3CPUState as an opaque poin= ter - * in define_arm_cp_regs_with_opaque(), because when we're called = back - * it might be with code translated by CPU 0 but run by CPU 1, in - * which case we'd get the wrong value. - * So instead we define the regs with no ri->opaque info, and - * get back to the GICv3CPUState from the CPUARMState. - * - * These CP regs callbacks can be called from either TCG or HVF co= de. - */ + /* These CP regs callbacks can be called from either TCG or HVF. */ define_arm_cp_regs(cpu, gicv3_cpuif_reginfo); =20 /* diff --git a/target/arm/helper.c b/target/arm/helper.c index 7b23e7e5889..b76a0edb0f4 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7355,12 +7355,11 @@ void register_cp_regs_for_features(ARMCPU *cpu) } =20 /* - * Private utility function for define_one_arm_cp_reg_with_opaque(): + * Private utility function for define_one_arm_cp_reg(): * add a single reginfo struct to the hash table. */ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, - void *opaque, CPState state, - CPSecureState secstate, + CPState state, CPSecureState secstate, int crm, int opc1, int opc2, const char *name) { @@ -7448,9 +7447,6 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, r2->opc2 =3D opc2; r2->state =3D state; r2->secure =3D secstate; - if (opaque) { - r2->opaque =3D opaque; - } =20 if (make_const) { /* This should not have been a very special register to begin. */ @@ -7555,8 +7551,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, } =20 =20 -void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, - const ARMCPRegInfo *r, void *opaque) +void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *r) { /* * Define implementations of coprocessor registers. @@ -7715,7 +7710,7 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, if (nxs_ri.fgt) { nxs_ri.fgt |=3D R_FGT_NXS_MASK; } - add_cpreg_to_hashtable(cpu, &nxs_ri, opaque, state, + add_cpreg_to_hashtable(cpu, &nxs_ri, state, ARM_CP_SECSTATE_NS, crm, opc1, opc2, name); } @@ -7729,17 +7724,17 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, switch (r->secure) { case ARM_CP_SECSTATE_S: case ARM_CP_SECSTATE_NS: - add_cpreg_to_hashtable(cpu, r, opaque, state, + add_cpreg_to_hashtable(cpu, r, state, r->secure, crm, opc1, o= pc2, r->name); break; case ARM_CP_SECSTATE_BOTH: name =3D g_strdup_printf("%s_S", r->name); - add_cpreg_to_hashtable(cpu, r, opaque, state, + add_cpreg_to_hashtable(cpu, r, state, ARM_CP_SECSTATE_S, crm, opc1, opc2, name); g_free(name); - add_cpreg_to_hashtable(cpu, r, opaque, state, + add_cpreg_to_hashtable(cpu, r, state, ARM_CP_SECSTATE_NS, crm, opc1, opc2, r->nam= e); break; @@ -7751,7 +7746,7 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, * AArch64 registers get mapped to non-secure inst= ance * of AArch32 */ - add_cpreg_to_hashtable(cpu, r, opaque, state, + add_cpreg_to_hashtable(cpu, r, state, ARM_CP_SECSTATE_NS, crm, opc1, opc2, r->name); } @@ -7762,12 +7757,10 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, } =20 /* Define a whole list of registers */ -void define_arm_cp_regs_with_opaque_len(ARMCPU *cpu, const ARMCPRegInfo *r= egs, - void *opaque, size_t len) +void define_arm_cp_regs_len(ARMCPU *cpu, const ARMCPRegInfo *regs, size_t = len) { - size_t i; - for (i =3D 0; i < len; ++i) { - define_one_arm_cp_reg_with_opaque(cpu, regs + i, opaque); + for (size_t i =3D 0; i < len; ++i) { + define_one_arm_cp_reg(cpu, regs + i); } } =20 --=20 2.43.0 From nobody Sun Sep 28 15:26:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758896891; cv=none; d=zohomail.com; s=zohoarc; b=noK+bHytDNMVlfmoszwzvnjfxVrV0QprBKbOrp2rJBz4/NH58Xfan3sDw8W2skdeGZhPq2RjhlXUGm89Rh6NBzTI/i8FKvvyYDAAsZ67b2br+p939b7oQFQb9giLomLZViUkczUbISperISeGPKWOhDcesxXTuvaU13OfhS6oCU= ARC-Message-Signature: i=1; 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Fri, 26 Sep 2025 07:09:02 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/44] target/arm: Restrict the scope of CPREG_FIELD32, CPREG_FIELD64 Date: Fri, 26 Sep 2025 15:08:15 +0100 Message-ID: <20250926140844.1493020-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250926140844.1493020-1-peter.maydell@linaro.org> References: <20250926140844.1493020-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758896893271116600 From: Richard Henderson Reviewed-by: Manos Pitsidianakis Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- target/arm/cpregs.h | 9 --------- target/arm/helper.c | 12 ++++++++++++ 2 files changed, 12 insertions(+), 9 deletions(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index d02d74f1f5d..6fb1994afa0 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -1016,15 +1016,6 @@ struct ARMCPRegInfo { CPAccessFn *orig_accessfn; }; =20 -/* - * Macros which are lvalues for the field in CPUARMState for the - * ARMCPRegInfo *ri. - */ -#define CPREG_FIELD32(env, ri) \ - (*(uint32_t *)((char *)(env) + (ri)->fieldoffset)) -#define CPREG_FIELD64(env, ri) \ - (*(uint64_t *)((char *)(env) + (ri)->fieldoffset)) - void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs); void define_arm_cp_regs_len(ARMCPU *cpu, const ARMCPRegInfo *regs, size_t = len); =20 diff --git a/target/arm/helper.c b/target/arm/helper.c index b76a0edb0f4..fe298670f12 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -51,6 +51,15 @@ int compare_u64(const void *a, const void *b) return 0; } =20 +/* + * Macros which are lvalues for the field in CPUARMState for the + * ARMCPRegInfo *ri. + */ +#define CPREG_FIELD32(env, ri) \ + (*(uint32_t *)((char *)(env) + (ri)->fieldoffset)) +#define CPREG_FIELD64(env, ri) \ + (*(uint64_t *)((char *)(env) + (ri)->fieldoffset)) + uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri) { assert(ri->fieldoffset); @@ -71,6 +80,9 @@ void raw_write(CPUARMState *env, const ARMCPRegInfo *ri, = uint64_t value) } } =20 +#undef CPREG_FIELD32 +#undef CPREG_FIELD64 + static void *raw_ptr(CPUARMState *env, const ARMCPRegInfo *ri) { return (char *)env + ri->fieldoffset; --=20 2.43.0 From nobody Sun Sep 28 15:26:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758896086; cv=none; d=zohomail.com; s=zohoarc; b=gZr4ci5wrJMyPXWOvN5tamUSFPpeV2/qBJiDMwybj0pZK/5bqQznwv4MazXtWpMRJAYLQl0Oche1TlWAkLO6Nvp+IrJesUfj63cbdsKXz9eWlfS4MLYtnT2iQFzpRXAbqMjIh5Su0GWl1NsT0zLdzuI2IU5zDOZmAMy71UFNxO0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758896086; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; 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Reviewed-by: Manos Pitsidianakis Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- target/arm/cpregs.h | 10 ++++++---- target/arm/gdbstub.c | 7 +++++-- target/arm/helper.c | 18 +++++++++++++----- 3 files changed, 24 insertions(+), 11 deletions(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 6fb1994afa0..74bae7309a3 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -22,6 +22,7 @@ #define TARGET_ARM_CPREGS_H =20 #include "hw/registerfields.h" +#include "exec/memop.h" #include "target/arm/kvm-consts.h" #include "cpu.h" =20 @@ -1078,12 +1079,13 @@ void raw_write(CPUARMState *env, const ARMCPRegInfo= *ri, uint64_t value); void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *ri); =20 /* - * Return true if this reginfo struct's field in the cpu state struct - * is 64 bits wide. + * Return MO_32 if the field in CPUARMState is uint32_t or + * MO_64 if the field in CPUARMState is uint64_t. */ -static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri) +static inline MemOp cpreg_field_type(const ARMCPRegInfo *ri) { - return (ri->state =3D=3D ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BI= T); + return (ri->state =3D=3D ARM_CP_STATE_AA64 || (ri->type & ARM_CP_64BIT) + ? MO_64 : MO_32); } =20 static inline bool cp_access_ok(int current_el, diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index 2d331fff445..4e2ac49b6a9 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -247,10 +247,13 @@ static int arm_gdb_get_sysreg(CPUState *cs, GByteArra= y *buf, int reg) key =3D cpu->dyn_sysreg_feature.data.cpregs.keys[reg]; ri =3D get_arm_cp_reginfo(cpu->cp_regs, key); if (ri) { - if (cpreg_field_is_64bit(ri)) { + switch (cpreg_field_type(ri)) { + case MO_64: return gdb_get_reg64(buf, (uint64_t)read_raw_cp_reg(env, ri)); - } else { + case MO_32: return gdb_get_reg32(buf, (uint32_t)read_raw_cp_reg(env, ri)); + default: + g_assert_not_reached(); } } return 0; diff --git a/target/arm/helper.c b/target/arm/helper.c index fe298670f12..26941ecd4f8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -63,20 +63,28 @@ int compare_u64(const void *a, const void *b) uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri) { assert(ri->fieldoffset); - if (cpreg_field_is_64bit(ri)) { + switch (cpreg_field_type(ri)) { + case MO_64: return CPREG_FIELD64(env, ri); - } else { + case MO_32: return CPREG_FIELD32(env, ri); + default: + g_assert_not_reached(); } } =20 void raw_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { assert(ri->fieldoffset); - if (cpreg_field_is_64bit(ri)) { + switch (cpreg_field_type(ri)) { + case MO_64: CPREG_FIELD64(env, ri) =3D value; - } else { + break; + case MO_32: CPREG_FIELD32(env, ri) =3D value; + break; + default: + g_assert_not_reached(); } } =20 @@ -2754,7 +2762,7 @@ static void vmsa_ttbr_write(CPUARMState *env, const A= RMCPRegInfo *ri, uint64_t value) { /* If the ASID changes (with a 64-bit write), we must flush the TLB. = */ - if (cpreg_field_is_64bit(ri) && + if (cpreg_field_type(ri) =3D=3D MO_64 && extract64(raw_read(env, ri) ^ value, 48, 16) !=3D 0) { ARMCPU *cpu =3D env_archcpu(env); tlb_flush(CPU(cpu)); --=20 2.43.0 From nobody Sun Sep 28 15:26:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758896726; cv=none; d=zohomail.com; s=zohoarc; b=ZWAqHUNXFc69xjoq5xRPf+Sw4QJeSDAkE6bDmGsFJ4QBGYYbPNnY1GyZ8EUlclUdvkmhSvuGsBwJrGQVQLv76tHqBdoHQPdBmzlylneRb+jfnHPfwPKlV7jTMY6pI0K/R2FgCfak1Eck0v9u0ZOWhtJSxc78lLFBPc4JJeQnp4M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758896726; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=gECgbKEcYHTmXKtVZy6CzY300CnzlKZCzOl+7EfMFg8=; b=LXFuChCtobL+Tg8L4wh1VbSezExn7GzO1oWITzeHKooRPxj1ty3U6malqqF7MXkKedHfqwJUaSa085Xj8Dl9W8itFG1cto9NZ9OHCs/zwNXTMJyfVtF6TpiwYaKIv+jZ/E4ECeF39AsB06FvptA9RW0jSPD9ajb9HhyYhEniFhY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1758896726586383.6032870159239; Fri, 26 Sep 2025 07:25:26 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v2992-0008BQ-PO; Fri, 26 Sep 2025 10:09:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v298Z-0007Sl-9U for qemu-devel@nongnu.org; Fri, 26 Sep 2025 10:09:27 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1v298J-0005gX-F0 for qemu-devel@nongnu.org; Fri, 26 Sep 2025 10:09:27 -0400 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-46e3a50bc0fso8862235e9.3 for ; Fri, 26 Sep 2025 07:09:07 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-410f2007372sm6338315f8f.16.2025.09.26.07.09.03 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Sep 2025 07:09:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758895744; x=1759500544; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=gECgbKEcYHTmXKtVZy6CzY300CnzlKZCzOl+7EfMFg8=; b=ICNxceDmPJyi8PfhLwMAWlFs2DsX+qr4ARt9xPCl7KtVeQlIYE+OKq9YBpKaHqljMf 7MvynTKSegKqlLbsCOi3UP+/XYAvAy7wu1XDxAoJELi5MqjAbaOyM41EpR/SOfJuIGLO yWypiBcslFA8FGkEvWNSJEqwWspxUTUyvnhlv+cf1A1kl0czC0l8pG8v/UjgHq2jY2Sd 36tSRNzHtZHSwgA52AUlxE5rryUB0H//V2sqPYM/RBe3iLCtFJaYhsa6ED3rr1NqhMer 7FMW8OYssWBeF1c3xDL6xg97ofxJPhJ5HlJKRfVahzqPy3VSal6p3qKLg2v/TfKq/oGf p1ZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758895744; x=1759500544; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gECgbKEcYHTmXKtVZy6CzY300CnzlKZCzOl+7EfMFg8=; b=IQgVIpZiZxruGq9CP/V4htkpUJ6+9jDmVIQafkZfZoQsFUHyP3YhLE/POrBhaxCAz2 RwDg8dAAJvyUNPXf7/X6hKA44e1JJ1YbZbO5ysVnEyrcfEV5J2aaPbKaOAFLEHRxezYI r4edUrNvoDJqWeA5elNUrIgOdXu5LB/R5gh/0mnhDofaJEKPCMBIAoz+2CURWOnKRgRu wHR0Oy2TFzCKGfuRrLIHK8XgsOBfZpyWrAkB1+8l1oFP6vxOR44Znn+xlSt92uTrMuXt pYPmt+nsCJFXnt1LjqbxIashdxxw7sCfwhxK43k979CdetQkV+wz5f2CqEsAGaqPPgX0 68+A== X-Gm-Message-State: AOJu0YyqNJ+U/82qh1l4wdUcnAtHY28iusPU26BkTZ4TDd2D09G6UZu4 YcvUeuHe44xGNfU+SoMoLuZFxv/6IVrukQ329LeYV7yCITbKf+88nnCrgyokHVsi3GlmcEQWXpy uKCby X-Gm-Gg: ASbGncs8a375wUc0HfTBrQvNUwl07xumJm4RCNfczII5uoRdPX8dN/t6Ep5GiFFCBhh ZOiEqaqc1UHAIGr9TAlc8cqFD60XuyaEb/A6dSWh5EmTonWMDPACEvJnUf5f8wOsyy2nSVsoa5N SA3qQpdprsQjIO/ONfQQkwQYBnjbtTphQlcuaCZx5Cg+jObgPs93XKx/HrZiyHtwVgxR+nNaC6e AHaHm1KevYVV48X/N8Fzxp9rArILGZjzwug01SSuywkSe5bh7Bffl3UDRlO4juvf2k6Ky5aM0t6 WGZDHUMzTob5rLpybWSQ2500/Gruz1C80PGLAHTgDr+IEEeoBbnWctCE9WAFsQEO30vhLb3GHo+ oG2ucKY6rW3pvK2IOlvS7UCxujhdFkKRr+oaj9Ag= X-Google-Smtp-Source: AGHT+IERT4vZcoUUULqK50d1Rrr/NOqo9FJqCfgK+ElSWQwSJ3cvRv22J+VdRNtul6vJnYkvcoLmAA== X-Received: by 2002:a05:600c:8b5b:b0:46e:3dcb:d9a3 with SMTP id 5b1f17b1804b1-46e3dcbdc9bmr20959135e9.12.1758895744277; Fri, 26 Sep 2025 07:09:04 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 17/44] target/arm: Add CP_REG_AA32_64BIT_{SHIFT,MASK} Date: Fri, 26 Sep 2025 15:08:17 +0100 Message-ID: <20250926140844.1493020-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250926140844.1493020-1-peter.maydell@linaro.org> References: <20250926140844.1493020-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758896727217116601 From: Richard Henderson Give a name to the bit we're already using. Reviewed-by: Manos Pitsidianakis Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- target/arm/cpregs.h | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 74bae7309a3..f7dd6d2f758 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -178,9 +178,14 @@ enum { #define CP_REG_NS_SHIFT 29 #define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT) =20 +/* Distinguish 32-bit and 64-bit views of AArch32 system registers. */ +#define CP_REG_AA32_64BIT_SHIFT 15 +#define CP_REG_AA32_64BIT_MASK (1 << CP_REG_AA32_64BIT_SHIFT) + #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ - ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \ - ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) + (((ns) << CP_REG_NS_SHIFT) | \ + ((is64) << CP_REG_AA32_64BIT_SHIFT) | \ + ((cp) << 16) | ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) =20 #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ (CP_REG_AA64_MASK | \ @@ -202,7 +207,7 @@ static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) cpregid |=3D CP_REG_AA64_MASK; } else { if ((kvmid & CP_REG_SIZE_MASK) =3D=3D CP_REG_SIZE_U64) { - cpregid |=3D (1 << 15); + cpregid |=3D CP_REG_AA32_64BIT_MASK; } =20 /* @@ -226,8 +231,8 @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) kvmid =3D cpregid & ~CP_REG_AA64_MASK; kvmid |=3D CP_REG_SIZE_U64 | CP_REG_ARM64; } else { - kvmid =3D cpregid & ~(1 << 15); - if (cpregid & (1 << 15)) { + kvmid =3D cpregid & ~CP_REG_AA32_64BIT_MASK; + if (cpregid & CP_REG_AA32_64BIT_MASK) { kvmid |=3D CP_REG_SIZE_U64 | CP_REG_ARM; } else { kvmid |=3D CP_REG_SIZE_U32 | CP_REG_ARM; --=20 2.43.0 From nobody Sun Sep 28 15:26:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758896046; cv=none; d=zohomail.com; s=zohoarc; b=A6Nsnmt/4AfgxWVgK6kS6R0bT74gQhF2B1WrA76bDI2+J59hskzqrTxM697SIN3z+k7X3/p1ASIRO39xy6b9+OzK5nNxPkguICWmJEjb7/x/gGg9O7PXj+fS9hz8z+ixmOwmVFs9MzN+98IfSBncA1oNpx3ZeTv20EeCJ1+28pI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758896046; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=rs/KWAsQ5SpX2/EhCbEfW4QHUF/6557YiO72ZWIsagc=; b=Lqv/S5eYdqJlAoUjg/LtQRuoYKp3eGQAyKgKNNQw5I9jV7nSeSdAFTgsgA8G0/NFTKOpTA9HTg/xNfsMFF0doDWF9kYR1lHF1r2eMn5KuuOCeDr6TpjgDmDHa26vatyCbVGEOEXVVFy+0gFU7SvLjZzx5jEgYD21bmQQIM2SgGs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1758896046310520.2800000581851; Fri, 26 Sep 2025 07:14:06 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v299M-0008VP-GM; Fri, 26 Sep 2025 10:10:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v298q-0007nC-0e for qemu-devel@nongnu.org; Fri, 26 Sep 2025 10:09:45 -0400 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1v298O-0005gc-OY for qemu-devel@nongnu.org; Fri, 26 Sep 2025 10:09:41 -0400 Received: by mail-wr1-x42d.google.com with SMTP id ffacd0b85a97d-3fc36b99e92so2019558f8f.0 for ; Fri, 26 Sep 2025 07:09:08 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-410f2007372sm6338315f8f.16.2025.09.26.07.09.04 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Sep 2025 07:09:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758895745; x=1759500545; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=rs/KWAsQ5SpX2/EhCbEfW4QHUF/6557YiO72ZWIsagc=; b=xv12BqUu2jfYRqaCfMQX5qT4cTwd/C50U6Vvv5qKU7Utuo9pcDRcueljJChPQk+Ylv 3L/50ceRjGpODDSfRABbSy8xS8Mlah/lwX96HlisqVBxtFMGRsYpS3iwVpm+VkflfRH+ 4akORth2i4gbkw415krt3CiopkGSewGo00tMIZwXeTGU7tCqJZcPYJZQylzjNUs0iW4A R9sM82NagGUKQh7UCdAG1mamQXfVCVYu5I6PhNekHOaoF8sABlM0QAHSZUxzF9D4Q0ip 442YcmWyfYOvxC1+tEgl3EWrjT1L/ednyiFyMA3jj03IwZ/Msso6V/Y2jH+X2eTf5Mc9 94gQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758895745; x=1759500545; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rs/KWAsQ5SpX2/EhCbEfW4QHUF/6557YiO72ZWIsagc=; b=SNTN1RN55JIWnDBwmm7HqRIXW9FY8BNlS6wh4LaDqBwoZzsGinzYnYdBog5+iVdEgw CNE24GSJJUN5hgSZZHdORTQbb2OdLKTcvtwlFoawPPbmj4rbncfgWtRQJ4ePYCa4chAF QRUhWyVoniJwcEzi3Dvvq+/vztAOnnftDNTvl2U4ZCjhWTnMUk46rdu3zvUSWZguUHFH xJo0L97x/1wj2hyvHv3lkC3wEI+WAqqCDVCtD4fKtxrjxy+ywewyIAAPNuOpblSHuv9z mO5OXav3I7f0WN6owxX2HzqYPYE07qHOcJ16/JkSl/t9jxKzBnj/Z5l8ClGrAYTNGy+a FTjw== X-Gm-Message-State: AOJu0YzKgoY1tbSKUP83D+1+ysjRw5986FJt2j5OTT2arnUubOsogZX9 x8IKV0CgD3jGqm7AWlwJy+INmB05Rs09gfSCIHrjc1AG9hE9C4YIfmrgE2p4kpLBNJVtWwEUo4n +r4/p X-Gm-Gg: ASbGncsBkPsowUT6dNHku6BU22XcPKPIlEktNg42NIlng6jYnM3GLW0x/zkRV72GgT/ XLPkhy0S+FaRNxtLmOra21U5edOt/hRqF420/4N6xJ8POPBYv7n7y+ytMZIEYVn+wNv/3ULEv+y pPW026AgPBeL36TsNge7w5B7Y5uiDOTER8CA2nSilhogMtbLqx/ancy4Iv0D9OkPYYMAhE33fm4 de5o+AaKWoF6vXptQhexe6fMRv8T8mQm0QtEqZ3aLzLIj/8Ou7lnOVHrgE/1nWoYtwk/ghu3qOo u3D0oJB+1oa6hdqHcHnjMnU3a+U0lVC1lbj7TvDJxrzCcqKqDJx7yXyx2uDPdlnAYE7aTZsvSpp KaZVdu5tpuKqHOHps5IfH7mCm6m09poR+ifGmYN8= X-Google-Smtp-Source: AGHT+IF8vOuXnaXYVmX9qXud6P+bKt/X63312oXs6EqLm+t/y3JZaRTlsP2SOdiaGySCDxFiX52k3Q== X-Received: by 2002:a05:6000:2204:b0:3ea:d634:1493 with SMTP id ffacd0b85a97d-40f5e5c1023mr6196924f8f.3.1758895745228; Fri, 26 Sep 2025 07:09:05 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 18/44] target/arm: Rename CP_REG_AA32_NS_{SHIFT,MASK} Date: Fri, 26 Sep 2025 15:08:18 +0100 Message-ID: <20250926140844.1493020-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250926140844.1493020-1-peter.maydell@linaro.org> References: <20250926140844.1493020-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758896047633116600 From: Richard Henderson Rename from CP_REG_NS_* to emphasize this is specific to AArch32. Reviewed-by: Manos Pitsidianakis Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- target/arm/cpregs.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index f7dd6d2f758..417d79f7ba6 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -175,15 +175,15 @@ enum { * add a bit to distinguish between secure and non-secure cpregs in the * hashtable. */ -#define CP_REG_NS_SHIFT 29 -#define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT) +#define CP_REG_AA32_NS_SHIFT 29 +#define CP_REG_AA32_NS_MASK (1 << CP_REG_AA32_NS_SHIFT) =20 /* Distinguish 32-bit and 64-bit views of AArch32 system registers. */ #define CP_REG_AA32_64BIT_SHIFT 15 #define CP_REG_AA32_64BIT_MASK (1 << CP_REG_AA32_64BIT_SHIFT) =20 #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ - (((ns) << CP_REG_NS_SHIFT) | \ + (((ns) << CP_REG_AA32_NS_SHIFT) | \ ((is64) << CP_REG_AA32_64BIT_SHIFT) | \ ((cp) << 16) | ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) =20 @@ -214,7 +214,7 @@ static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) * KVM is always non-secure so add the NS flag on AArch32 register * entries. */ - cpregid |=3D 1 << CP_REG_NS_SHIFT; + cpregid |=3D CP_REG_AA32_NS_MASK; } return cpregid; } --=20 2.43.0 From nobody Sun Sep 28 15:26:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758896864; cv=none; d=zohomail.com; s=zohoarc; b=ZcsXaVh2SXT/VaDgixK5yAsOmOQO8BPaSgAeiBCkJ6SbYA3TeKex0FYR5g9MVK1bGvLokGbeEMAyjRHAVAQJ1NZ8Xn/t/wVQnrC+YgWH6CSig/VRJypvnk3CpKaN4+XRZwWS2a0KeLWvfYjVUbRDWocOXmc/8YOp5AnftBlDaQE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758896864; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=EvffExaOTzwk+Qku7c6pfTqkaF9GGHtbtWdcKsTMZPs=; b=ndlB7bB1UJ1BtRWOuP/kGTn7ArLTDgFu6XrdNkRQVtKAvOUYHOP8mE2d09cjclEdU6zYDYPiUmVa3vyDhHj3xnTN2KrBVrXlxbeZ6U+M6wjrRTM+4Dh/dMbZkzwq5rbe9R699+OhZiCa3+1eY4Aru+64aoSab9uREtfllfztB1w= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1758896864123725.8877027353429; Fri, 26 Sep 2025 07:27:44 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v2996-0008M4-IH; Fri, 26 Sep 2025 10:10:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v298k-0007gW-CP for qemu-devel@nongnu.org; Fri, 26 Sep 2025 10:09:40 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1v298O-0005gu-0J for qemu-devel@nongnu.org; Fri, 26 Sep 2025 10:09:37 -0400 Received: by mail-wr1-x432.google.com with SMTP id ffacd0b85a97d-3ee64bc6b90so1460150f8f.0 for ; Fri, 26 Sep 2025 07:09:09 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-410f2007372sm6338315f8f.16.2025.09.26.07.09.05 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Sep 2025 07:09:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758895746; x=1759500546; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=EvffExaOTzwk+Qku7c6pfTqkaF9GGHtbtWdcKsTMZPs=; b=eTorzBIc9Iy1vEclPbvyvxglOlkkXn/FnTQlSBnGFf93ljvhrJ9aoGz6MJN+jqIvcz RIHryq6nYbWF/DCqR06Yd883Zr6QwXp5hIVBtN3BR5T+ERMaxf4V4pP8CbxdMJBTv0X3 WhfFzj1CKmOB27+CDfpPbpM47l83NOBoCHIJvV4KRGu+qRHAyKwweI77UZDnqcipyKBa FqGy2zoCcDhZQdVscySPlLPik2DX3o7H3hLRhNXc2mV6wUbIvtdupAUepjRs07pM2qve oQKEFuPRLE2GbJ7ub+EjatCbkt9SGYjZp+JLz56gN1yARcUqOIZK3yM2zJm9uGnM+D+o 0wKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758895746; x=1759500546; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EvffExaOTzwk+Qku7c6pfTqkaF9GGHtbtWdcKsTMZPs=; b=Bbai9rAyRU5kruwSGYKq17x+9w4lU4LzyM2sAm9zo4fvftowoAm7RNO4jylnSL/zMh I1PALuegZyftDRd1nLK0bugAcCHojOBakFeMdQo20jywLwGkuUQhbybZphQrrbXHkdIF nzL8JcZedCoplm1CvcyLjp1ljvCL0W7GXktfhEMlxM5+soitvwt4hyHiSoK2otEQ7YyV ilPhndkqMcliwM6QWOpX7D0Pyct1o9JkVpNZ172MycLazqSS1QqmxsWwgtH9hU151KC6 1/dUHTQ4fqVb0fjwtJb/Gga5fkl5bzkonAKqJSqG1lI6YVT5GAS5M/nIc2qSz2rutE5E i15g== X-Gm-Message-State: AOJu0Yyr1U6ULJQ7He7VquxXls4qzT35xwJXRdfJg3wGOyujTUsWuLId jfXNjz2qENZFPMnMLwy3TwhdkLwq7937kVapyui6j6OiZ/agBO/kqlli3TqI93TmJCQ8q1p7Hz0 BDyG+ X-Gm-Gg: ASbGncvNEhbggMVxzRqPsZ0aZDgQt8JmSka8H9Z7sT7cU+BSbo7PeDuPoe75O9YX0NS 27YrBmrchsBtc59l/aBHuwBjjAyb3cDkzeHIxnRrevdtdp+rxanc/NQr6iEGFtUEcpEQKWK448q Qv4hT6GdmpDxsuSUpfAIUtpOyNg+oUHvYB+qg7jKcmwDve6mHJRsVuqR3PReS4BkX0Eg74/HZ8a Q0kQYCDXl5XyAb2CzjBkmLD/Y133D7HpXAccp/EKTunJvg23MHM+M/RAo09kMYPovT32guvdDbx DhKtBu6VA71I0I+I8zhCJG8Rb9Jqmll2Fbm2xUC7FM4Iu0qorJagnqFeBQJov77Nx2lvUQyu7lp AjHxpmk1gyAl2gjOIWPQlpZrBDH7I X-Google-Smtp-Source: AGHT+IG2KNcKc/6vVaXmX7wNASfpHoIbsZDlCkb8T4B2MPX03Wsd5iRDZGLKPktfnyNlIlVUOZInVg== X-Received: by 2002:a05:6000:2484:b0:405:1925:4972 with SMTP id ffacd0b85a97d-40e46515005mr6429455f8f.1.1758895746181; Fri, 26 Sep 2025 07:09:06 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 19/44] target/arm: Convert init_cpreg_list to g_hash_table_foreach Date: Fri, 26 Sep 2025 15:08:19 +0100 Message-ID: <20250926140844.1493020-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250926140844.1493020-1-peter.maydell@linaro.org> References: <20250926140844.1493020-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758896864841116600 From: Richard Henderson Adjust count_cpreg and add_cpreg_to_list to be used with g_hash_table_foreach instead of g_list_foreach. In this way we have the ARMCPRegInfo pointer directly rather than having to look it up from the key. Delay the sorting of the cpreg_indexes until after add_cpreg_to_list. This allows us to sort the data that we actually care about, the kvm id, as computed within add_cpreg_to_list, instead of having to repeatedly compute the kvm id within cpreg_key_compare. Signed-off-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- target/arm/helper.c | 54 ++++++++++++++++++--------------------------- 1 file changed, 21 insertions(+), 33 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 26941ecd4f8..27d5ab82920 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -229,11 +229,11 @@ bool write_list_to_cpustate(ARMCPU *cpu) return ok; } =20 -static void add_cpreg_to_list(gpointer key, gpointer opaque) +static void add_cpreg_to_list(gpointer key, gpointer value, gpointer opaqu= e) { ARMCPU *cpu =3D opaque; uint32_t regidx =3D (uintptr_t)key; - const ARMCPRegInfo *ri =3D get_arm_cp_reginfo(cpu->cp_regs, regidx); + const ARMCPRegInfo *ri =3D value; =20 if (!(ri->type & (ARM_CP_NO_RAW | ARM_CP_ALIAS))) { cpu->cpreg_indexes[cpu->cpreg_array_len] =3D cpreg_to_kvm_id(regid= x); @@ -242,61 +242,49 @@ static void add_cpreg_to_list(gpointer key, gpointer = opaque) } } =20 -static void count_cpreg(gpointer key, gpointer opaque) +static void count_cpreg(gpointer key, gpointer value, gpointer opaque) { ARMCPU *cpu =3D opaque; - const ARMCPRegInfo *ri; - - ri =3D g_hash_table_lookup(cpu->cp_regs, key); + const ARMCPRegInfo *ri =3D value; =20 if (!(ri->type & (ARM_CP_NO_RAW | ARM_CP_ALIAS))) { cpu->cpreg_array_len++; } } =20 -static gint cpreg_key_compare(gconstpointer a, gconstpointer b, gpointer d) -{ - uint64_t aidx =3D cpreg_to_kvm_id((uintptr_t)a); - uint64_t bidx =3D cpreg_to_kvm_id((uintptr_t)b); - - if (aidx > bidx) { - return 1; - } - if (aidx < bidx) { - return -1; - } - return 0; -} - void init_cpreg_list(ARMCPU *cpu) { /* * Initialise the cpreg_tuples[] array based on the cp_regs hash. * Note that we require cpreg_tuples[] to be sorted by key ID. */ - GList *keys; int arraylen; =20 - keys =3D g_hash_table_get_keys(cpu->cp_regs); - keys =3D g_list_sort_with_data(keys, cpreg_key_compare, NULL); - cpu->cpreg_array_len =3D 0; - - g_list_foreach(keys, count_cpreg, cpu); + g_hash_table_foreach(cpu->cp_regs, count_cpreg, cpu); =20 arraylen =3D cpu->cpreg_array_len; - cpu->cpreg_indexes =3D g_new(uint64_t, arraylen); - cpu->cpreg_values =3D g_new(uint64_t, arraylen); - cpu->cpreg_vmstate_indexes =3D g_new(uint64_t, arraylen); - cpu->cpreg_vmstate_values =3D g_new(uint64_t, arraylen); - cpu->cpreg_vmstate_array_len =3D cpu->cpreg_array_len; + if (arraylen) { + cpu->cpreg_indexes =3D g_new(uint64_t, arraylen); + cpu->cpreg_values =3D g_new(uint64_t, arraylen); + cpu->cpreg_vmstate_indexes =3D g_new(uint64_t, arraylen); + cpu->cpreg_vmstate_values =3D g_new(uint64_t, arraylen); + } else { + cpu->cpreg_indexes =3D NULL; + cpu->cpreg_values =3D NULL; + cpu->cpreg_vmstate_indexes =3D NULL; + cpu->cpreg_vmstate_values =3D NULL; + } + cpu->cpreg_vmstate_array_len =3D arraylen; cpu->cpreg_array_len =3D 0; =20 - g_list_foreach(keys, add_cpreg_to_list, cpu); + g_hash_table_foreach(cpu->cp_regs, add_cpreg_to_list, cpu); =20 assert(cpu->cpreg_array_len =3D=3D arraylen); =20 - g_list_free(keys); + if (arraylen) { + qsort(cpu->cpreg_indexes, arraylen, sizeof(uint64_t), compare_u64); + } } =20 bool arm_pan_enabled(CPUARMState *env) --=20 2.43.0 From nobody Sun Sep 28 15:26:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Bake that in to the result directly. Remove CP_REG_ARM64_SYSREG_CP as unused. Reviewed-by: Manos Pitsidianakis Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- target/arm/cpregs.h | 5 ++--- target/arm/kvm-consts.h | 3 --- target/arm/helper.c | 11 +++++------ target/arm/hvf/hvf.c | 3 +-- target/arm/tcg/translate-a64.c | 6 ++---- 5 files changed, 10 insertions(+), 18 deletions(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 417d79f7ba6..a10abadb932 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -187,9 +187,8 @@ enum { ((is64) << CP_REG_AA32_64BIT_SHIFT) | \ ((cp) << 16) | ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) =20 -#define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ - (CP_REG_AA64_MASK | \ - ((cp) << CP_REG_ARM_COPROC_SHIFT) | \ +#define ENCODE_AA64_CP_REG(crn, crm, op0, op1, op2) \ + (CP_REG_AA64_MASK | CP_REG_ARM64_SYSREG | \ ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ diff --git a/target/arm/kvm-consts.h b/target/arm/kvm-consts.h index fdb305eea1a..54ae5da7ce3 100644 --- a/target/arm/kvm-consts.h +++ b/target/arm/kvm-consts.h @@ -160,9 +160,6 @@ MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A53, KVM_ARM_= TARGET_CORTEX_A53); #define CP_REG_ARM64_SYSREG_OP2_MASK 0x0000000000000007 #define CP_REG_ARM64_SYSREG_OP2_SHIFT 0 =20 -/* No kernel define but it's useful to QEMU */ -#define CP_REG_ARM64_SYSREG_CP (CP_REG_ARM64_SYSREG >> CP_REG_ARM_COPROC_S= HIFT) - MISMATCH_CHECK(CP_REG_ARM64, KVM_REG_ARM64); MISMATCH_CHECK(CP_REG_ARM_COPROC_MASK, KVM_REG_ARM_COPROC_MASK); MISMATCH_CHECK(CP_REG_ARM_COPROC_SHIFT, KVM_REG_ARM_COPROC_SHIFT); diff --git a/target/arm/helper.c b/target/arm/helper.c index 27d5ab82920..2732112ff21 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4503,7 +4503,7 @@ static void define_arm_vh_e2h_redirects_aliases(ARMCP= U *cpu) }; =20 #define K(op0, op1, crn, crm, op2) \ - ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2) + ENCODE_AA64_CP_REG(crn, crm, op0, op1, op2) =20 static const struct E2HAlias aliases[] =3D { { K(3, 0, 1, 0, 0), K(3, 4, 1, 0, 0), K(3, 5, 1, 0, 0), @@ -7396,10 +7396,9 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, cons= t ARMCPRegInfo *r, * in their AArch64 view (the .cp value may be non-zero for the * benefit of the AArch32 view). */ - if (cp =3D=3D 0 || r->state =3D=3D ARM_CP_STATE_BOTH) { - cp =3D CP_REG_ARM64_SYSREG_CP; - } - key =3D ENCODE_AA64_CP_REG(cp, r->crn, crm, r->opc0, opc1, opc2); + assert(cp =3D=3D 0 || r->state =3D=3D ARM_CP_STATE_BOTH); + cp =3D 0; + key =3D ENCODE_AA64_CP_REG(r->crn, crm, r->opc0, opc1, opc2); break; default: g_assert_not_reached(); @@ -7624,7 +7623,7 @@ void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRe= gInfo *r) } break; case ARM_CP_STATE_AA64: - assert(r->cp =3D=3D 0 || r->cp =3D=3D CP_REG_ARM64_SYSREG_CP); + assert(r->cp =3D=3D 0); break; default: g_assert_not_reached(); diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 694584cc130..6e67d89163f 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -1124,8 +1124,7 @@ static bool is_id_sysreg(uint32_t reg) =20 static uint32_t hvf_reg2cp_reg(uint32_t reg) { - return ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, - (reg >> SYSREG_CRN_SHIFT) & SYSREG_CRN_MASK, + return ENCODE_AA64_CP_REG((reg >> SYSREG_CRN_SHIFT) & SYSREG_CRN_MASK, (reg >> SYSREG_CRM_SHIFT) & SYSREG_CRM_MASK, (reg >> SYSREG_OP0_SHIFT) & SYSREG_OP0_MASK, (reg >> SYSREG_OP1_SHIFT) & SYSREG_OP1_MASK, diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 37bedc3780b..a560ef0f42c 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2466,8 +2466,7 @@ static void handle_sys(DisasContext *s, bool isread, unsigned int op0, unsigned int op1, unsigned int op= 2, unsigned int crn, unsigned int crm, unsigned int rt) { - uint32_t key =3D ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, - crn, crm, op0, op1, op2); + uint32_t key =3D ENCODE_AA64_CP_REG(crn, crm, op0, op1, op2); const ARMCPRegInfo *ri =3D get_arm_cp_reginfo(s->cp_regs, key); bool need_exit_tb =3D false; bool nv_trap_to_el2 =3D false; @@ -2603,8 +2602,7 @@ static void handle_sys(DisasContext *s, bool isread, * We don't use the EL1 register's access function, and * fine-grained-traps on EL1 also do not apply here. */ - key =3D ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, - crn, crm, op0, 0, op2); + key =3D ENCODE_AA64_CP_REG(crn, crm, op0, 0, op2); ri =3D get_arm_cp_reginfo(s->cp_regs, key); assert(ri); assert(cp_access_ok(s->current_el, ri, isread)); --=20 2.43.0 From nobody Sun Sep 28 15:26:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758896269; cv=none; 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Reviewed-by: Manos Pitsidianakis Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- target/arm/cpregs.h | 2 +- target/arm/helper.c | 4 ++-- target/arm/hvf/hvf.c | 6 +++--- target/arm/tcg/translate-a64.c | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index a10abadb932..08fc42ea571 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -187,7 +187,7 @@ enum { ((is64) << CP_REG_AA32_64BIT_SHIFT) | \ ((cp) << 16) | ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) =20 -#define ENCODE_AA64_CP_REG(crn, crm, op0, op1, op2) \ +#define ENCODE_AA64_CP_REG(op0, op1, crn, crm, op2) \ (CP_REG_AA64_MASK | CP_REG_ARM64_SYSREG | \ ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ diff --git a/target/arm/helper.c b/target/arm/helper.c index 2732112ff21..965941f04e5 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4503,7 +4503,7 @@ static void define_arm_vh_e2h_redirects_aliases(ARMCP= U *cpu) }; =20 #define K(op0, op1, crn, crm, op2) \ - ENCODE_AA64_CP_REG(crn, crm, op0, op1, op2) + ENCODE_AA64_CP_REG(op0, op1, crn, crm, op2) =20 static const struct E2HAlias aliases[] =3D { { K(3, 0, 1, 0, 0), K(3, 4, 1, 0, 0), K(3, 5, 1, 0, 0), @@ -7398,7 +7398,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, */ assert(cp =3D=3D 0 || r->state =3D=3D ARM_CP_STATE_BOTH); cp =3D 0; - key =3D ENCODE_AA64_CP_REG(r->crn, crm, r->opc0, opc1, opc2); + key =3D ENCODE_AA64_CP_REG(r->opc0, opc1, r->crn, crm, opc2); break; default: g_assert_not_reached(); diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 6e67d89163f..8b467b36638 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -1124,10 +1124,10 @@ static bool is_id_sysreg(uint32_t reg) =20 static uint32_t hvf_reg2cp_reg(uint32_t reg) { - return ENCODE_AA64_CP_REG((reg >> SYSREG_CRN_SHIFT) & SYSREG_CRN_MASK, - (reg >> SYSREG_CRM_SHIFT) & SYSREG_CRM_MASK, - (reg >> SYSREG_OP0_SHIFT) & SYSREG_OP0_MASK, + return ENCODE_AA64_CP_REG((reg >> SYSREG_OP0_SHIFT) & SYSREG_OP0_MASK, (reg >> SYSREG_OP1_SHIFT) & SYSREG_OP1_MASK, + (reg >> SYSREG_CRN_SHIFT) & SYSREG_CRN_MASK, + (reg >> SYSREG_CRM_SHIFT) & SYSREG_CRM_MASK, (reg >> SYSREG_OP2_SHIFT) & SYSREG_OP2_MASK); } =20 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index a560ef0f42c..0ec309f1ea9 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2466,7 +2466,7 @@ static void handle_sys(DisasContext *s, bool isread, unsigned int op0, unsigned int op1, unsigned int op= 2, unsigned int crn, unsigned int crm, unsigned int rt) { - uint32_t key =3D ENCODE_AA64_CP_REG(crn, crm, op0, op1, op2); + uint32_t key =3D ENCODE_AA64_CP_REG(op0, op1, crn, crm, op2); const ARMCPRegInfo *ri =3D get_arm_cp_reginfo(s->cp_regs, key); bool need_exit_tb =3D false; bool nv_trap_to_el2 =3D false; @@ -2602,7 +2602,7 @@ static void handle_sys(DisasContext *s, bool isread, * We don't use the EL1 register's access function, and * fine-grained-traps on EL1 also do not apply here. */ - key =3D ENCODE_AA64_CP_REG(crn, crm, op0, 0, op2); + key =3D ENCODE_AA64_CP_REG(op0, 0, crn, crm, op2); ri =3D get_arm_cp_reginfo(s->cp_regs, key); assert(ri); assert(cp_access_ok(s->current_el, ri, isread)); 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-410f2007372sm6338315f8f.16.2025.09.26.07.09.08 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Sep 2025 07:09:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758895750; x=1759500550; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=0POmbfKZjptMI68V/Yj5GRhXEz6mNx19mWcRvcJN0yE=; b=GqfasopWOYbC/iCHV8Yp3molCkz4aCxl4Cv0NpUU5Nokey8CiWEoprgL5cZsjlZfwn q8rc7+jy8yf4WJclff9kPsb4FfLtVVWEdyhBShneyVz7bXhDvzmeqwOzyUkLA7A7uCzt kGXT7+Ib22IJoVEa8rDUh8r1d1pk05vvCWYdWjTAYLp1kq/r42Y+XizW89G3SkuO3EyJ ahpplL4Knnwm32CYs3OsB+G0SGmDsz348psQ+XLROOwba5G+2WtXnRiOHdFA7MfMSPVA Z6f8pPUEE/LrkpaJGYujgdIaizVQQf76onLDPIvyGwEtvY1DINVVXCh3DFkiTn3IGTtb mfMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758895750; x=1759500550; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0POmbfKZjptMI68V/Yj5GRhXEz6mNx19mWcRvcJN0yE=; b=WeJ20tZUKHW7UrAOkRnCT7i+FEFDWz6B1yw2125cRJd/bXt/2asVzOAX6zranVgAK7 ygAM0Va3qtEMfrXSFHLlgLDCUxyGwu9px0OVnaMzJ7e79o91JKdDzvlbGPR/VJjoTU/F N5ROca5FWi1EpQIUY82uAJ62sr5IsLMQocw1cNME1bf+yoZ8jsqyKBrbPK7n1VFkG0Wo TMwwSWsrd8h88sx1ket7Fnx1qMIKGztKExCHW0zCkQEv8ZXCEqsu77iivQgWTWTH4M9c JsgiHKD9IZqJ0YXijI/y0udttGU7alA9C2k7VDKoochp5W8kJ5xWZ6g78wFAha8Z1Pii rJwg== X-Gm-Message-State: AOJu0YxZ2vD2RWGavEVRLFIZfxR7tqJg/Y3XxsbIDujsnGcrWttvu4eq QlD359eHacSQJnm2GtXuRat/MeSOzsPZEPL8OHEahNhhnCZ6rebTAPCIKUwbgtZLLmvfkTReAb2 CFDdr X-Gm-Gg: ASbGncu2xW296aOgPwdzKJ1LSMvo+OVm8fSpux6BS/XfoeZtWUeryrx3LvN6Xfh7eWe fUQIJjA5p880uBH4KK9pmVf+jA8jJrABm5fijpxwRDBRU0M2Yw1OKee86TmaKmA4TIpZu0VnAGL JYYjMo31ljiMrjUtsitFoqkFESMODXVCBSaGekqj8h3f1Nj17ZsMECIUp41T9L2KPzA7yHRMcpz XwMYkJNqNp50ANGLAPWcxX3PfsUHCgQo89CGuym+QxGij0kpfH9v6A8BrQR3GhvcGeUZYfHtXbX 1pHefgBoDCFO6K1UvpKu32Yspy3IeCDy0OwbMn+H0vqrNYv8ZwBqxmCOcRAVrYA4xkp6VEBoHiZ TjB6O0nIkKzC7MR+6KHsPLVSrR/RV X-Google-Smtp-Source: AGHT+IEG0RM4FOEW5MUIuY5ePxL91RklwnwqxofMc8VKLAgbbqOx5FKXZkVBPl7wL2vT6fh6eEiBDA== X-Received: by 2002:a05:6000:18a7:b0:3e9:d0a5:e436 with SMTP id ffacd0b85a97d-40e437371acmr7918055f8f.23.1758895749631; Fri, 26 Sep 2025 07:09:09 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 22/44] target/arm: Split out add_cpreg_to_hashtable_aa{32, 64} Date: Fri, 26 Sep 2025 15:08:22 +0100 Message-ID: <20250926140844.1493020-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250926140844.1493020-1-peter.maydell@linaro.org> References: <20250926140844.1493020-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758896053900116600 From: Richard Henderson The nesting level for the inner loop of define_one_arm_cp_reg was overly deep. Split out that code into two functions, for the AArch32 and AArch64 paths separately. Simplify the innermost loop to a switch statement over r->state. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- target/arm/helper.c | 147 +++++++++++++++++++++++--------------------- 1 file changed, 76 insertions(+), 71 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 965941f04e5..39f5297a1a7 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7557,6 +7557,66 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, cons= t ARMCPRegInfo *r, g_hash_table_insert(cpu->cp_regs, (gpointer)(uintptr_t)key, r2); } =20 +static void add_cpreg_to_hashtable_aa32(ARMCPU *cpu, const ARMCPRegInfo *r, + int crm, int opc1, int opc2) +{ + /* + * Under AArch32 CP registers can be common + * (same for secure and non-secure world) or banked. + */ + char *name; + + assert(!(r->type & ARM_CP_ADD_TLBI_NXS)); /* aa64 only */ + + switch (r->secure) { + case ARM_CP_SECSTATE_S: + case ARM_CP_SECSTATE_NS: + add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32, + r->secure, crm, opc1, opc2, r->name); + break; + case ARM_CP_SECSTATE_BOTH: + name =3D g_strdup_printf("%s_S", r->name); + add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32, + ARM_CP_SECSTATE_S, crm, opc1, opc2, name); + g_free(name); + add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32, + ARM_CP_SECSTATE_NS, crm, opc1, opc2, r->nam= e); + break; + default: + g_assert_not_reached(); + } +} + +static void add_cpreg_to_hashtable_aa64(ARMCPU *cpu, const ARMCPRegInfo *r, + int crm, int opc1, int opc2) +{ + if ((r->type & ARM_CP_ADD_TLBI_NXS) && + cpu_isar_feature(aa64_xs, cpu)) { + /* + * This is a TLBI insn which has an NXS variant. The + * NXS variant is at the same encoding except that + * crn is +1, and has the same behaviour except for + * fine-grained trapping. Add the NXS insn here and + * then fall through to add the normal register. + * add_cpreg_to_hashtable() copies the cpreg struct + * and name that it is passed, so it's OK to use + * a local struct here. + */ + ARMCPRegInfo nxs_ri =3D *r; + g_autofree char *name =3D g_strdup_printf("%sNXS", r->name); + + assert(nxs_ri.crn < 0xf); + nxs_ri.crn++; + if (nxs_ri.fgt) { + nxs_ri.fgt |=3D R_FGT_NXS_MASK; + } + add_cpreg_to_hashtable(cpu, &nxs_ri, ARM_CP_STATE_AA64, + ARM_CP_SECSTATE_NS, crm, opc1, opc2, name); + } + + add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA64, ARM_CP_SECSTATE_NS, + crm, opc1, opc2, r->name); +} =20 void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *r) { @@ -7584,14 +7644,12 @@ void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCP= RegInfo *r) * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of * the register, if any. */ - int crm, opc1, opc2; int crmmin =3D (r->crm =3D=3D CP_ANY) ? 0 : r->crm; int crmmax =3D (r->crm =3D=3D CP_ANY) ? 15 : r->crm; int opc1min =3D (r->opc1 =3D=3D CP_ANY) ? 0 : r->opc1; int opc1max =3D (r->opc1 =3D=3D CP_ANY) ? 7 : r->opc1; int opc2min =3D (r->opc2 =3D=3D CP_ANY) ? 0 : r->opc2; int opc2max =3D (r->opc2 =3D=3D CP_ANY) ? 7 : r->opc2; - CPState state; =20 /* 64 bit registers have only CRm and Opc1 fields */ assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn))); @@ -7688,75 +7746,22 @@ void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCP= RegInfo *r) } } =20 - for (crm =3D crmmin; crm <=3D crmmax; crm++) { - for (opc1 =3D opc1min; opc1 <=3D opc1max; opc1++) { - for (opc2 =3D opc2min; opc2 <=3D opc2max; opc2++) { - for (state =3D ARM_CP_STATE_AA32; - state <=3D ARM_CP_STATE_AA64; state++) { - if (r->state !=3D state && r->state !=3D ARM_CP_STATE_= BOTH) { - continue; - } - if ((r->type & ARM_CP_ADD_TLBI_NXS) && - cpu_isar_feature(aa64_xs, cpu)) { - /* - * This is a TLBI insn which has an NXS variant. T= he - * NXS variant is at the same encoding except that - * crn is +1, and has the same behaviour except for - * fine-grained trapping. Add the NXS insn here and - * then fall through to add the normal register. - * add_cpreg_to_hashtable() copies the cpreg struct - * and name that it is passed, so it's OK to use - * a local struct here. - */ - ARMCPRegInfo nxs_ri =3D *r; - g_autofree char *name =3D g_strdup_printf("%sNXS",= r->name); - - assert(state =3D=3D ARM_CP_STATE_AA64); - assert(nxs_ri.crn < 0xf); - nxs_ri.crn++; - if (nxs_ri.fgt) { - nxs_ri.fgt |=3D R_FGT_NXS_MASK; - } - add_cpreg_to_hashtable(cpu, &nxs_ri, state, - ARM_CP_SECSTATE_NS, - crm, opc1, opc2, name); - } - if (state =3D=3D ARM_CP_STATE_AA32) { - /* - * Under AArch32 CP registers can be common - * (same for secure and non-secure world) or banke= d. - */ - char *name; - - switch (r->secure) { - case ARM_CP_SECSTATE_S: - case ARM_CP_SECSTATE_NS: - add_cpreg_to_hashtable(cpu, r, state, - r->secure, crm, opc1, o= pc2, - r->name); - break; - case ARM_CP_SECSTATE_BOTH: - name =3D g_strdup_printf("%s_S", r->name); - add_cpreg_to_hashtable(cpu, r, state, - ARM_CP_SECSTATE_S, - crm, opc1, opc2, name); - g_free(name); - add_cpreg_to_hashtable(cpu, r, state, - ARM_CP_SECSTATE_NS, - crm, opc1, opc2, r->nam= e); - break; - default: - g_assert_not_reached(); - } - } else { - /* - * AArch64 registers get mapped to non-secure inst= ance - * of AArch32 - */ - add_cpreg_to_hashtable(cpu, r, state, - ARM_CP_SECSTATE_NS, - crm, opc1, opc2, r->name); - } + for (int crm =3D crmmin; crm <=3D crmmax; crm++) { + for (int opc1 =3D opc1min; opc1 <=3D opc1max; opc1++) { + for (int opc2 =3D opc2min; opc2 <=3D opc2max; opc2++) { + switch (r->state) { + case ARM_CP_STATE_AA32: + add_cpreg_to_hashtable_aa32(cpu, r, crm, opc1, opc2); + break; + case ARM_CP_STATE_AA64: + add_cpreg_to_hashtable_aa64(cpu, r, crm, opc1, opc2); + break; + case ARM_CP_STATE_BOTH: + add_cpreg_to_hashtable_aa32(cpu, r, crm, opc1, opc2); + add_cpreg_to_hashtable_aa64(cpu, r, crm, opc1, opc2); + break; + default: + g_assert_not_reached(); } } } --=20 2.43.0 From nobody Sun Sep 28 15:26:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758896380; cv=none; d=zohomail.com; s=zohoarc; b=hAbxmCkXEpDdIyVDb2f2FOupAcYNyTkOJ9604FJdTv6KIynIFxLhqhpeFlTG5Kns/wSxGTfu46/E4QLIo+yEwCXEKVFxQWZBpAAQTbjTt643dGAuP3u12uISxMpyt4BRyLbBzpeTHqtKZTYFyH9S08kouJ+8QTP1BkHdSkWkBas= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758896380; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=NF7qfHw2I9shSn+UnJOx9Y2E4M/oZXJIVSezgmWGofU=; b=hm8l+Vi1iD5Cb1o3VT3taiQZ2cZ2RsDOqjJMnWriOmdau1VcEAYHD1zq2KQGxFXvdvzorc8LqoLd0iFOzlY68L91oKLGkDiE1Rdq9l1vCrT2PZt49ElBtUk8ZEQVk1T5cj8p1kfQG/Zzmg/iBq177m13dEtJEmOiOySIHaqLu18= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1758896380474594.4621392131086; Fri, 26 Sep 2025 07:19:40 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v298w-00082t-91; Fri, 26 Sep 2025 10:09:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v298t-0007uo-5E for qemu-devel@nongnu.org; Fri, 26 Sep 2025 10:09:48 -0400 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1v298T-0005i8-Bm for qemu-devel@nongnu.org; Fri, 26 Sep 2025 10:09:46 -0400 Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-46b7bf21fceso16761575e9.3 for ; Fri, 26 Sep 2025 07:09:15 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-410f2007372sm6338315f8f.16.2025.09.26.07.09.09 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Sep 2025 07:09:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758895750; x=1759500550; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=NF7qfHw2I9shSn+UnJOx9Y2E4M/oZXJIVSezgmWGofU=; b=C6gTO6csZMO87vybUy3Pa1CRHqosUPBJnynqUJTDPyWy4EJWlU+TCOu5v3TKvWOdfl Rg7F5vpmW+atShiUcsCWGv/iwh6YovEwU6CNUCESejQ8LOP2/6RjCYI5s5P2msDKHo8N 0sDg16liSZFCrNAdLVXXopGU4kOIV+lI0FTfhWDjPMyjwpAe4b2YsVad1TrivbHWpK1x Z4+3wcMWAICyYk2VLQ4muLMarj8UmDObbQvvf8G2KFsgKZ+NlPYBmgQrMltANVOPgTaG hMPbPVbDZujvBMDgFBVeFpbOuJD+YIw8lxiAG04mAhJhXnxjZS4G2RLVcid3Y8magzOU 8pJA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758895750; x=1759500550; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NF7qfHw2I9shSn+UnJOx9Y2E4M/oZXJIVSezgmWGofU=; b=REOxqYleHM3bhxQyQrCkxSjIAofQDy/RcIC9Lqxl38Pgnzc0pS31lQxPG0CcHocxj9 LpuSs3abDpnEBko8WqupCPk9IGQU4FlP4FMHn1o4BstXPLp2wRJXgtDhP41+cjvX2AuJ +XSTvK+5htwEEOR0/6b77G+zSZwesQixKm/anrjveSEb84TtRWtw79dD4wHGxKv0JypQ hXNJAORbGbMavotlcdZw5YUTCbt9+VOj9J8osX35gx82IlbatDoMxwmHfcW361xFHfb/ eshrivF+fUDHnvwDZuDay4KZkksYL0P0JSZhD+0SoTud+0+pADGPR8Ce75ySjJjvqAYF y4AQ== X-Gm-Message-State: AOJu0Yz8ulJl1PqeKMAHx29kv/eB6GlmwGz1O7SwhwwwDeKJNdUf9eHx FEeG0tb7rUwM0CJrq/cSGaivTiSlXL8lRDrGpuYggtSedaaCrcAXn41wm9g0R4ZXvWmbd7ndUr3 kJRRg X-Gm-Gg: ASbGnctPNi/eTw/N8BeKZH+/3xoBHCM76dUaZB7NCMbhjc7JUFTeReFbAf59bQxSebB 2joeeESEXxozNVDdXDeIe9H1Qucv0j01EwTGIzCY0Ncp3ATbYjwsBGjipnN+fk8MJOLAw3+iQUK QIOnMASdwSbKoxhfyzMuWfo2GCLZvNWWWqug9r5OFzHUDa0VyZ1M3USvj4q4brjF6vm6a6lZohq z+arQQQQ1jWQRND0bMhheaZw2KI1WMFsEuDd0zbGAwkPAzSs2QGzz6cRQs0T0Y2Cig5jqNTGzHA 2Ye2wSw5b5pPtEkXVgwPpeGpke5g+klmOIsL8xJuqAc4n5BgFrBYzELsI2A5w9sE/3c3FLJ0Q7c J42w3rk5pJVJVQXTo74jLIy4Rp8FiKrKVyitEHgM= X-Google-Smtp-Source: AGHT+IFxyQ5fRCh29XFQpbTbmUSgvhsUcG0GWGRa4w0LmXlGkrdUj9H57dbB2qGDFeeb9CopjtsdBw== X-Received: by 2002:a05:6000:1a8c:b0:3b9:148b:e78 with SMTP id ffacd0b85a97d-40e4cd576f0mr7648851f8f.53.1758895750498; Fri, 26 Sep 2025 07:09:10 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 23/44] target/arm: Improve asserts in define_one_arm_cp_reg Date: Fri, 26 Sep 2025 15:08:23 +0100 Message-ID: <20250926140844.1493020-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250926140844.1493020-1-peter.maydell@linaro.org> References: <20250926140844.1493020-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758896382467116600 From: Richard Henderson Reject ARM_CP_64BIT with ARM_CP_STATE_BOTH, because encoding constrains prevent it from working. Remove some extra parens; distribute ! across && to simplify. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- target/arm/helper.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 39f5297a1a7..8c2b7e037e8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7651,12 +7651,17 @@ void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCP= RegInfo *r) int opc2min =3D (r->opc2 =3D=3D CP_ANY) ? 0 : r->opc2; int opc2max =3D (r->opc2 =3D=3D CP_ANY) ? 7 : r->opc2; =20 - /* 64 bit registers have only CRm and Opc1 fields */ - assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn))); + /* + * AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless. + * Moreover, the encoding test just following in general prevents + * shared encoding so ARM_CP_STATE_BOTH won't work either. + */ + assert(r->state =3D=3D ARM_CP_STATE_AA32 || !(r->type & ARM_CP_64BIT)); + /* AArch32 64-bit registers have only CRm and Opc1 fields. */ + assert(!(r->type & ARM_CP_64BIT) || !(r->opc2 || r->crn)); /* op0 only exists in the AArch64 encodings */ - assert((r->state !=3D ARM_CP_STATE_AA32) || (r->opc0 =3D=3D 0)); - /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */ - assert((r->state !=3D ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT)); + assert(r->state !=3D ARM_CP_STATE_AA32 || r->opc0 =3D=3D 0); + /* * This API is only for Arm's system coprocessors (14 and 15) or * (M-profile or v7A-and-earlier only) for implementation defined --=20 2.43.0 From nobody Sun Sep 28 15:26:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758896026; cv=none; d=zohomail.com; s=zohoarc; b=Ryj4cQTR65CchaDi7Ayql1Tay3KX7pQUD24V4AASScuZvwIBMaV3H2ftynGzZQnN4Q+SDbKtPO5GwugUyVbf/tDLlS/dvpCVDBhfIbkue/qXaKX9kiJk/aCpaHPLn3vHdD2ZcrdPSuNu5QlavMQIPLm2J6AUvPEFJVXCBAU8ED4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758896026; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=Eg6nfok1GwG5zNCB5mi0v4fpJCgjR6fP+MDXEr0QDn8=; b=IEqNlgQ7QzyJuWN9Giic3X/D16q7QixdZynUKlnbCZ5Ek3pWRkKjBBmkADM4G4bqruySGrUbLvyfSO6xCzwiHRset9NSeUr8cxgUx4UTzt9mdlrGF/IWx/622lgeRb1bz4yMXo2fiIbtCdLeyZ6fCPi7h5VWYzxeI35JEv6ZgZg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 175889602611561.17237825582299; Fri, 26 Sep 2025 07:13:46 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v299t-0000ht-3t; Fri, 26 Sep 2025 10:10:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v298x-00086U-3E for qemu-devel@nongnu.org; Fri, 26 Sep 2025 10:09:51 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1v298T-0005id-Vj for qemu-devel@nongnu.org; Fri, 26 Sep 2025 10:09:49 -0400 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-45dd505a1dfso12675085e9.2 for ; Fri, 26 Sep 2025 07:09:13 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-410f2007372sm6338315f8f.16.2025.09.26.07.09.10 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Sep 2025 07:09:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758895751; x=1759500551; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Eg6nfok1GwG5zNCB5mi0v4fpJCgjR6fP+MDXEr0QDn8=; b=LeokCobNN2gp/0NarPHbAF0esq95H/z1PPXftGy66PLQIn6juFTEvf+KR4l3L6mQa8 CbxvXoEei4jDtCb21QivFDfXDMRvjB5dGoeYhtUBLtQwSbOXCMDfJVeybp+mUPiJbT7t o+XAlxNdED/8kGQspC5F/bxW3QWyONdXwz/re50Cd5HVPDL/EBmb23Y3JeuOCX/34Lu+ rZE0oVoMHiOeXBPUTU06ceOMvKfpSsyMPZmSlbfeCi8OtyQ1ctxOvDInNQxYdwmQWg/d 7P0jT++R97ffW/EXkKbR+QxzW8zg1GNCoSKEi5kEI694/mpCUxUXcoaLYVe9IgyoWbZU 7P6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758895751; x=1759500551; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Eg6nfok1GwG5zNCB5mi0v4fpJCgjR6fP+MDXEr0QDn8=; b=eRuDWMrQ414nKWfgufnZ0oOPUSJcgG/Sk7fDyCXEYNX1AlcbfiMMLSG4D/fNwox8dx 0r7rNF/WmEQmLecoXsZS+YKeo1FxYKehYh2eSLIFbrY/WbZy8IE1wckr7jX71bOGfcQc FgwC37MPwRgCUwOVCLfnGFI0tCqMThuljKsosekg07uZaioWM+oet+nOtIr4O5paZaQu oxjkql0UXz6KKeoxmm+2kRFaXvdVvCKUZrv4WDTzi3QTx5Vp2c23JB6ykH45AL/JmfiU 1m5K1EnPn8KExXoMtz6lOYSnimwi20jGsrWAXn7UjJnCmCINGy/p4iHLqHmAmcY2HXEB XNkg== X-Gm-Message-State: AOJu0YyCEYUa34VnkhF3VQdfXStRZiafp7RCJuO7anZ4ZH8Y42NS0/YO OghsDYasv92+maff1T+XEGw7JTZboQOhsYR1HlPOyS6/ytRHCNfChi04eQx0ya4J5F+O1BWI6HY iG4P1 X-Gm-Gg: ASbGncuzlWnJpoHdccc8SCosUdB/xvqfpAFFvPDpuXNhoP+jDninTXfDPmyKB9bI/9t tORXAgNQt5jIi8Id+4BCfo/3WNVI3f8Dl0TiEp95dQjr4o4RT+n/KncIstLH06vp7dvIYpWR+83 t/o2dDv167mK632HmzbHedAopiXGRXua5lJaAJszgyYe0kFAZj3eNX0ycJo3dMyj5CPOlu7Iy6A Dyg0HFJlwQziEHjyPRmRXSd0ka1KA+qwlAe0pBIMgwtbo32AYpHitKo8VmH02dpLBO6XU0qIRwm i16EQQHuCYhzDGSeBNJPmzSN+abEq4z+df8WJaR8TJ1HyBvSGLDOusSeo9sTCjZQ0DHNO+zfsti 1D9K3hcFBy6GiWWbpKKsIgsqyNkCo X-Google-Smtp-Source: AGHT+IGSFhAOg0W+ArWQFeAHzr1Q9MIEFOMWR4NbiA8VLX11MgExdYuPGde0PLZN65BKBaIhb+tiEA== X-Received: by 2002:a05:600c:310c:b0:46e:21c8:ad37 with SMTP id 5b1f17b1804b1-46e35d550acmr55983085e9.25.1758895751486; Fri, 26 Sep 2025 07:09:11 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 24/44] target/arm: Move cp processing to define_one_arm_cp_reg Date: Fri, 26 Sep 2025 15:08:24 +0100 Message-ID: <20250926140844.1493020-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250926140844.1493020-1-peter.maydell@linaro.org> References: <20250926140844.1493020-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758896027885116600 From: Richard Henderson Processing of cp was split between add_cpreg_to_hashtable and define_one_arm_cp_reg. Unify it all to the top-level function. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- target/arm/helper.c | 53 +++++++++++++++++++-------------------------- 1 file changed, 22 insertions(+), 31 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 8c2b7e037e8..f0e423e623b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7368,7 +7368,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) */ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, CPState state, CPSecureState secstate, - int crm, int opc1, int opc2, + int cp, int crm, int opc1, int opc2, const char *name) { CPUARMState *env =3D &cpu->env; @@ -7376,28 +7376,14 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, con= st ARMCPRegInfo *r, ARMCPRegInfo *r2; bool is64 =3D r->type & ARM_CP_64BIT; bool ns =3D secstate & ARM_CP_SECSTATE_NS; - int cp =3D r->cp; size_t name_len; bool make_const; =20 switch (state) { case ARM_CP_STATE_AA32: - /* We assume it is a cp15 register if the .cp field is left unset.= */ - if (cp =3D=3D 0 && r->state =3D=3D ARM_CP_STATE_BOTH) { - cp =3D 15; - } key =3D ENCODE_CP_REG(cp, is64, ns, r->crn, crm, opc1, opc2); break; case ARM_CP_STATE_AA64: - /* - * To allow abbreviation of ARMCPRegInfo definitions, we treat - * cp =3D=3D 0 as equivalent to the value for "standard guest-visi= ble - * sysreg". STATE_BOTH definitions are also always "standard sysr= eg" - * in their AArch64 view (the .cp value may be non-zero for the - * benefit of the AArch32 view). - */ - assert(cp =3D=3D 0 || r->state =3D=3D ARM_CP_STATE_BOTH); - cp =3D 0; key =3D ENCODE_AA64_CP_REG(r->opc0, opc1, r->crn, crm, opc2); break; default: @@ -7558,7 +7544,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, } =20 static void add_cpreg_to_hashtable_aa32(ARMCPU *cpu, const ARMCPRegInfo *r, - int crm, int opc1, int opc2) + int cp, int crm, int opc1, int opc= 2) { /* * Under AArch32 CP registers can be common @@ -7571,16 +7557,16 @@ static void add_cpreg_to_hashtable_aa32(ARMCPU *cpu= , const ARMCPRegInfo *r, switch (r->secure) { case ARM_CP_SECSTATE_S: case ARM_CP_SECSTATE_NS: - add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32, - r->secure, crm, opc1, opc2, r->name); + add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32, r->secure, + cp, crm, opc1, opc2, r->name); break; case ARM_CP_SECSTATE_BOTH: name =3D g_strdup_printf("%s_S", r->name); - add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32, - ARM_CP_SECSTATE_S, crm, opc1, opc2, name); + add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32, ARM_CP_SECSTATE_= S, + cp, crm, opc1, opc2, name); g_free(name); - add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32, - ARM_CP_SECSTATE_NS, crm, opc1, opc2, r->nam= e); + add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32, ARM_CP_SECSTATE_= NS, + cp, crm, opc1, opc2, r->name); break; default: g_assert_not_reached(); @@ -7611,11 +7597,11 @@ static void add_cpreg_to_hashtable_aa64(ARMCPU *cpu= , const ARMCPRegInfo *r, nxs_ri.fgt |=3D R_FGT_NXS_MASK; } add_cpreg_to_hashtable(cpu, &nxs_ri, ARM_CP_STATE_AA64, - ARM_CP_SECSTATE_NS, crm, opc1, opc2, name); + ARM_CP_SECSTATE_NS, 0, crm, opc1, opc2, nam= e); } =20 add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA64, ARM_CP_SECSTATE_NS, - crm, opc1, opc2, r->name); + 0, crm, opc1, opc2, r->name); } =20 void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *r) @@ -7650,6 +7636,7 @@ void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRe= gInfo *r) int opc1max =3D (r->opc1 =3D=3D CP_ANY) ? 7 : r->opc1; int opc2min =3D (r->opc2 =3D=3D CP_ANY) ? 0 : r->opc2; int opc2max =3D (r->opc2 =3D=3D CP_ANY) ? 7 : r->opc2; + int cp =3D r->cp; =20 /* * AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless. @@ -7672,21 +7659,25 @@ void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCP= RegInfo *r) */ switch (r->state) { case ARM_CP_STATE_BOTH: - /* 0 has a special meaning, but otherwise the same rules as AA32. = */ - if (r->cp =3D=3D 0) { + /* + * If the cp field is left unset, assume cp15. + * Otherwise apply the same rules as AA32. + */ + if (cp =3D=3D 0) { + cp =3D 15; break; } /* fall through */ case ARM_CP_STATE_AA32: if (arm_feature(&cpu->env, ARM_FEATURE_V8) && !arm_feature(&cpu->env, ARM_FEATURE_M)) { - assert(r->cp >=3D 14 && r->cp <=3D 15); + assert(cp >=3D 14 && cp <=3D 15); } else { - assert(r->cp < 8 || (r->cp >=3D 14 && r->cp <=3D 15)); + assert(cp < 8 || (cp >=3D 14 && cp <=3D 15)); } break; case ARM_CP_STATE_AA64: - assert(r->cp =3D=3D 0); + assert(cp =3D=3D 0); break; default: g_assert_not_reached(); @@ -7756,13 +7747,13 @@ void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCP= RegInfo *r) for (int opc2 =3D opc2min; opc2 <=3D opc2max; opc2++) { switch (r->state) { case ARM_CP_STATE_AA32: - add_cpreg_to_hashtable_aa32(cpu, r, crm, opc1, opc2); + add_cpreg_to_hashtable_aa32(cpu, r, cp, crm, opc1, opc= 2); break; case ARM_CP_STATE_AA64: add_cpreg_to_hashtable_aa64(cpu, r, crm, opc1, opc2); break; case ARM_CP_STATE_BOTH: - add_cpreg_to_hashtable_aa32(cpu, r, crm, opc1, opc2); + add_cpreg_to_hashtable_aa32(cpu, r, cp, crm, opc1, opc= 2); add_cpreg_to_hashtable_aa64(cpu, r, crm, opc1, opc2); break; default: --=20 2.43.0 From nobody Sun Sep 28 15:26:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758896298; cv=none; d=zohomail.com; s=zohoarc; b=bp/L/xCxQSV1MvOTPsEDR7oXm1GE9oObCnVFKs3tTr4LMy49qO9xHqpNrSPvGM9cgDFpGS/lFKVgcfrZlLpgFIxMSiqCI+fzCJBv68vInGcrS4WxS3rEczwqRK0z/JyexXb5F+aDYLMl2xVRiXXLNa3rgH5w5pHj27cxSyK7ZZ8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758896298; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=rpIrhuYE6q9Jr9VMOg9Sf2KgkjnAL/weTQU2KUeBzTI=; b=VwUwenmGK4muz0IC3B3pBRBPV8NIKacgtqEWdEy8zBtaRArPsiHRYpRKQJbtiq6SU+fD5BCYyH1YlX0e6Mziftct9Sji6htKdnQIupNgbGrNvAYeVja5U/cgWE9kfsOPZ6hFwtCAOEQYxMiBBpyZvqslWsBpmgfS0ZGqImcq0uc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1758896298625339.4301886431434; Fri, 26 Sep 2025 07:18:18 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v299n-0000Mb-8j; Fri, 26 Sep 2025 10:10:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v298t-0007w3-Nr for qemu-devel@nongnu.org; Fri, 26 Sep 2025 10:09:48 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1v298U-0005ix-0p for qemu-devel@nongnu.org; Fri, 26 Sep 2025 10:09:46 -0400 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-46e317bc647so15092255e9.2 for ; Fri, 26 Sep 2025 07:09:15 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- target/arm/helper.c | 123 +++++++++++++++++++++++--------------------- 1 file changed, 64 insertions(+), 59 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index f0e423e623b..ade16138e75 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7377,7 +7377,6 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, bool is64 =3D r->type & ARM_CP_64BIT; bool ns =3D secstate & ARM_CP_SECSTATE_NS; size_t name_len; - bool make_const; =20 switch (state) { case ARM_CP_STATE_AA32: @@ -7398,32 +7397,6 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, cons= t ARMCPRegInfo *r, } } =20 - /* - * Eliminate registers that are not present because the EL is missing. - * Doing this here makes it easier to put all registers for a given - * feature into the same ARMCPRegInfo array and define them all at onc= e. - */ - make_const =3D false; - if (arm_feature(env, ARM_FEATURE_EL3)) { - /* - * An EL2 register without EL2 but with EL3 is (usually) RES0. - * See rule RJFFP in section D1.1.3 of DDI0487H.a. - */ - int min_el =3D ctz32(r->access) / 2; - if (min_el =3D=3D 2 && !arm_feature(env, ARM_FEATURE_EL2)) { - if (r->type & ARM_CP_EL3_NO_EL2_UNDEF) { - return; - } - make_const =3D !(r->type & ARM_CP_EL3_NO_EL2_KEEP); - } - } else { - CPAccessRights max_el =3D (arm_feature(env, ARM_FEATURE_EL2) - ? PL2_RW : PL1_RW); - if ((r->access & max_el) =3D=3D 0) { - return; - } - } - /* Combine cpreg and name into one allocation. */ name_len =3D strlen(name) + 1; r2 =3D g_malloc(sizeof(*r2) + name_len); @@ -7441,38 +7414,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, cons= t ARMCPRegInfo *r, r2->state =3D state; r2->secure =3D secstate; =20 - if (make_const) { - /* This should not have been a very special register to begin. */ - int old_special =3D r2->type & ARM_CP_SPECIAL_MASK; - assert(old_special =3D=3D 0 || old_special =3D=3D ARM_CP_NOP); - /* - * Set the special function to CONST, retaining the other flags. - * This is important for e.g. ARM_CP_SVE so that we still - * take the SVE trap if CPTR_EL3.EZ =3D=3D 0. - */ - r2->type =3D (r2->type & ~ARM_CP_SPECIAL_MASK) | ARM_CP_CONST; - /* - * Usually, these registers become RES0, but there are a few - * special cases like VPIDR_EL2 which have a constant non-zero - * value with writes ignored. - */ - if (!(r->type & ARM_CP_EL3_NO_EL2_C_NZ)) { - r2->resetvalue =3D 0; - } - /* - * ARM_CP_CONST has precedence, so removing the callbacks and - * offsets are not strictly necessary, but it is potentially - * less confusing to debug later. - */ - r2->readfn =3D NULL; - r2->writefn =3D NULL; - r2->raw_readfn =3D NULL; - r2->raw_writefn =3D NULL; - r2->resetfn =3D NULL; - r2->fieldoffset =3D 0; - r2->bank_fieldoffsets[0] =3D 0; - r2->bank_fieldoffsets[1] =3D 0; - } else { + { bool isbanked =3D r->bank_fieldoffsets[0] && r->bank_fieldoffsets[= 1]; =20 if (isbanked) { @@ -7637,6 +7579,8 @@ void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRe= gInfo *r) int opc2min =3D (r->opc2 =3D=3D CP_ANY) ? 0 : r->opc2; int opc2max =3D (r->opc2 =3D=3D CP_ANY) ? 7 : r->opc2; int cp =3D r->cp; + ARMCPRegInfo r_const; + CPUARMState *env =3D &cpu->env; =20 /* * AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless. @@ -7742,6 +7686,67 @@ void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPR= egInfo *r) } } =20 + /* + * Eliminate registers that are not present because the EL is missing. + * Doing this here makes it easier to put all registers for a given + * feature into the same ARMCPRegInfo array and define them all at onc= e. + */ + if (arm_feature(env, ARM_FEATURE_EL3)) { + /* + * An EL2 register without EL2 but with EL3 is (usually) RES0. + * See rule RJFFP in section D1.1.3 of DDI0487H.a. + */ + int min_el =3D ctz32(r->access) / 2; + if (min_el =3D=3D 2 && !arm_feature(env, ARM_FEATURE_EL2)) { + if (r->type & ARM_CP_EL3_NO_EL2_UNDEF) { + return; + } + if (!(r->type & ARM_CP_EL3_NO_EL2_KEEP)) { + /* This should not have been a very special register. */ + int old_special =3D r->type & ARM_CP_SPECIAL_MASK; + assert(old_special =3D=3D 0 || old_special =3D=3D ARM_CP_N= OP); + + r_const =3D *r; + + /* + * Set the special function to CONST, retaining the other = flags. + * This is important for e.g. ARM_CP_SVE so that we still + * take the SVE trap if CPTR_EL3.EZ =3D=3D 0. + */ + r_const.type =3D (r->type & ~ARM_CP_SPECIAL_MASK) | ARM_CP= _CONST; + /* + * Usually, these registers become RES0, but there are a f= ew + * special cases like VPIDR_EL2 which have a constant non-= zero + * value with writes ignored. + */ + if (!(r->type & ARM_CP_EL3_NO_EL2_C_NZ)) { + r_const.resetvalue =3D 0; + } + /* + * ARM_CP_CONST has precedence, so removing the callbacks = and + * offsets are not strictly necessary, but it is potential= ly + * less confusing to debug later. + */ + r_const.readfn =3D NULL; + r_const.writefn =3D NULL; + r_const.raw_readfn =3D NULL; + r_const.raw_writefn =3D NULL; + r_const.resetfn =3D NULL; + r_const.fieldoffset =3D 0; + r_const.bank_fieldoffsets[0] =3D 0; + r_const.bank_fieldoffsets[1] =3D 0; + + r =3D &r_const; + } + } + } else { + CPAccessRights max_el =3D (arm_feature(env, ARM_FEATURE_EL2) + ? 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Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 [PMM: added comment about CRN key field increment] Signed-off-by: Peter Maydell --- target/arm/helper.c | 40 ++++++++++++++++++++-------------------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index ade16138e75..8a8fa8c40e9 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7369,26 +7369,13 @@ void register_cp_regs_for_features(ARMCPU *cpu) static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, CPState state, CPSecureState secstate, int cp, int crm, int opc1, int opc2, - const char *name) + const char *name, uint32_t key) { CPUARMState *env =3D &cpu->env; - uint32_t key; ARMCPRegInfo *r2; - bool is64 =3D r->type & ARM_CP_64BIT; bool ns =3D secstate & ARM_CP_SECSTATE_NS; size_t name_len; =20 - switch (state) { - case ARM_CP_STATE_AA32: - key =3D ENCODE_CP_REG(cp, is64, ns, r->crn, crm, opc1, opc2); - break; - case ARM_CP_STATE_AA64: - key =3D ENCODE_AA64_CP_REG(r->opc0, opc1, r->crn, crm, opc2); - break; - default: - g_assert_not_reached(); - } - /* Overriding of an existing definition must be explicitly requested. = */ if (!(r->type & ARM_CP_OVERRIDE)) { const ARMCPRegInfo *oldreg =3D get_arm_cp_reginfo(cpu->cp_regs, ke= y); @@ -7493,22 +7480,28 @@ static void add_cpreg_to_hashtable_aa32(ARMCPU *cpu= , const ARMCPRegInfo *r, * (same for secure and non-secure world) or banked. */ char *name; + bool is64 =3D r->type & ARM_CP_64BIT; + uint32_t key =3D ENCODE_CP_REG(cp, is64, 0, r->crn, crm, opc1, opc2); =20 assert(!(r->type & ARM_CP_ADD_TLBI_NXS)); /* aa64 only */ =20 switch (r->secure) { - case ARM_CP_SECSTATE_S: case ARM_CP_SECSTATE_NS: + key |=3D CP_REG_AA32_NS_MASK; + /* fall through */ + case ARM_CP_SECSTATE_S: add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32, r->secure, - cp, crm, opc1, opc2, r->name); + cp, crm, opc1, opc2, r->name, key); break; case ARM_CP_SECSTATE_BOTH: name =3D g_strdup_printf("%s_S", r->name); add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32, ARM_CP_SECSTATE_= S, - cp, crm, opc1, opc2, name); + cp, crm, opc1, opc2, name, key); g_free(name); + + key |=3D CP_REG_AA32_NS_MASK; add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32, ARM_CP_SECSTATE_= NS, - cp, crm, opc1, opc2, r->name); + cp, crm, opc1, opc2, r->name, key); break; default: g_assert_not_reached(); @@ -7518,6 +7511,8 @@ static void add_cpreg_to_hashtable_aa32(ARMCPU *cpu, = const ARMCPRegInfo *r, static void add_cpreg_to_hashtable_aa64(ARMCPU *cpu, const ARMCPRegInfo *r, int crm, int opc1, int opc2) { + uint32_t key =3D ENCODE_AA64_CP_REG(r->opc0, opc1, r->crn, crm, opc2); + if ((r->type & ARM_CP_ADD_TLBI_NXS) && cpu_isar_feature(aa64_xs, cpu)) { /* @@ -7532,18 +7527,23 @@ static void add_cpreg_to_hashtable_aa64(ARMCPU *cpu= , const ARMCPRegInfo *r, */ ARMCPRegInfo nxs_ri =3D *r; g_autofree char *name =3D g_strdup_printf("%sNXS", r->name); + uint32_t nxs_key; =20 assert(nxs_ri.crn < 0xf); nxs_ri.crn++; + /* Also increment the CRN field inside the key value */ + nxs_key =3D key + (1 << CP_REG_ARM64_SYSREG_CRN_SHIFT); if (nxs_ri.fgt) { nxs_ri.fgt |=3D R_FGT_NXS_MASK; } + add_cpreg_to_hashtable(cpu, &nxs_ri, ARM_CP_STATE_AA64, - ARM_CP_SECSTATE_NS, 0, crm, opc1, opc2, nam= e); + ARM_CP_SECSTATE_NS, 0, crm, opc1, opc2, + name, nxs_key); } =20 add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA64, ARM_CP_SECSTATE_NS, - 0, crm, opc1, opc2, r->name); + 0, crm, opc1, opc2, r->name, key); } =20 void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *r) --=20 2.43.0 From nobody Sun Sep 28 15:26:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758896878; cv=none; d=zohomail.com; s=zohoarc; b=Y3Vo5NFU5SMd6cqP732ZwZVT62NuPIoW5xP8Q0vZuytavQW6X+KyG4EAE9aVeewFRxpyFDa5WiUnFZm9jB+jYGc4ST0xhlPNSMkxpehv6L/Pyiz5JENkXAhtA3jdtHlJmM/PrYWveKnLINsnpb3bXwjGPALTXaSF3XuKs74AtFA= ARC-Message-Signature: i=1; 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Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- target/arm/helper.c | 29 +++++++++++++++++++++++------ 1 file changed, 23 insertions(+), 6 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 8a8fa8c40e9..e36598e273b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7362,6 +7362,28 @@ void register_cp_regs_for_features(ARMCPU *cpu) #endif } =20 +/* + * Copy a ARMCPRegInfo structure, allocating it along with the name + * and an optional suffix to the name. + */ +static ARMCPRegInfo *alloc_cpreg(const ARMCPRegInfo *in, + const char *name, const char *suffix) +{ + size_t name_len =3D strlen(name); + size_t suff_len =3D suffix ? strlen(suffix) : 0; + ARMCPRegInfo *out =3D g_malloc(sizeof(*in) + name_len + suff_len + 1); + char *p =3D (char *)(out + 1); + + *out =3D *in; + out->name =3D p; + + memcpy(p, name, name_len + 1); + if (suffix) { + memcpy(p + name_len, suffix, suff_len + 1); + } + return out; +} + /* * Private utility function for define_one_arm_cp_reg(): * add a single reginfo struct to the hash table. @@ -7374,7 +7396,6 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, CPUARMState *env =3D &cpu->env; ARMCPRegInfo *r2; bool ns =3D secstate & ARM_CP_SECSTATE_NS; - size_t name_len; =20 /* Overriding of an existing definition must be explicitly requested. = */ if (!(r->type & ARM_CP_OVERRIDE)) { @@ -7384,11 +7405,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, cons= t ARMCPRegInfo *r, } } =20 - /* Combine cpreg and name into one allocation. */ - name_len =3D strlen(name) + 1; - r2 =3D g_malloc(sizeof(*r2) + name_len); - *r2 =3D *r; - r2->name =3D memcpy(r2 + 1, name, name_len); + r2 =3D alloc_cpreg(r, name, NULL); =20 /* * Update fields to match the instantiation, overwiting wildcards --=20 2.43.0 From nobody Sun Sep 28 15:26:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758896143; cv=none; d=zohomail.com; s=zohoarc; b=ONDdox2Tf7FM6nnm9NXCvExg5AmbWyYljJ0hUWXnaJvHP3jt8v1UOVsdMke7A5FvyrbK722hFobYaeJGIZa/gzB+tEB8mnwPROdZiFNAKoTsTGzo6egTjZRKls8TxWuBcRUsjMWsAC35Tv2U/Q3HsufjCdVjgNd8o3W/8/7RTAs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758896143; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=4KNnz1B08IfySAfOU3KxSHeljJLIDfXWvH3ivvy21G8=; b=jsn+LJWzkW80snvo/MiOrtLX7aCFXKK00HvHPiRLQo/cKogzCGw3CiCKS6E8m6uScvS7wtgr3kh6YXEvpuOlgmP5SpGJeP6A1yEtDCxtJbhkULAJUwRm01ULxUaWujq1LIiwNMlBX2Mypeq3+mi/2pVWI6vMr8kHBxkUv3zcZo0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 175889614348456.5300052452144; Fri, 26 Sep 2025 07:15:43 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v299Q-0000GC-V4; Fri, 26 Sep 2025 10:10:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v298x-00086Q-UT for qemu-devel@nongnu.org; Fri, 26 Sep 2025 10:09:54 -0400 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1v298S-0005k4-R3 for qemu-devel@nongnu.org; Fri, 26 Sep 2025 10:09:48 -0400 Received: by mail-wr1-x42c.google.com with SMTP id ffacd0b85a97d-3ee15505cdeso1851645f8f.0 for ; Fri, 26 Sep 2025 07:09:17 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-410f2007372sm6338315f8f.16.2025.09.26.07.09.14 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Sep 2025 07:09:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758895755; x=1759500555; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=4KNnz1B08IfySAfOU3KxSHeljJLIDfXWvH3ivvy21G8=; b=qztl2Hr6cESixOWiO8TP6ozy/bTFU/BP0h9a8Ixy7CNuGv122aHDNL4RL3hKAx21Gz 0VgI9jvZc6dX8P83NEUbg8uZYBuG/nzi3TGKX1e4Deq/eF0OVq7bQtXoG8F7iCxO1WwR PUbQA5gCjdvOAHH/sGWuuftglbrug0EFiwXfWrLvBMMFbYVZLMtdlVTR+u2+OHIKqGP9 6KS4GUK9SfQqQk/g6x0rDmOmXtDDMmcOzVvy/djwzj6ydgHpCFIDa5FMIEXKtXQqShX+ boqbwCohP7tEPtU658F23K5cQO4WD4L+yhYHKwyiI6D4tekqHYHjT3qXmzEvJehddwOT XtTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758895755; x=1759500555; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4KNnz1B08IfySAfOU3KxSHeljJLIDfXWvH3ivvy21G8=; b=aFtJQ8zAebG05IrGEnG6VJsp8rczJLay4dUhzQXR+mrexAM64ZqXrBC1VWXpJ5kLQv EObAC4ksmUeNmE+p5/O8zDlRddUnYyZJpjfTcKv5h9cNmnriD8JOHZ9Oo03VbzGakGu0 8VDiCRZ+NqKOxS+8xS5EugjAW5diqSRao3+PqU23TxSfQRytriPZO95Pfr41cMl4yz6n mhsbHPGMIZG5mItGVZKLuC5nDgzSBWRKvGTHqR5nFGppHtBlkyi+kIUJ++hGK/tB9+V+ fzKxl4sVg3a3ZGwJNokGyhiBzmtAbuQRkMy73lQutxS6/MeFH20v9+XJNPD1JGElF8Rm cESA== X-Gm-Message-State: AOJu0YzG0xTO0k2zbNlchT1WQp9OSItea/2oZFLht5U2e2K3M2X4iMQI fw3CeVAG6oFZx34ar9ipVG02tDLwLqOpcJrqRcgp0AV47mYbn01H+SdB8h0cZvgwjN6Jbc93kdW E7rOS X-Gm-Gg: ASbGncsb0GzM6dlpuGR5gJfeW9P9375wf95y15azRE9/+B93WjpheZheK5Imqp/MLgw RFIHTh5jOJ13JdGWpamV2Tsyk+8f0krlGJouGYQikY1UrkiecTydQ8fPBwWLWKcB3gHb1zZCbqT JFQJzEap0mF2ax4W0PL0FMIGHnBkFgFljubXHyn2KXsoTQw66J3PJCHUQfhu3PreFfElQw1KhxC go6hB6//EFmwnTCOMdpobRBY/nv8tm/9FAGbTVXNId4CupUdzKAQ9tDdjIVov4i8c4LLRo3xZrI CuIMnh8xypG7p4+lGGvZHVLa23XujXwlapRaEFeHJt80uwh1xhW5jg5yPWkT7HA5/6SdS+XTXF4 bvd/nBxFEvdr58aF6/QYFbQ0DygOr1liDbwLSyDg= X-Google-Smtp-Source: AGHT+IE4F79uO225GwLirnc6pWap0JNIcGeiVKXhrSfI4nMoOV6nTmMMnDeXxhwP41bhqXuWyqGZ7w== X-Received: by 2002:a05:6000:2184:b0:411:3c14:3ad9 with SMTP id ffacd0b85a97d-4113c14418emr4862136f8f.21.1758895755315; Fri, 26 Sep 2025 07:09:15 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 28/44] target/arm: Hoist the allocation of ARMCPRegInfo Date: Fri, 26 Sep 2025 15:08:28 +0100 Message-ID: <20250926140844.1493020-29-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250926140844.1493020-1-peter.maydell@linaro.org> References: <20250926140844.1493020-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758896145172116600 From: Richard Henderson Pass in a newly allocated structure, rather than having to dance around allocation of the name and the structure. Since we no longer have two copies of the structure handy within add_cpreg_to_hashtable, delay the writeback of concrete values over wildcards until we're done querying the wildcards. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- target/arm/helper.c | 97 ++++++++++++++++++++++----------------------- 1 file changed, 48 insertions(+), 49 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index e36598e273b..88b5ec1a5a2 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7388,13 +7388,12 @@ static ARMCPRegInfo *alloc_cpreg(const ARMCPRegInfo= *in, * Private utility function for define_one_arm_cp_reg(): * add a single reginfo struct to the hash table. */ -static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, +static void add_cpreg_to_hashtable(ARMCPU *cpu, ARMCPRegInfo *r, CPState state, CPSecureState secstate, int cp, int crm, int opc1, int opc2, - const char *name, uint32_t key) + uint32_t key) { CPUARMState *env =3D &cpu->env; - ARMCPRegInfo *r2; bool ns =3D secstate & ARM_CP_SECSTATE_NS; =20 /* Overriding of an existing definition must be explicitly requested. = */ @@ -7405,19 +7404,6 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, cons= t ARMCPRegInfo *r, } } =20 - r2 =3D alloc_cpreg(r, name, NULL); - - /* - * Update fields to match the instantiation, overwiting wildcards - * such as CP_ANY, ARM_CP_STATE_BOTH, or ARM_CP_SECSTATE_BOTH. - */ - r2->cp =3D cp; - r2->crm =3D crm; - r2->opc1 =3D opc1; - r2->opc2 =3D opc2; - r2->state =3D state; - r2->secure =3D secstate; - { bool isbanked =3D r->bank_fieldoffsets[0] && r->bank_fieldoffsets[= 1]; =20 @@ -7427,7 +7413,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, * Overwriting fieldoffset as the array is only used to define * banked registers but later only fieldoffset is used. */ - r2->fieldoffset =3D r->bank_fieldoffsets[ns]; + r->fieldoffset =3D r->bank_fieldoffsets[ns]; } if (state =3D=3D ARM_CP_STATE_AA32) { if (isbanked) { @@ -7444,19 +7430,19 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, con= st ARMCPRegInfo *r, */ if ((r->state =3D=3D ARM_CP_STATE_BOTH && ns) || (arm_feature(env, ARM_FEATURE_V8) && !ns)) { - r2->type |=3D ARM_CP_ALIAS; + r->type |=3D ARM_CP_ALIAS; } } else if ((secstate !=3D r->secure) && !ns) { /* * The register is not banked so we only want to allow * migration of the non-secure instance. */ - r2->type |=3D ARM_CP_ALIAS; + r->type |=3D ARM_CP_ALIAS; } =20 if (HOST_BIG_ENDIAN && - r->state =3D=3D ARM_CP_STATE_BOTH && r2->fieldoffset) { - r2->fieldoffset +=3D sizeof(uint32_t); + r->state =3D=3D ARM_CP_STATE_BOTH && r->fieldoffset) { + r->fieldoffset +=3D sizeof(uint32_t); } } } @@ -7468,35 +7454,46 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, con= st ARMCPRegInfo *r, * multiple times. Special registers (ie NOP/WFI) are * never migratable and not even raw-accessible. */ - if (r2->type & ARM_CP_SPECIAL_MASK) { - r2->type |=3D ARM_CP_NO_RAW; + if (r->type & ARM_CP_SPECIAL_MASK) { + r->type |=3D ARM_CP_NO_RAW; } if (((r->crm =3D=3D CP_ANY) && crm !=3D 0) || ((r->opc1 =3D=3D CP_ANY) && opc1 !=3D 0) || ((r->opc2 =3D=3D CP_ANY) && opc2 !=3D 0)) { - r2->type |=3D ARM_CP_ALIAS | ARM_CP_NO_GDB; + r->type |=3D ARM_CP_ALIAS | ARM_CP_NO_GDB; } =20 + /* + * Update fields to match the instantiation, overwiting wildcards + * such as CP_ANY, ARM_CP_STATE_BOTH, or ARM_CP_SECSTATE_BOTH. + */ + r->cp =3D cp; + r->crm =3D crm; + r->opc1 =3D opc1; + r->opc2 =3D opc2; + r->state =3D state; + r->secure =3D secstate; + /* * Check that raw accesses are either forbidden or handled. Note that * we can't assert this earlier because the setup of fieldoffset for * banked registers has to be done first. */ - if (!(r2->type & ARM_CP_NO_RAW)) { - assert(!raw_accessors_invalid(r2)); + if (!(r->type & ARM_CP_NO_RAW)) { + assert(!raw_accessors_invalid(r)); } =20 - g_hash_table_insert(cpu->cp_regs, (gpointer)(uintptr_t)key, r2); + g_hash_table_insert(cpu->cp_regs, (gpointer)(uintptr_t)key, r); } =20 -static void add_cpreg_to_hashtable_aa32(ARMCPU *cpu, const ARMCPRegInfo *r, +static void add_cpreg_to_hashtable_aa32(ARMCPU *cpu, ARMCPRegInfo *r, int cp, int crm, int opc1, int opc= 2) { /* * Under AArch32 CP registers can be common * (same for secure and non-secure world) or banked. */ - char *name; + ARMCPRegInfo *r_s; bool is64 =3D r->type & ARM_CP_64BIT; uint32_t key =3D ENCODE_CP_REG(cp, is64, 0, r->crn, crm, opc1, opc2); =20 @@ -7508,24 +7505,23 @@ static void add_cpreg_to_hashtable_aa32(ARMCPU *cpu= , const ARMCPRegInfo *r, /* fall through */ case ARM_CP_SECSTATE_S: add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32, r->secure, - cp, crm, opc1, opc2, r->name, key); + cp, crm, opc1, opc2, key); break; case ARM_CP_SECSTATE_BOTH: - name =3D g_strdup_printf("%s_S", r->name); - add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32, ARM_CP_SECSTATE_= S, - cp, crm, opc1, opc2, name, key); - g_free(name); + r_s =3D alloc_cpreg(r, r->name, "_S"); + add_cpreg_to_hashtable(cpu, r_s, ARM_CP_STATE_AA32, ARM_CP_SECSTAT= E_S, + cp, crm, opc1, opc2, key); =20 key |=3D CP_REG_AA32_NS_MASK; add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32, ARM_CP_SECSTATE_= NS, - cp, crm, opc1, opc2, r->name, key); + cp, crm, opc1, opc2, key); break; default: g_assert_not_reached(); } } =20 -static void add_cpreg_to_hashtable_aa64(ARMCPU *cpu, const ARMCPRegInfo *r, +static void add_cpreg_to_hashtable_aa64(ARMCPU *cpu, ARMCPRegInfo *r, int crm, int opc1, int opc2) { uint32_t key =3D ENCODE_AA64_CP_REG(r->opc0, opc1, r->crn, crm, opc2); @@ -7542,25 +7538,24 @@ static void add_cpreg_to_hashtable_aa64(ARMCPU *cpu= , const ARMCPRegInfo *r, * and name that it is passed, so it's OK to use * a local struct here. */ - ARMCPRegInfo nxs_ri =3D *r; - g_autofree char *name =3D g_strdup_printf("%sNXS", r->name); + ARMCPRegInfo *nxs_ri =3D alloc_cpreg(r, r->name, "NXS"); uint32_t nxs_key; =20 - assert(nxs_ri.crn < 0xf); - nxs_ri.crn++; + assert(nxs_ri->crn < 0xf); + nxs_ri->crn++; /* Also increment the CRN field inside the key value */ nxs_key =3D key + (1 << CP_REG_ARM64_SYSREG_CRN_SHIFT); - if (nxs_ri.fgt) { - nxs_ri.fgt |=3D R_FGT_NXS_MASK; + if (nxs_ri->fgt) { + nxs_ri->fgt |=3D R_FGT_NXS_MASK; } =20 - add_cpreg_to_hashtable(cpu, &nxs_ri, ARM_CP_STATE_AA64, + add_cpreg_to_hashtable(cpu, nxs_ri, ARM_CP_STATE_AA64, ARM_CP_SECSTATE_NS, 0, crm, opc1, opc2, - name, nxs_key); + nxs_key); } =20 add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA64, ARM_CP_SECSTATE_NS, - 0, crm, opc1, opc2, r->name, key); + 0, crm, opc1, opc2, key); } =20 void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *r) @@ -7767,16 +7762,20 @@ void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCP= RegInfo *r) for (int crm =3D crmmin; crm <=3D crmmax; crm++) { for (int opc1 =3D opc1min; opc1 <=3D opc1max; opc1++) { for (int opc2 =3D opc2min; opc2 <=3D opc2max; opc2++) { + ARMCPRegInfo *r2 =3D alloc_cpreg(r, r->name, NULL); + ARMCPRegInfo *r3; + switch (r->state) { case ARM_CP_STATE_AA32: - add_cpreg_to_hashtable_aa32(cpu, r, cp, crm, opc1, opc= 2); + add_cpreg_to_hashtable_aa32(cpu, r2, cp, crm, opc1, op= c2); break; case ARM_CP_STATE_AA64: - add_cpreg_to_hashtable_aa64(cpu, r, crm, opc1, opc2); + add_cpreg_to_hashtable_aa64(cpu, r2, crm, opc1, opc2); break; case ARM_CP_STATE_BOTH: - add_cpreg_to_hashtable_aa32(cpu, r, cp, crm, opc1, opc= 2); - add_cpreg_to_hashtable_aa64(cpu, r, crm, opc1, opc2); + r3 =3D alloc_cpreg(r2, r2->name, NULL); + add_cpreg_to_hashtable_aa32(cpu, r2, cp, crm, opc1, op= c2); + add_cpreg_to_hashtable_aa64(cpu, r3, crm, opc1, opc2); break; default: g_assert_not_reached(); --=20 2.43.0 From nobody Sun Sep 28 15:26:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-410f2007372sm6338315f8f.16.2025.09.26.07.09.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Sep 2025 07:09:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758895756; x=1759500556; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=EHT5aieK++hY09AXJRzSJMjJlTqqjIrNE0E91jZWOnU=; b=k3h+ezv8cGAF8VMTKNhXzbZGuJZwqKO3GMflT3qu60Tn5IOUzmOgEjgjyLeLgG4MzD 6E//d34Tolj+HHgszK9TkDveuLWYoHjB83QN8MA3joHPllr8XmJm6eNHopsZnRcjGyUg qk2BVSCMaVYU0fBMp3YqWnnJElruWn++0Bzp4xQlAt4sQGE3Ic7JAmeJgIuld4ETxbVT Xs+iP321lursVciomGoZrT6k/VVnWGEY2bQBzGwHWM79xarvbh1chqk9AoPkrxhi5DsV Rewl7qWbMmzsFEqWEh0n3gSK0Vi4zIL+4iU+P2LN1sFE3Dza1gIJDiMX3YKPvOvPl9Q3 Y26Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758895756; x=1759500556; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EHT5aieK++hY09AXJRzSJMjJlTqqjIrNE0E91jZWOnU=; b=KEH++EeuuJJ7w/6fdS6Cxj+pd37/6pHrNaLL5iKAtEPnuC3vliBwtTQtxJTEHaRB78 O4RFT/nkV4r4eHKZzTB4f7W184X6hOId2mc8CX8RD5MFC8EdZHBnz9qi6VOWufvKH7H4 qkOnZaZSI3PkP76gLfUOEoj+Q74zGuvP1k4w8IwuXP2DysD+2wvqCj3Oyiyg0i0CZwP+ xPyGc/Qk/WMuKjZs12upRi62aAAEZqU+tXW6pUEi5+UUTyVp+2X3md+JtDw+gxDZS08P E33v1x3Cj6PcCOlLSnU7KCjP/H/hQhVOp0cu7+FC+zu5c9YJE6EjGVlJEbP+k4ypWWU+ i1GQ== X-Gm-Message-State: AOJu0YxMKvGfbi00ukJzVCbgcnuTxtSqc5PWh5DFR28wq7Q1o4VZ7YOa fN9SPLNJc5l/DNc95wLuCe2u4bkfkmVvyI+lW5/mRM7sukUd2FJ6DNOjIJ+jCAxVxgd+jtsOFKK N7HQF X-Gm-Gg: ASbGnctYg4ZTEqdPduO6RSuSd6tAzoyphkwuMh2SE+gFpUdS6macImbGTdivFPm2WGc kij5DgcJJvvY3msbcl7pfzwkDh8MZFt8f6sKVIfkUMF4BmcePkXPpPot3hMBPhoX5IL3h2Ac9/X b90fWx6L/t7JIczZ2WBgzwFETIbvbSm22p3vLDD9ithVop1SBIymyivo2O8du0JAebxftg9MwM5 vzzbpv9Y0W1GZ+tpq4u95i3Ko0uUFtXOmO7Gml4uKouFVOBiBjCzqYhLNRqNSfBbMdKQ2YhQRfI UcdmCJW/0dFTLwUqCMgvcZyieWKmxmj7qY3pE0fBW86uUvH2WS3FB5BDBE9rBMNy1rjEoB97Pib z0tGBsJNjwx0dvUYvWxStjettPozOJ7cQ8Pv+zcs= X-Google-Smtp-Source: AGHT+IGvq0kJ/TJjv26NaVeMufVVCbtQ2B4xt62kq1dWQKP58KFNCUHfC6CtVr3RnjmbMCzC8UGIGA== X-Received: by 2002:a5d:5889:0:b0:3ec:98fb:d767 with SMTP id ffacd0b85a97d-40e4d9c9f15mr7510691f8f.58.1758895756215; Fri, 26 Sep 2025 07:09:16 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 29/44] target/arm: Remove name argument to alloc_cpreg Date: Fri, 26 Sep 2025 15:08:29 +0100 Message-ID: <20250926140844.1493020-30-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250926140844.1493020-1-peter.maydell@linaro.org> References: <20250926140844.1493020-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758896279245116600 From: Richard Henderson All callers now pass in->name, so take the value from there. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- target/arm/helper.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 88b5ec1a5a2..a199320f140 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7366,9 +7366,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) * Copy a ARMCPRegInfo structure, allocating it along with the name * and an optional suffix to the name. */ -static ARMCPRegInfo *alloc_cpreg(const ARMCPRegInfo *in, - const char *name, const char *suffix) +static ARMCPRegInfo *alloc_cpreg(const ARMCPRegInfo *in, const char *suffi= x) { + const char *name =3D in->name; size_t name_len =3D strlen(name); size_t suff_len =3D suffix ? strlen(suffix) : 0; ARMCPRegInfo *out =3D g_malloc(sizeof(*in) + name_len + suff_len + 1); @@ -7508,7 +7508,7 @@ static void add_cpreg_to_hashtable_aa32(ARMCPU *cpu, = ARMCPRegInfo *r, cp, crm, opc1, opc2, key); break; case ARM_CP_SECSTATE_BOTH: - r_s =3D alloc_cpreg(r, r->name, "_S"); + r_s =3D alloc_cpreg(r, "_S"); add_cpreg_to_hashtable(cpu, r_s, ARM_CP_STATE_AA32, ARM_CP_SECSTAT= E_S, cp, crm, opc1, opc2, key); =20 @@ -7538,7 +7538,7 @@ static void add_cpreg_to_hashtable_aa64(ARMCPU *cpu, = ARMCPRegInfo *r, * and name that it is passed, so it's OK to use * a local struct here. */ - ARMCPRegInfo *nxs_ri =3D alloc_cpreg(r, r->name, "NXS"); + ARMCPRegInfo *nxs_ri =3D alloc_cpreg(r, "NXS"); uint32_t nxs_key; =20 assert(nxs_ri->crn < 0xf); @@ -7762,7 +7762,7 @@ void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRe= gInfo *r) for (int crm =3D crmmin; crm <=3D crmmax; crm++) { for (int opc1 =3D opc1min; opc1 <=3D opc1max; opc1++) { for (int opc2 =3D opc2min; opc2 <=3D opc2max; opc2++) { - ARMCPRegInfo *r2 =3D alloc_cpreg(r, r->name, NULL); + ARMCPRegInfo *r2 =3D alloc_cpreg(r, NULL); ARMCPRegInfo *r3; =20 switch (r->state) { @@ -7773,7 +7773,7 @@ void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRe= gInfo *r) add_cpreg_to_hashtable_aa64(cpu, r2, crm, opc1, opc2); break; case ARM_CP_STATE_BOTH: - r3 =3D alloc_cpreg(r2, r2->name, NULL); + r3 =3D alloc_cpreg(r2, NULL); add_cpreg_to_hashtable_aa32(cpu, r2, cp, crm, opc1, op= c2); add_cpreg_to_hashtable_aa64(cpu, r3, crm, opc1, opc2); break; --=20 2.43.0 From nobody Sun Sep 28 15:26:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758897074; cv=none; d=zohomail.com; s=zohoarc; b=MABTTyzzB754OwrdDDtwlJhmbjdFdCU8543QtPav/YSJVB6/gLbAOQrORHxsscOOe0B0z5acsyQUNdkrZ8GoV6xnWqUnJ0FY9ngkHKK6ANeGaMJVZwV7/UyTm8weX9GaGZfkIOIoWCzD6I0vyjPAME/vINhrwIEH98ejpuBcny0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758897074; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=+TKuT+/hIikpcraTr+q4FAKa4j7Yp774WfscMXmqb7w=; b=nzB4h0A5pgdI6hHCw38qx30Q6Cj1XDjGuGdRpvhgi5KWHVlAwYCgFve3dEQeLVhjB7/dBYzd7ST9WP5OKCCA4cJqhGTy/LPETpTmzv5Nd77mPb8KZkhajo0StA49eGOY/0DPn9YoLI444swONzoOnhzqGVI2UQfEWm4M+Jt4olg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1758897074145450.29898122352006; Fri, 26 Sep 2025 07:31:14 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v29A7-0000p0-91; Fri, 26 Sep 2025 10:11:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v299N-00006i-A1 for qemu-devel@nongnu.org; Fri, 26 Sep 2025 10:10:17 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1v298Y-0005ki-Mf for qemu-devel@nongnu.org; Fri, 26 Sep 2025 10:10:02 -0400 Received: by mail-wr1-x432.google.com with SMTP id ffacd0b85a97d-3ece0e4c5faso2050774f8f.1 for ; Fri, 26 Sep 2025 07:09:22 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-410f2007372sm6338315f8f.16.2025.09.26.07.09.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Sep 2025 07:09:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758895757; x=1759500557; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=+TKuT+/hIikpcraTr+q4FAKa4j7Yp774WfscMXmqb7w=; b=cPxEttfe9Yg0/EX3wT1Iz7Ho3y6YJOz5dyCx7ym0OCr+HF3qpCoXNde3sEf0txu4iS QxQmEkvX76AYpLk4ydMMvuGAND/7v2pQDs52jfe+JcbjdkQbXmS2O5PuT+vadZPKwnhX QK4AslXG0VL18MPF5t1OtANDgDNF8nEeUjPZNYMZqy9dhdx7GABXWTMNQwKlp/HEg65+ y7bI5h3aD52dgM9ehHXno0FGk0sMI2bXwuZGfhmUmtd9DkoyRf7YyFana/jQVnMVZO5V jBFipTLyq8WDaYtwoLHavV+numUTt3RkVXcAUAXbaq7j9p+uRJ+/Up37bBiDGWUqPLIE nfcA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758895757; x=1759500557; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+TKuT+/hIikpcraTr+q4FAKa4j7Yp774WfscMXmqb7w=; b=K2aDUEsihvJ07xOUuYEQE8ktG27tMTkK0OHrZGf59M8KbMfGmOlEaPqF08HA4vP6Uo +cQwgU9Q7NXUobPDbvtPSzUv4QEmIIJC+LKBR/ahCL1sr8pVPp7aBkOz6/sK9xByT63F xgY0h85PAvFdBMYms1wYzGVmnUxVV/s/dHkVTeMX+OJRdWmVry++zwrdDXSMmLkL5reR fqKdcvcc0XG01nkT5SKVo5+5A8mJs6rH0gtzRo7RwnC0/s3KVNny4V46AGmoMl0pUMUA BzCdA5Y1VlJW2EVjzbMfmDlTblBDayzyYWXhlDIvhA/elHn1wM/eV1+Ep9+MK7P0XEYj CPyQ== X-Gm-Message-State: AOJu0Ywe2yLyZhsdhGVy/wNKY5DuCg6n250QYkiFve9U3RdkSHx7t4sZ Eky8+Zn1siewoAPWKi4p1g1R6Ykjugf3dLlJpp8HsZZ506hxklnNyBOFwe1SpCtgCuvkUR0N5HX m9CGm X-Gm-Gg: ASbGncukRs4YKSys8L0mLH9EWUnDd2ukg/442Bk5Bja7JfLDGkX+XGlRLo+0HMITdnz DJqQLc59yjYFiRMIHOZiCfLjlCbQBsJYMQBiyho4OxojqsFhBs+u6mvuviDjGlOouS/PumsIS3N PFZTI6F3ykelKvL6/eauxOQip/NuzgBmvIX+sPIlzSOdg9oarF+SeA4g44Ut05R621ifCekF1hL NBGsU85e+debLa0xAB1weFpwR1VvoZUNZo2sWixWTYV15JgpTpGncXLMjEtu4ncyTg45JTrpvtk zqGGeukHqFfGtGn5bq1eL+8872LWC+c9TojbjfxxW363t4h6ffoOXvj92hH9OZnhCU8uC1qOAfB f7BmmsRzTr6+82qRaHmD8TeymRNHdgsG6Ndyvva2ddDLRxQ6j+A== X-Google-Smtp-Source: AGHT+IG2prdz1XZ9eGTDiIzjqcNPqZtzxR1a6lghZb8RmLUFF/BaQgC0oKbzs7MLxKQs4HWuS8Vpcg== X-Received: by 2002:a05:6000:2dc5:b0:3e9:a1cb:ea93 with SMTP id ffacd0b85a97d-40e43b08e26mr6436522f8f.21.1758895757124; Fri, 26 Sep 2025 07:09:17 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 30/44] target/arm: Move alias setting for wildcards Date: Fri, 26 Sep 2025 15:08:30 +0100 Message-ID: <20250926140844.1493020-31-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250926140844.1493020-1-peter.maydell@linaro.org> References: <20250926140844.1493020-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758897075932116600 From: Richard Henderson Move this test from add_cpreg_to_hashtable to define_one_arm_cp_reg_with_opaque, where we can also simplify it based on the loop variables. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 [PMM: adjusted placement of comma in a comment] Signed-off-by: Peter Maydell --- target/arm/helper.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index a199320f140..274b7b5808e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7448,20 +7448,12 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, ARM= CPRegInfo *r, } =20 /* - * By convention, for wildcarded registers only the first - * entry is used for migration; the others are marked as - * ALIAS so we don't try to transfer the register - * multiple times. Special registers (ie NOP/WFI) are - * never migratable and not even raw-accessible. + * Special registers (ie NOP/WFI) are never migratable and + * are not even raw-accessible. */ if (r->type & ARM_CP_SPECIAL_MASK) { r->type |=3D ARM_CP_NO_RAW; } - if (((r->crm =3D=3D CP_ANY) && crm !=3D 0) || - ((r->opc1 =3D=3D CP_ANY) && opc1 !=3D 0) || - ((r->opc2 =3D=3D CP_ANY) && opc2 !=3D 0)) { - r->type |=3D ARM_CP_ALIAS | ARM_CP_NO_GDB; - } =20 /* * Update fields to match the instantiation, overwiting wildcards @@ -7765,6 +7757,16 @@ void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPR= egInfo *r) ARMCPRegInfo *r2 =3D alloc_cpreg(r, NULL); ARMCPRegInfo *r3; =20 + /* + * By convention, for wildcarded registers only the first + * entry is used for migration; the others are marked as + * ALIAS so we don't try to transfer the register + * multiple times. + */ + if (crm !=3D crmmin || opc1 !=3D opc1min || opc2 !=3D opc2= min) { + r2->type |=3D ARM_CP_ALIAS | ARM_CP_NO_GDB; + } + switch (r->state) { case ARM_CP_STATE_AA32: add_cpreg_to_hashtable_aa32(cpu, r2, cp, crm, opc1, op= c2); --=20 2.43.0 From nobody Sun Sep 28 15:26:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758896848; cv=none; d=zohomail.com; s=zohoarc; b=GLtUEw+eT9w9mvUvAqHFJid7u4TekkaAPXZf+J+EBPhTZqKWnZKLa0mjYFhEH2jPAlrAuIbPiCDDRqHWWTtaQI4njrWJ8qdOSvtFB4v7L4Z47Mh8VxcsL3+2LQrzD23jN5BaKTjG0jOnIRDl474S+MVd5woVQXTxVLn/GKR+HZE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758896848; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=yZEFx/GNhVkQj1G0HF9zfJ7+hUERk6GLhLOLXCxKnsc=; b=R/Uw7CkqoGgWu2pmfRexRcpvaQVD+D8dOangMm6weHPJiyr0aCxMmD0CZrlQ4wcYPcn7nMOqo5vH+aB/E3lkDTMOjrj+eQ0gVrNmqmWWDEF52coaJNrqtXQmuwMUeYy2oeOXPcImKC7aLsVUKOXERW7e7JBS4fA52Rn32UN4NY4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 175889684808938.81977983505851; Fri, 26 Sep 2025 07:27:28 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v29A9-0000pn-BN; Fri, 26 Sep 2025 10:11:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v299O-000081-HX for qemu-devel@nongnu.org; Fri, 26 Sep 2025 10:10:18 -0400 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1v298X-0005kj-Ao for qemu-devel@nongnu.org; Fri, 26 Sep 2025 10:10:02 -0400 Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-46e326e4e99so12248235e9.1 for ; Fri, 26 Sep 2025 07:09:21 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-410f2007372sm6338315f8f.16.2025.09.26.07.09.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Sep 2025 07:09:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758895758; x=1759500558; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=yZEFx/GNhVkQj1G0HF9zfJ7+hUERk6GLhLOLXCxKnsc=; b=WJHWg2PSElYFfo83bWTPjFEZQfEzFwvJrXUs+2QmzY+NFCgJFHvGv0MBBLSXk07Mdv gCM2uihJoNDTGrumlM6rW5yQ+JofxjaEOqD1yxuaEnTqNjwOM93Ag5pn3fdP6qKl26vR h33LaJiweQo423XLjks/uMO1UNT8G/Frvg0hnTR5oKxVyMcoDRFCALuWh2sFl8ntYY4e aYkKKy8ApsIVsiIXqViQZ31IEfbQANhjOkN96GW29ksA9SmZ3EzkiwrWmQvZRTKHVPVC eZufcRE80tU0Zh2KIoqX8t0hGmsriv96pt406TtXXb+uoYdHhXI/EhDTYFz9O/etswZ1 q7Ng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758895758; x=1759500558; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yZEFx/GNhVkQj1G0HF9zfJ7+hUERk6GLhLOLXCxKnsc=; b=pmBpjPG7/MKt0zJ+koCHtmjzxSRd+DlAulSNxb+JwGD3EZOWU3ipa7jJARuSjwrzIP DsxuLgDeqqYnwEPLJs0uLifkyaW1YIlvIqB+rWmp4y85YzfuWrtwubNTxGDOJ3Wo+MGD cU2s8LcUTQYmtLh0tCcCXiRXQt7r1exQVzu/qfrVOCZm5oWIrdGZuwXHb+CQh62eyxLj VO6YEqBcuuPG5IHRihT9M+5OQQMC8X66W574mpWM4+7xO7jgtoLGL4/MQcTgP58X4XFJ MfXZM0OtgdzseGLVnjeIEu+9W5x6mf1KOzaSBTidhlGCfPgbj+jTgJYt23J1WDPh0UzB X+JA== X-Gm-Message-State: AOJu0YzNzzqon/itgxp9BoLl8/7qCq9Uk2eeVTpgmce2Va0bem2AvN4U b0rtaqf7adEM7mPfBAY1seWRnogdJBVjrSy8tG8OHqXo9pPfC1ZExJDOmsBf4tk2IF4pJyD7Z1y O3c6Y X-Gm-Gg: ASbGnctccdjy/AndbzhbT/SsJTi0EddMB656SlBO83FICbS50v8axW59VigsJmaOxiI 1oMv65R0E8PTj81Xfs++8S3i+BKoXW4uLJsjpf9A+sx4ywFhaIdoPzziKJvhkBUdfYbYinauYe+ mhoYUTkP3joo4kEYMX0OjYJMsuYfldPbx9rqeRK172oWnFTDMg9Zcw0fNx9RkL4ViU0QTI/l/vU mWp1DpODXcHg3O8Fy30o/HEYff3ZRGMNo9HHcbE/MkA7ra5ey5etDx/9DHfwAxQaoqJXe+4RaiJ 8rqBhLJgyUv+DSaeRTL9xs1+ijwvcJ5fPCa1bwy9bIlvsx3m6Uvfai4YnF8k6W65OyW06EOrqeA aESPr4Rk9z2/L69UygwLiI0uJYj2JTthFT/DXg04= X-Google-Smtp-Source: AGHT+IG6mx6ouGnhLaaeYs0SfVVodUX6c9+5lmbuhWVgngsjOYxAEhrZuedhHa4ZWU6nHYK9sZWJUw== X-Received: by 2002:a05:6000:24c6:b0:3f4:ad3f:7c35 with SMTP id ffacd0b85a97d-40f69cd780fmr5764685f8f.27.1758895758130; Fri, 26 Sep 2025 07:09:18 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 31/44] target/arm: Move writeback of CP_ANY fields Date: Fri, 26 Sep 2025 15:08:31 +0100 Message-ID: <20250926140844.1493020-32-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250926140844.1493020-1-peter.maydell@linaro.org> References: <20250926140844.1493020-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758896848931116600 From: Richard Henderson Move the writeback of cp, crm, opc1, opc2 to define_one_arm_cp_reg, which means we don't have to pass all those parameters down to subroutines. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- target/arm/helper.c | 52 ++++++++++++++++++++++----------------------- 1 file changed, 26 insertions(+), 26 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 274b7b5808e..4063c8a0b6f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7390,7 +7390,6 @@ static ARMCPRegInfo *alloc_cpreg(const ARMCPRegInfo *= in, const char *suffix) */ static void add_cpreg_to_hashtable(ARMCPU *cpu, ARMCPRegInfo *r, CPState state, CPSecureState secstate, - int cp, int crm, int opc1, int opc2, uint32_t key) { CPUARMState *env =3D &cpu->env; @@ -7457,12 +7456,8 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, ARMC= PRegInfo *r, =20 /* * Update fields to match the instantiation, overwiting wildcards - * such as CP_ANY, ARM_CP_STATE_BOTH, or ARM_CP_SECSTATE_BOTH. + * such as ARM_CP_STATE_BOTH or ARM_CP_SECSTATE_BOTH. */ - r->cp =3D cp; - r->crm =3D crm; - r->opc1 =3D opc1; - r->opc2 =3D opc2; r->state =3D state; r->secure =3D secstate; =20 @@ -7478,8 +7473,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, ARMCP= RegInfo *r, g_hash_table_insert(cpu->cp_regs, (gpointer)(uintptr_t)key, r); } =20 -static void add_cpreg_to_hashtable_aa32(ARMCPU *cpu, ARMCPRegInfo *r, - int cp, int crm, int opc1, int opc= 2) +static void add_cpreg_to_hashtable_aa32(ARMCPU *cpu, ARMCPRegInfo *r) { /* * Under AArch32 CP registers can be common @@ -7487,7 +7481,8 @@ static void add_cpreg_to_hashtable_aa32(ARMCPU *cpu, = ARMCPRegInfo *r, */ ARMCPRegInfo *r_s; bool is64 =3D r->type & ARM_CP_64BIT; - uint32_t key =3D ENCODE_CP_REG(cp, is64, 0, r->crn, crm, opc1, opc2); + uint32_t key =3D ENCODE_CP_REG(r->cp, is64, 0, r->crn, + r->crm, r->opc1, r->opc2); =20 assert(!(r->type & ARM_CP_ADD_TLBI_NXS)); /* aa64 only */ =20 @@ -7496,27 +7491,26 @@ static void add_cpreg_to_hashtable_aa32(ARMCPU *cpu= , ARMCPRegInfo *r, key |=3D CP_REG_AA32_NS_MASK; /* fall through */ case ARM_CP_SECSTATE_S: - add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32, r->secure, - cp, crm, opc1, opc2, key); + add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32, r->secure, key); break; case ARM_CP_SECSTATE_BOTH: r_s =3D alloc_cpreg(r, "_S"); - add_cpreg_to_hashtable(cpu, r_s, ARM_CP_STATE_AA32, ARM_CP_SECSTAT= E_S, - cp, crm, opc1, opc2, key); + add_cpreg_to_hashtable(cpu, r_s, ARM_CP_STATE_AA32, + ARM_CP_SECSTATE_S, key); =20 key |=3D CP_REG_AA32_NS_MASK; - add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32, ARM_CP_SECSTATE_= NS, - cp, crm, opc1, opc2, key); + add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32, + ARM_CP_SECSTATE_NS, key); break; default: g_assert_not_reached(); } } =20 -static void add_cpreg_to_hashtable_aa64(ARMCPU *cpu, ARMCPRegInfo *r, - int crm, int opc1, int opc2) +static void add_cpreg_to_hashtable_aa64(ARMCPU *cpu, ARMCPRegInfo *r) { - uint32_t key =3D ENCODE_AA64_CP_REG(r->opc0, opc1, r->crn, crm, opc2); + uint32_t key =3D ENCODE_AA64_CP_REG(r->opc0, r->opc1, + r->crn, r->crm, r->opc2); =20 if ((r->type & ARM_CP_ADD_TLBI_NXS) && cpu_isar_feature(aa64_xs, cpu)) { @@ -7542,12 +7536,11 @@ static void add_cpreg_to_hashtable_aa64(ARMCPU *cpu= , ARMCPRegInfo *r, } =20 add_cpreg_to_hashtable(cpu, nxs_ri, ARM_CP_STATE_AA64, - ARM_CP_SECSTATE_NS, 0, crm, opc1, opc2, - nxs_key); + ARM_CP_SECSTATE_NS, nxs_key); } =20 - add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA64, ARM_CP_SECSTATE_NS, - 0, crm, opc1, opc2, key); + add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA64, + ARM_CP_SECSTATE_NS, key); } =20 void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *r) @@ -7767,17 +7760,24 @@ void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCP= RegInfo *r) r2->type |=3D ARM_CP_ALIAS | ARM_CP_NO_GDB; } =20 + /* Overwrite CP_ANY with the instantiation. */ + r2->crm =3D crm; + r2->opc1 =3D opc1; + r2->opc2 =3D opc2; + switch (r->state) { case ARM_CP_STATE_AA32: - add_cpreg_to_hashtable_aa32(cpu, r2, cp, crm, opc1, op= c2); + add_cpreg_to_hashtable_aa32(cpu, r2); break; case ARM_CP_STATE_AA64: - add_cpreg_to_hashtable_aa64(cpu, r2, crm, opc1, opc2); + add_cpreg_to_hashtable_aa64(cpu, r2); break; case ARM_CP_STATE_BOTH: r3 =3D alloc_cpreg(r2, NULL); - add_cpreg_to_hashtable_aa32(cpu, r2, cp, crm, opc1, op= c2); - add_cpreg_to_hashtable_aa64(cpu, r3, crm, opc1, opc2); + r2->cp =3D cp; + add_cpreg_to_hashtable_aa32(cpu, r2); + r3->cp =3D 0; + add_cpreg_to_hashtable_aa64(cpu, r3); break; default: g_assert_not_reached(); --=20 2.43.0 From nobody Sun Sep 28 15:26:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758896378; cv=none; d=zohomail.com; s=zohoarc; b=DcbTJ2Gb2UZgV3hMWpV+11BVZNGYk0pccWvUPIWLQgZ2WF0Hki2B79cr6t0M0Fr+sdGpt55J7aM90wkuII53ZLiNrQiLArItDrxD10zSN4SNSrqVBXsPaQ580qQ7KuTpwnAhBidXSxNTi8YrTLNlyv1ZMb4M3xQXd/bCtzdIdrQ= ARC-Message-Signature: i=1; a=rsa-sha256; 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Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- target/arm/helper.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 4063c8a0b6f..18066b0c5dc 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7438,14 +7438,21 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, ARM= CPRegInfo *r, */ r->type |=3D ARM_CP_ALIAS; } - - if (HOST_BIG_ENDIAN && - r->state =3D=3D ARM_CP_STATE_BOTH && r->fieldoffset) { - r->fieldoffset +=3D sizeof(uint32_t); - } } } =20 + /* + * For 32-bit AArch32 regs shared with 64-bit AArch64 regs, + * adjust the field offset for endianness. This had to be + * delayed until banked registers were resolved. + */ + if (HOST_BIG_ENDIAN && + state =3D=3D ARM_CP_STATE_AA32 && + r->state =3D=3D ARM_CP_STATE_BOTH && + r->fieldoffset) { + r->fieldoffset +=3D sizeof(uint32_t); + } + /* * Special registers (ie NOP/WFI) are never migratable and * are not even raw-accessible. --=20 2.43.0 From nobody Sun Sep 28 15:26:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758896273; cv=none; d=zohomail.com; s=zohoarc; b=YeSZO2qRwt2QZI06Omh5UnXNC2Zjbm4MO/GAROiAP2mLVsEnNNrUu4DMzME3gnjhnsqxXgSwLNOZO+sstqAD2h/ssq5FN8fovlY1YCX3u3AteDHJrKhaHQ6/sSzoObTvQJNHcIfKfvVVvI/DcvEnEak0Zy62rN1cY8cf5fTtHh8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758896273; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=54i7q0TRCUXKYY+qLOk6M0n5wBbAsiSPn2GQEuQkelk=; b=MUQM4jeMBCpCt/JRvLAbjPyeUaunXAAaBl4JM4ek3/m8OvPHcxNTGmsuQennZoIQ8dUQTvMyn7pc7tzNePz9bbn76rgArSfg70SLzEl8Ngyy/A7M5nW3ytmEgS2ef7o7K6HGum8KjfQ8bAMQchpWg3/OO2fh0cEytI3QFDyAn8o= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1758896273545942.6476026442883; Fri, 26 Sep 2025 07:17:53 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v299Q-0000Cg-2I; Fri, 26 Sep 2025 10:10:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v2994-0008IM-45 for qemu-devel@nongnu.org; Fri, 26 Sep 2025 10:09:58 -0400 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1v298X-0005l0-Bv for qemu-devel@nongnu.org; Fri, 26 Sep 2025 10:09:55 -0400 Received: by mail-wr1-x434.google.com with SMTP id ffacd0b85a97d-3f2ae6fae12so1212136f8f.1 for ; Fri, 26 Sep 2025 07:09:22 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- target/arm/cpu.h | 3 +-- target/arm/tcg/translate.h | 2 ++ target/arm/tcg/hflags.c | 8 +++++--- target/arm/tcg/translate-a64.c | 3 ++- 4 files changed, 10 insertions(+), 6 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 1c0deb723d7..d5534e35804 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3065,8 +3065,7 @@ FIELD(TBFLAG_A64, ATA0, 31, 1) FIELD(TBFLAG_A64, NV, 32, 1) FIELD(TBFLAG_A64, NV1, 33, 1) FIELD(TBFLAG_A64, NV2, 34, 1) -/* Set if FEAT_NV2 RAM accesses use the EL2&0 translation regime */ -FIELD(TBFLAG_A64, NV2_MEM_E20, 35, 1) +FIELD(TBFLAG_A64, E2H, 35, 1) /* Set if FEAT_NV2 RAM accesses are big-endian */ FIELD(TBFLAG_A64, NV2_MEM_BE, 36, 1) FIELD(TBFLAG_A64, AH, 37, 1) /* FPCR.AH */ diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index ec4755ae3fd..f1a6e5e2b61 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -150,6 +150,8 @@ typedef struct DisasContext { bool trap_eret; /* True if FEAT_LSE2 SCTLR_ELx.nAA is set */ bool naa; + /* True if HCR_EL2.E2H is set */ + bool e2h; /* True if FEAT_NV HCR_EL2.NV is enabled */ bool nv; /* True if NV enabled and HCR_EL2.NV1 is set */ diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c index 01894226cc9..17f83f13a40 100644 --- a/target/arm/tcg/hflags.c +++ b/target/arm/tcg/hflags.c @@ -258,6 +258,11 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *e= nv, int el, int fp_el, DP_TBFLAG_A64(flags, TBII, tbii); DP_TBFLAG_A64(flags, TBID, tbid); =20 + /* E2H is used by both VHE and NV2. */ + if (hcr & HCR_E2H) { + DP_TBFLAG_A64(flags, E2H, 1); + } + if (cpu_isar_feature(aa64_sve, env_archcpu(env))) { int sve_el =3D sve_exception_el(env, el); =20 @@ -390,9 +395,6 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *en= v, int el, int fp_el, } if (hcr & HCR_NV2) { DP_TBFLAG_A64(flags, NV2, 1); - if (hcr & HCR_E2H) { - DP_TBFLAG_A64(flags, NV2_MEM_E20, 1); - } if (env->cp15.sctlr_el[2] & SCTLR_EE) { DP_TBFLAG_A64(flags, NV2_MEM_BE, 1); } diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 0ec309f1ea9..599e7a36ee3 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -10304,10 +10304,11 @@ static void aarch64_tr_init_disas_context(DisasCo= ntextBase *dcbase, dc->pstate_za =3D EX_TBFLAG_A64(tb_flags, PSTATE_ZA); dc->sme_trap_nonstreaming =3D EX_TBFLAG_A64(tb_flags, SME_TRAP_NONSTRE= AMING); dc->naa =3D EX_TBFLAG_A64(tb_flags, NAA); + dc->e2h =3D EX_TBFLAG_A64(tb_flags, E2H); dc->nv =3D EX_TBFLAG_A64(tb_flags, NV); dc->nv1 =3D EX_TBFLAG_A64(tb_flags, NV1); dc->nv2 =3D EX_TBFLAG_A64(tb_flags, NV2); - dc->nv2_mem_e20 =3D EX_TBFLAG_A64(tb_flags, NV2_MEM_E20); + dc->nv2_mem_e20 =3D dc->nv2 && dc->e2h; dc->nv2_mem_be =3D EX_TBFLAG_A64(tb_flags, NV2_MEM_BE); dc->fpcr_ah =3D EX_TBFLAG_A64(tb_flags, AH); dc->fpcr_nep =3D EX_TBFLAG_A64(tb_flags, NEP); --=20 2.43.0 From nobody Sun Sep 28 15:26:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Fri, 26 Sep 2025 07:09:20 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 34/44] target/arm: Split out redirect_cpreg Date: Fri, 26 Sep 2025 15:08:34 +0100 Message-ID: <20250926140844.1493020-35-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250926140844.1493020-1-peter.maydell@linaro.org> References: <20250926140844.1493020-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758896404798116600 From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- target/arm/tcg/translate-a64.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 599e7a36ee3..c0fa2137b63 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2455,6 +2455,19 @@ static void gen_sysreg_undef(DisasContext *s, bool i= sread, gen_exception_insn(s, 0, EXCP_UDEF, syndrome); } =20 +/* + * Look up @key, returning the cpreg, which must exist. + * Additionally, the new cpreg must also be accessible. + */ +static const ARMCPRegInfo * +redirect_cpreg(DisasContext *s, uint32_t key, bool isread) +{ + const ARMCPRegInfo *ri =3D get_arm_cp_reginfo(s->cp_regs, key); + assert(ri); + assert(cp_access_ok(s->current_el, ri, isread)); + return ri; +} + /* MRS - move from system register * MSR (register) - move to system register * SYS @@ -2603,9 +2616,7 @@ static void handle_sys(DisasContext *s, bool isread, * fine-grained-traps on EL1 also do not apply here. */ key =3D ENCODE_AA64_CP_REG(op0, 0, crn, crm, op2); - ri =3D get_arm_cp_reginfo(s->cp_regs, key); - assert(ri); - assert(cp_access_ok(s->current_el, ri, isread)); + ri =3D redirect_cpreg(s, key, isread); /* * We might not have done an update_pc earlier, so check we don't * need it. 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Fri, 26 Sep 2025 07:09:21 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 35/44] target/arm: Redirect VHE FOO_EL1 -> FOO_EL2 during translation Date: Fri, 26 Sep 2025 15:08:35 +0100 Message-ID: <20250926140844.1493020-36-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250926140844.1493020-1-peter.maydell@linaro.org> References: <20250926140844.1493020-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758897029300116600 From: Richard Henderson Reviewed-by: Manos Pitsidianakis Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- target/arm/cpregs.h | 6 ++++ target/arm/gdbstub.c | 5 ++++ target/arm/helper.c | 53 +--------------------------------- target/arm/tcg/translate-a64.c | 9 ++++++ 4 files changed, 21 insertions(+), 52 deletions(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 08fc42ea571..eac0cb9ebf1 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -936,6 +936,12 @@ struct ARMCPRegInfo { */ uint32_t nv2_redirect_offset; =20 + /* + * With VHE, with E2H, at EL2, access to this EL0/EL1 reg redirects + * to the EL2 reg with the specified key. + */ + uint32_t vhe_redir_to_el2; + /* This is used only by VHE. */ void *opaque; /* diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index 4e2ac49b6a9..87d40d4366b 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -249,6 +249,11 @@ static int arm_gdb_get_sysreg(CPUState *cs, GByteArray= *buf, int reg) if (ri) { switch (cpreg_field_type(ri)) { case MO_64: + if (ri->vhe_redir_to_el2 && + (arm_hcr_el2_eff(env) & HCR_E2H) && + arm_current_el(env) =3D=3D 2) { + ri =3D get_arm_cp_reginfo(cpu->cp_regs, ri->vhe_redir_to_e= l2); + } return gdb_get_reg64(buf, (uint64_t)read_raw_cp_reg(env, ri)); case MO_32: return gdb_get_reg32(buf, (uint32_t)read_raw_cp_reg(env, ri)); diff --git a/target/arm/helper.c b/target/arm/helper.c index 18066b0c5dc..87a32e363e9 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4417,47 +4417,6 @@ static CPAccessResult access_el1nvvct(CPUARMState *e= nv, const ARMCPRegInfo *ri, return e2h_access(env, ri, isread); } =20 -/* Test if system register redirection is to occur in the current state. = */ -static bool redirect_for_e2h(CPUARMState *env) -{ - return arm_current_el(env) =3D=3D 2 && (arm_hcr_el2_eff(env) & HCR_E2H= ); -} - -static uint64_t el2_e2h_read(CPUARMState *env, const ARMCPRegInfo *ri) -{ - CPReadFn *readfn; - - if (redirect_for_e2h(env)) { - /* Switch to the saved EL2 version of the register. */ - ri =3D ri->opaque; - readfn =3D ri->readfn; - } else { - readfn =3D ri->orig_readfn; - } - if (readfn =3D=3D NULL) { - readfn =3D raw_read; - } - return readfn(env, ri); -} - -static void el2_e2h_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - CPWriteFn *writefn; - - if (redirect_for_e2h(env)) { - /* Switch to the saved EL2 version of the register. */ - ri =3D ri->opaque; - writefn =3D ri->writefn; - } else { - writefn =3D ri->orig_writefn; - } - if (writefn =3D=3D NULL) { - writefn =3D raw_write; - } - writefn(env, ri, value); -} - static uint64_t el2_e2h_e12_read(CPUARMState *env, const ARMCPRegInfo *ri) { /* Pass the EL1 register accessor its ri, not the EL12 alias ri */ @@ -4632,17 +4591,7 @@ static void define_arm_vh_e2h_redirects_aliases(ARMC= PU *cpu) (gpointer)(uintptr_t)a->new_key, new_reg); g_assert(ok); =20 - src_reg->opaque =3D dst_reg; - src_reg->orig_readfn =3D src_reg->readfn ?: raw_read; - src_reg->orig_writefn =3D src_reg->writefn ?: raw_write; - if (!src_reg->raw_readfn) { - src_reg->raw_readfn =3D raw_read; - } - if (!src_reg->raw_writefn) { - src_reg->raw_writefn =3D raw_write; - } - src_reg->readfn =3D el2_e2h_read; - src_reg->writefn =3D el2_e2h_write; + src_reg->vhe_redir_to_el2 =3D a->dst_key; } } #endif diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index c0fa2137b63..3ef24fb0c3d 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2573,6 +2573,15 @@ static void handle_sys(DisasContext *s, bool isread, } } =20 + if (ri->vhe_redir_to_el2 && s->current_el =3D=3D 2 && s->e2h) { + /* + * This one of the FOO_EL1 registers which redirect to FOO_EL2 + * from EL2 when HCR_EL2.E2H is set. + */ + key =3D ri->vhe_redir_to_el2; + ri =3D redirect_cpreg(s, key, isread); + } + if (ri->accessfn || (ri->fgt && s->fgt_active)) { /* Emit code to perform further access permissions checks at * runtime; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-410f2007372sm6338315f8f.16.2025.09.26.07.09.21 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Sep 2025 07:09:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758895763; x=1759500563; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=DjT9lISCaQBeI88j1b+YFCNbfn0WTQJFDq4zyRv2P5w=; b=FwbDh5K1Wz0D7adnonCY4IAaLq7JiHa7nTdFYEqstCMIF5Xt7L0MTXHdHNCy52TYxF Gyv/cpo4NhYRzvItHXZV4KK7Osb4HJSo8e6ME7iZvQyheHgRpCo2WAE7qdyDlJZvPS7M GEm4FgGBJhNFm2cTcmplaU5wyObqfPNVpt+foiFxuXWQ/E43gUlbGuE6PDR66DaArijv dTurCG1GTVh2A1NnxTjoo75DJ2wgy34U7gxkCQXJtS2dGky1okHKNcy6acDRg3ZHV+Qu oFzE4a2TfiFbqPrd5woHi/Z558Bqh+GnZ3mK+nV/Dkwg5MwwS/TVEFxwMTE2ZkraBR/m n4HQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758895763; x=1759500563; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DjT9lISCaQBeI88j1b+YFCNbfn0WTQJFDq4zyRv2P5w=; b=qAxJnkI9EQHTSFo6wKN92Nhl7fvuGUBP8TyM+Bex3OGzd/KRNHRNZof5HSk/lqg9JC EzwjrlFD2CRcw0XK+75L1me2eWEDT8JCgYGnlwh3vHmi1FjGE3rOjWb2omAUVn7RrCMR 8rKXmxsYfjgJmScSa1w5qKUQIOwnbe8hL9ckKj3DvZjHQ9HUoA8/xEL1BqDCnoUdiEbx 9ZE7v8It/tE3zhLJ7nDcKGeXxazoqTTZWqmcDNFaE8dV+EcH5sjzlw4PG2Kk4Rg0SWRw bLQ7Q2y2/v1fjCDiWKMlqPXg/G7GKbYvtLyVpcK2bdWSmVAkzuSmcSDxpD7bu8F2W34z BjUA== X-Gm-Message-State: AOJu0Yx81qHJRpJnIIh5VgxbDBMJyfPAkqXbu4WHZUziFTRdFGAvtGlC /SqHm9hwGY25njNuoYx05Stl+fWtKskNJtHDmHsOLQiMRD6cfmiXR745xBNhTOLNI0ovz+DfGUc xMvpw X-Gm-Gg: ASbGncvH44EvAwIK1k/n4OXBjhgq6stma3j6CRu3y9yi8v3+CtieW15A/1xpbhkbtcH J1gsjRkdsRcUyH3JV45k1MUKPddc8AyJRW22Bb6QotLFrEx+XuMvBUjTCKwRzChfGo1XEZBclSz T+XE6MMUlRtQ8qxs8icBoXogMtj0XoTde0/drCUabLQbOXQ+TUGwevc4AZBOCfbZjZftEFdSWaK RyJPyEvyaP2zUMPbNOF/fqqJa5yrF/LZ1lBq3M86yPwJIzsCxlsMGX77PzRpZt4ZhU17wFKMB3m YHI23bD+IzuAg7HBH9SDN8b1PAMy+LnyJz2J3vifXPRVu9N67YK1paTCTD9FJGiqcXwitSxpG9H xqtZHxAZrOCvdpkaC20rk0pBt3iZL X-Google-Smtp-Source: AGHT+IF5lUB+EfsAs4tq3mMz42eeK/x13Zl52IO0BYNbIwPcaY2CiRztFPNt6MSbe01eEtJVbNWJDg== X-Received: by 2002:a05:6000:40dc:b0:3ee:13b1:d70e with SMTP id ffacd0b85a97d-40e47ee1da9mr7433145f8f.40.1758895762863; Fri, 26 Sep 2025 07:09:22 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 36/44] target/arm: Redirect VHE FOO_EL12 to FOO_EL1 during translation Date: Fri, 26 Sep 2025 15:08:36 +0100 Message-ID: <20250926140844.1493020-37-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250926140844.1493020-1-peter.maydell@linaro.org> References: <20250926140844.1493020-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758896411142116600 From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Tested-by: Philippe Mathieu-Daud=C3=A9 [PMM: expanded a comment slightly] Signed-off-by: Peter Maydell --- target/arm/cpregs.h | 22 ++++--------- target/arm/gdbstub.c | 2 ++ target/arm/helper.c | 57 +++------------------------------- target/arm/tcg/translate-a64.c | 12 +++++++ 4 files changed, 25 insertions(+), 68 deletions(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index eac0cb9ebf1..8ab5892acce 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -942,8 +942,12 @@ struct ARMCPRegInfo { */ uint32_t vhe_redir_to_el2; =20 - /* This is used only by VHE. */ - void *opaque; + /* + * With VHE, with E2H, at EL2+, access to this EL02/EL12 reg + * redirects to the EL0/EL1 reg with the specified key. + */ + uint32_t vhe_redir_to_el01; + /* * Value of this register, if it is ARM_CP_CONST. Otherwise, if * fieldoffset is non-zero, the reset value of the register. @@ -1011,20 +1015,6 @@ struct ARMCPRegInfo { * fieldoffset is 0 then no reset will be done. */ CPResetFn *resetfn; - - /* - * "Original" readfn, writefn, accessfn. - * For ARMv8.1-VHE register aliases, we overwrite the read/write - * accessor functions of various EL1/EL0 to perform the runtime - * check for which sysreg should actually be modified, and then - * forwards the operation. Before overwriting the accessors, - * the original function is copied here, so that accesses that - * really do go to the EL1/EL0 version proceed normally. - * (The corresponding EL2 register is linked via opaque.) - */ - CPReadFn *orig_readfn; - CPWriteFn *orig_writefn; - CPAccessFn *orig_accessfn; }; =20 void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs); diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index 87d40d4366b..8d2229f5192 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -253,6 +253,8 @@ static int arm_gdb_get_sysreg(CPUState *cs, GByteArray = *buf, int reg) (arm_hcr_el2_eff(env) & HCR_E2H) && arm_current_el(env) =3D=3D 2) { ri =3D get_arm_cp_reginfo(cpu->cp_regs, ri->vhe_redir_to_e= l2); + } else if (ri->vhe_redir_to_el01) { + ri =3D get_arm_cp_reginfo(cpu->cp_regs, ri->vhe_redir_to_e= l01); } return gdb_get_reg64(buf, (uint64_t)read_raw_cp_reg(env, ri)); case MO_32: diff --git a/target/arm/helper.c b/target/arm/helper.c index 87a32e363e9..3840ca62a69 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4417,42 +4417,6 @@ static CPAccessResult access_el1nvvct(CPUARMState *e= nv, const ARMCPRegInfo *ri, return e2h_access(env, ri, isread); } =20 -static uint64_t el2_e2h_e12_read(CPUARMState *env, const ARMCPRegInfo *ri) -{ - /* Pass the EL1 register accessor its ri, not the EL12 alias ri */ - return ri->orig_readfn(env, ri->opaque); -} - -static void el2_e2h_e12_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - /* Pass the EL1 register accessor its ri, not the EL12 alias ri */ - return ri->orig_writefn(env, ri->opaque, value); -} - -static CPAccessResult el2_e2h_e12_access(CPUARMState *env, - const ARMCPRegInfo *ri, - bool isread) -{ - if (arm_current_el(env) =3D=3D 1) { - /* - * This must be a FEAT_NV access (will either trap or redirect - * to memory). None of the registers with _EL12 aliases want to - * apply their trap controls for this kind of access, so don't - * call the orig_accessfn or do the "UNDEF when E2H is 0" check. - */ - return CP_ACCESS_OK; - } - /* FOO_EL12 aliases only exist when E2H is 1; otherwise they UNDEF */ - if (!(arm_hcr_el2_eff(env) & HCR_E2H)) { - return CP_ACCESS_UNDEFINED; - } - if (ri->orig_accessfn) { - return ri->orig_accessfn(env, ri->opaque, isread); - } - return CP_ACCESS_OK; -} - static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu) { struct E2HAlias { @@ -4541,9 +4505,6 @@ static void define_arm_vh_e2h_redirects_aliases(ARMCP= U *cpu) g_assert(strcmp(src_reg->name, a->src_name) =3D=3D 0); g_assert(strcmp(dst_reg->name, a->dst_name) =3D=3D 0); =20 - /* None of the core system registers use opaque; we will. */ - g_assert(src_reg->opaque =3D=3D NULL); - /* Create alias before redirection so we dup the right data. */ new_reg =3D g_memdup(src_reg, sizeof(ARMCPRegInfo)); =20 @@ -4562,19 +4523,11 @@ static void define_arm_vh_e2h_redirects_aliases(ARM= CPU *cpu) >> CP_REG_ARM64_SYSREG_OP1_SHIFT; new_reg->opc2 =3D (a->new_key & CP_REG_ARM64_SYSREG_OP2_MASK) >> CP_REG_ARM64_SYSREG_OP2_SHIFT; - new_reg->opaque =3D src_reg; - new_reg->orig_readfn =3D src_reg->readfn ?: raw_read; - new_reg->orig_writefn =3D src_reg->writefn ?: raw_write; - new_reg->orig_accessfn =3D src_reg->accessfn; - if (!new_reg->raw_readfn) { - new_reg->raw_readfn =3D raw_read; - } - if (!new_reg->raw_writefn) { - new_reg->raw_writefn =3D raw_write; - } - new_reg->readfn =3D el2_e2h_e12_read; - new_reg->writefn =3D el2_e2h_e12_write; - new_reg->accessfn =3D el2_e2h_e12_access; + new_reg->vhe_redir_to_el01 =3D a->src_key; + new_reg->readfn =3D NULL; + new_reg->writefn =3D NULL; + new_reg->accessfn =3D NULL; + new_reg->fieldoffset =3D 0; =20 /* * If the _EL1 register is redirected to memory by FEAT_NV2, diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 3ef24fb0c3d..a0e3300231f 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2580,6 +2580,18 @@ static void handle_sys(DisasContext *s, bool isread, */ key =3D ri->vhe_redir_to_el2; ri =3D redirect_cpreg(s, key, isread); + } else if (ri->vhe_redir_to_el01 && s->current_el >=3D 2) { + /* + * This is one of the FOO_EL12 or FOO_EL02 registers. + * With !E2H, they all UNDEF. + * With E2H, from EL2 or EL3, they redirect to FOO_EL1/FOO_EL0. + */ + if (!s->e2h) { + gen_sysreg_undef(s, isread, op0, op1, op2, crn, crm, rt); + return; + } + key =3D ri->vhe_redir_to_el01; + ri =3D redirect_cpreg(s, key, isread); } =20 if (ri->accessfn || (ri->fgt && s->fgt_active)) { --=20 2.43.0 From nobody Sun Sep 28 15:26:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758896605; cv=none; d=zohomail.com; s=zohoarc; b=E7Hy9k4LPo9YSf6gvAXOD1TrilNllZ98liE/99S4Wp9Tv10tI9THURinWnN6IWukwv5C/PC+X7bOt08RGKWD+S8WYlxTLPSujCb5Nwy1DdQFEWBB3INlLEU8Qt9FLDTDmyLL3cDamjetL3k8KHerPA1+W9i+3IAl4Is1OBXp4i0= ARC-Message-Signature: i=1; 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Reviewed-by: Manos Pitsidianakis Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- target/arm/helper.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 3840ca62a69..12835977bd8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -671,7 +671,7 @@ static const ARMCPRegInfo v6_cp_reginfo[] =3D { */ { .name =3D "WFAR", .cp =3D 15, .crn =3D 6, .crm =3D 0, .opc1 =3D 0, .= opc2 =3D 1, .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0, }, - { .name =3D "CPACR", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, + { .name =3D "CPACR_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .crn =3D 1, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 2, .accessfn =3D cpac= r_access, .fgt =3D FGT_CPACR_EL1, .nv2_redirect_offset =3D 0x100 | NV2_REDIR_NV1, @@ -2018,7 +2018,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = =3D { .resetfn =3D arm_gt_cntfrq_reset, }, /* overall control: mostly access permissions */ - { .name =3D "CNTKCTL", .state =3D ARM_CP_STATE_BOTH, + { .name =3D "CNTKCTL_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 14, .crm =3D 1, .opc2 =3D 0, .access =3D PL1_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.c14_cntkctl), @@ -3048,8 +3048,8 @@ static uint64_t mpidr_read(CPUARMState *env, const AR= MCPRegInfo *ri) } =20 static const ARMCPRegInfo lpae_cp_reginfo[] =3D { - /* NOP AMAIR0/1 */ - { .name =3D "AMAIR0", .state =3D ARM_CP_STATE_BOTH, + /* AMAIR0 is mapped to AMAIR_EL1[31:0] */ + { .name =3D "AMAIR_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .crn =3D 10, .crm =3D 3, .opc1 =3D 0, .opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .fgt =3D FGT_AMAIR_EL1, @@ -4430,11 +4430,11 @@ static void define_arm_vh_e2h_redirects_aliases(ARM= CPU *cpu) =20 static const struct E2HAlias aliases[] =3D { { K(3, 0, 1, 0, 0), K(3, 4, 1, 0, 0), K(3, 5, 1, 0, 0), - "SCTLR", "SCTLR_EL2", "SCTLR_EL12" }, + "SCTLR_EL1", "SCTLR_EL2", "SCTLR_EL12" }, { K(3, 0, 1, 0, 3), K(3, 4, 1, 0, 3), K(3, 5, 1, 0, 3), "SCTLR2_EL1", "SCTLR2_EL2", "SCTLR2_EL12", isar_feature_aa64_sct= lr2 }, { K(3, 0, 1, 0, 2), K(3, 4, 1, 1, 2), K(3, 5, 1, 0, 2), - "CPACR", "CPTR_EL2", "CPACR_EL12" }, + "CPACR_EL1", "CPTR_EL2", "CPACR_EL12" }, { K(3, 0, 2, 0, 0), K(3, 4, 2, 0, 0), K(3, 5, 2, 0, 0), "TTBR0_EL1", "TTBR0_EL2", "TTBR0_EL12" }, { K(3, 0, 2, 0, 1), K(3, 4, 2, 0, 1), K(3, 5, 2, 0, 1), @@ -4458,13 +4458,13 @@ static void define_arm_vh_e2h_redirects_aliases(ARM= CPU *cpu) { K(3, 0, 10, 2, 0), K(3, 4, 10, 2, 0), K(3, 5, 10, 2, 0), "MAIR_EL1", "MAIR_EL2", "MAIR_EL12" }, { K(3, 0, 10, 3, 0), K(3, 4, 10, 3, 0), K(3, 5, 10, 3, 0), - "AMAIR0", "AMAIR_EL2", "AMAIR_EL12" }, + "AMAIR_EL1", "AMAIR_EL2", "AMAIR_EL12" }, { K(3, 0, 12, 0, 0), K(3, 4, 12, 0, 0), K(3, 5, 12, 0, 0), - "VBAR", "VBAR_EL2", "VBAR_EL12" }, + "VBAR_EL1", "VBAR_EL2", "VBAR_EL12" }, { K(3, 0, 13, 0, 1), K(3, 4, 13, 0, 1), K(3, 5, 13, 0, 1), "CONTEXTIDR_EL1", "CONTEXTIDR_EL2", "CONTEXTIDR_EL12" }, { K(3, 0, 14, 1, 0), K(3, 4, 14, 1, 0), K(3, 5, 14, 1, 0), - "CNTKCTL", "CNTHCTL_EL2", "CNTKCTL_EL12" }, + "CNTKCTL_EL1", "CNTHCTL_EL2", "CNTKCTL_EL12" }, =20 { K(3, 0, 1, 2, 0), K(3, 4, 1, 2, 0), K(3, 5, 1, 2, 0), "ZCR_EL1", "ZCR_EL2", "ZCR_EL12", isar_feature_aa64_sve }, @@ -7098,7 +7098,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) =20 if (arm_feature(env, ARM_FEATURE_VBAR)) { static const ARMCPRegInfo vbar_cp_reginfo[] =3D { - { .name =3D "VBAR", .state =3D ARM_CP_STATE_BOTH, + { .name =3D "VBAR_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .crn =3D 12, .crm =3D 0, .opc1 =3D 0, .opc2 =3D= 0, .access =3D PL1_RW, .writefn =3D vbar_write, .accessfn =3D access_nv1, @@ -7114,7 +7114,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) /* Generic registers whose values depend on the implementation */ { ARMCPRegInfo sctlr =3D { - .name =3D "SCTLR", .state =3D ARM_CP_STATE_BOTH, + .name =3D "SCTLR_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 1, .crm =3D 0, .opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .fgt =3D FGT_SCTLR_EL1, --=20 2.43.0 From nobody Sun Sep 28 15:26:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Clear the fields within add_cpreg_to_hashtable_aa32. Create the FOO_EL12 cpreg within add_cpreg_to_hashtable_aa64; add ARM_CP_NO_RAW. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- target/arm/cpregs.h | 6 +- target/arm/helper.c | 243 +++++++++++++++++++------------------------- 2 files changed, 107 insertions(+), 142 deletions(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 8ab5892acce..57fde5f57ae 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -943,8 +943,10 @@ struct ARMCPRegInfo { uint32_t vhe_redir_to_el2; =20 /* - * With VHE, with E2H, at EL2+, access to this EL02/EL12 reg - * redirects to the EL0/EL1 reg with the specified key. + * For VHE. Before registration, this field holds the key for an + * EL02/EL12 reg to be created to point back to this EL0/EL1 reg. + * After registration, this field is set only on the EL02/EL12 reg + * and points back to the EL02/EL12 reg for redirection with E2H. */ uint32_t vhe_redir_to_el01; =20 diff --git a/target/arm/helper.c b/target/arm/helper.c index 12835977bd8..c5a8ef50493 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -454,6 +454,8 @@ static const ARMCPRegInfo cp_reginfo[] =3D { .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .fgt =3D FGT_CONTEXTIDR_EL1, .nv2_redirect_offset =3D 0x108 | NV2_REDIR_NV1, + .vhe_redir_to_el2 =3D ENCODE_AA64_CP_REG(3, 4, 13, 0, 1), + .vhe_redir_to_el01 =3D ENCODE_AA64_CP_REG(3, 5, 13, 0, 1), .secure =3D ARM_CP_SECSTATE_NS, .fieldoffset =3D offsetof(CPUARMState, cp15.contextidr_el[1]), .resetvalue =3D 0, .writefn =3D contextidr_write, .raw_writefn =3D r= aw_write, }, @@ -674,6 +676,8 @@ static const ARMCPRegInfo v6_cp_reginfo[] =3D { { .name =3D "CPACR_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .crn =3D 1, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 2, .accessfn =3D cpac= r_access, .fgt =3D FGT_CPACR_EL1, + .vhe_redir_to_el2 =3D ENCODE_AA64_CP_REG(3, 4, 1, 1, 2), + .vhe_redir_to_el01 =3D ENCODE_AA64_CP_REG(3, 5, 1, 0, 2), .nv2_redirect_offset =3D 0x100 | NV2_REDIR_NV1, .access =3D PL1_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.cpac= r_el1), .resetfn =3D cpacr_reset, .writefn =3D cpacr_write, .readfn =3D cpac= r_read }, @@ -956,12 +960,16 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .fgt =3D FGT_AFSR0_EL1, .nv2_redirect_offset =3D 0x128 | NV2_REDIR_NV1, + .vhe_redir_to_el2 =3D ENCODE_AA64_CP_REG(3, 4, 5, 1, 0), + .vhe_redir_to_el01 =3D ENCODE_AA64_CP_REG(3, 5, 5, 1, 0), .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, { .name =3D "AFSR1_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 5, .crm =3D 1, .opc2 =3D 1, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .fgt =3D FGT_AFSR1_EL1, .nv2_redirect_offset =3D 0x130 | NV2_REDIR_NV1, + .vhe_redir_to_el2 =3D ENCODE_AA64_CP_REG(3, 4, 5, 1, 1), + .vhe_redir_to_el01 =3D ENCODE_AA64_CP_REG(3, 5, 5, 1, 1), .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, /* * MAIR can just read-as-written because we don't implement caches @@ -972,6 +980,8 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .fgt =3D FGT_MAIR_EL1, .nv2_redirect_offset =3D 0x140 | NV2_REDIR_NV1, + .vhe_redir_to_el2 =3D ENCODE_AA64_CP_REG(3, 4, 10, 2, 0), + .vhe_redir_to_el01 =3D ENCODE_AA64_CP_REG(3, 5, 10, 2, 0), .fieldoffset =3D offsetof(CPUARMState, cp15.mair_el[1]), .resetvalue =3D 0 }, { .name =3D "MAIR_EL3", .state =3D ARM_CP_STATE_AA64, @@ -2021,6 +2031,8 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = =3D { { .name =3D "CNTKCTL_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 14, .crm =3D 1, .opc2 =3D 0, .access =3D PL1_RW, + .vhe_redir_to_el2 =3D ENCODE_AA64_CP_REG(3, 4, 14, 1, 0), + .vhe_redir_to_el01 =3D ENCODE_AA64_CP_REG(3, 5, 14, 1, 0), .fieldoffset =3D offsetof(CPUARMState, cp15.c14_cntkctl), .resetvalue =3D 0, }, @@ -2811,6 +2823,8 @@ static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] =3D { .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .fgt =3D FGT_FAR_EL1, .nv2_redirect_offset =3D 0x220 | NV2_REDIR_NV1, + .vhe_redir_to_el2 =3D ENCODE_AA64_CP_REG(3, 4, 6, 0, 0), + .vhe_redir_to_el01 =3D ENCODE_AA64_CP_REG(3, 5, 6, 0, 0), .fieldoffset =3D offsetof(CPUARMState, cp15.far_el[1]), .resetvalue =3D 0, }, }; @@ -2821,12 +2835,16 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] =3D { .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .fgt =3D FGT_ESR_EL1, .nv2_redirect_offset =3D 0x138 | NV2_REDIR_NV1, + .vhe_redir_to_el2 =3D ENCODE_AA64_CP_REG(3, 4, 5, 2, 0), + .vhe_redir_to_el01 =3D ENCODE_AA64_CP_REG(3, 5, 5, 2, 0), .fieldoffset =3D offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = =3D 0, }, { .name =3D "TTBR0_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 0, .opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .fgt =3D FGT_TTBR0_EL1, .nv2_redirect_offset =3D 0x200 | NV2_REDIR_NV1, + .vhe_redir_to_el2 =3D ENCODE_AA64_CP_REG(3, 4, 2, 0, 0), + .vhe_redir_to_el01 =3D ENCODE_AA64_CP_REG(3, 5, 2, 0, 0), .writefn =3D vmsa_ttbr_write, .resetvalue =3D 0, .raw_writefn =3D ra= w_write, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr0_s), offsetof(CPUARMState, cp15.ttbr0_ns) } }, @@ -2835,6 +2853,8 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] =3D { .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .fgt =3D FGT_TTBR1_EL1, .nv2_redirect_offset =3D 0x210 | NV2_REDIR_NV1, + .vhe_redir_to_el2 =3D ENCODE_AA64_CP_REG(3, 4, 2, 0, 1), + .vhe_redir_to_el01 =3D ENCODE_AA64_CP_REG(3, 5, 2, 0, 1), .writefn =3D vmsa_ttbr_write, .resetvalue =3D 0, .raw_writefn =3D ra= w_write, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr1_s), offsetof(CPUARMState, cp15.ttbr1_ns) } }, @@ -2843,6 +2863,8 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] =3D { .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .fgt =3D FGT_TCR_EL1, .nv2_redirect_offset =3D 0x120 | NV2_REDIR_NV1, + .vhe_redir_to_el2 =3D ENCODE_AA64_CP_REG(3, 4, 2, 0, 2), + .vhe_redir_to_el01 =3D ENCODE_AA64_CP_REG(3, 5, 2, 0, 2), .writefn =3D vmsa_tcr_el12_write, .raw_writefn =3D raw_write, .resetvalue =3D 0, @@ -3054,6 +3076,8 @@ static const ARMCPRegInfo lpae_cp_reginfo[] =3D { .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .fgt =3D FGT_AMAIR_EL1, .nv2_redirect_offset =3D 0x148 | NV2_REDIR_NV1, + .vhe_redir_to_el2 =3D ENCODE_AA64_CP_REG(3, 4, 10, 3, 0), + .vhe_redir_to_el01 =3D ENCODE_AA64_CP_REG(3, 5, 10, 3, 0), .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, /* AMAIR1 is mapped to AMAIR_EL1[63:32] */ { .name =3D "AMAIR1", .cp =3D 15, .crn =3D 10, .crm =3D 3, .opc1 =3D 0= , .opc2 =3D 1, @@ -3569,12 +3593,16 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .opc0 =3D 3, .opc1 =3D 0, .crn =3D 4, .crm =3D 0, .opc2 =3D 1, .access =3D PL1_RW, .accessfn =3D access_nv1, .nv2_redirect_offset =3D 0x230 | NV2_REDIR_NV1, + .vhe_redir_to_el2 =3D ENCODE_AA64_CP_REG(3, 4, 4, 0, 1), + .vhe_redir_to_el01 =3D ENCODE_AA64_CP_REG(3, 5, 4, 0, 1), .fieldoffset =3D offsetof(CPUARMState, elr_el[1]) }, { .name =3D "SPSR_EL1", .state =3D ARM_CP_STATE_AA64, .type =3D ARM_CP_ALIAS, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 4, .crm =3D 0, .opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_nv1, .nv2_redirect_offset =3D 0x160 | NV2_REDIR_NV1, + .vhe_redir_to_el2 =3D ENCODE_AA64_CP_REG(3, 4, 4, 0, 0), + .vhe_redir_to_el01 =3D ENCODE_AA64_CP_REG(3, 5, 4, 0, 0), .fieldoffset =3D offsetof(CPUARMState, banked_spsr[BANK_SVC]) }, /* * We rely on the access checks not allowing the guest to write to the @@ -4417,136 +4445,6 @@ static CPAccessResult access_el1nvvct(CPUARMState *= env, const ARMCPRegInfo *ri, return e2h_access(env, ri, isread); } =20 -static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu) -{ - struct E2HAlias { - uint32_t src_key, dst_key, new_key; - const char *src_name, *dst_name, *new_name; - bool (*feature)(const ARMISARegisters *id); - }; - -#define K(op0, op1, crn, crm, op2) \ - ENCODE_AA64_CP_REG(op0, op1, crn, crm, op2) - - static const struct E2HAlias aliases[] =3D { - { K(3, 0, 1, 0, 0), K(3, 4, 1, 0, 0), K(3, 5, 1, 0, 0), - "SCTLR_EL1", "SCTLR_EL2", "SCTLR_EL12" }, - { K(3, 0, 1, 0, 3), K(3, 4, 1, 0, 3), K(3, 5, 1, 0, 3), - "SCTLR2_EL1", "SCTLR2_EL2", "SCTLR2_EL12", isar_feature_aa64_sct= lr2 }, - { K(3, 0, 1, 0, 2), K(3, 4, 1, 1, 2), K(3, 5, 1, 0, 2), - "CPACR_EL1", "CPTR_EL2", "CPACR_EL12" }, - { K(3, 0, 2, 0, 0), K(3, 4, 2, 0, 0), K(3, 5, 2, 0, 0), - "TTBR0_EL1", "TTBR0_EL2", "TTBR0_EL12" }, - { K(3, 0, 2, 0, 1), K(3, 4, 2, 0, 1), K(3, 5, 2, 0, 1), - "TTBR1_EL1", "TTBR1_EL2", "TTBR1_EL12" }, - { K(3, 0, 2, 0, 2), K(3, 4, 2, 0, 2), K(3, 5, 2, 0, 2), - "TCR_EL1", "TCR_EL2", "TCR_EL12" }, - { K(3, 0, 2, 0, 3), K(3, 4, 2, 0, 3), K(3, 5, 2, 0, 3), - "TCR2_EL1", "TCR2_EL2", "TCR2_EL12", isar_feature_aa64_tcr2 }, - { K(3, 0, 4, 0, 0), K(3, 4, 4, 0, 0), K(3, 5, 4, 0, 0), - "SPSR_EL1", "SPSR_EL2", "SPSR_EL12" }, - { K(3, 0, 4, 0, 1), K(3, 4, 4, 0, 1), K(3, 5, 4, 0, 1), - "ELR_EL1", "ELR_EL2", "ELR_EL12" }, - { K(3, 0, 5, 1, 0), K(3, 4, 5, 1, 0), K(3, 5, 5, 1, 0), - "AFSR0_EL1", "AFSR0_EL2", "AFSR0_EL12" }, - { K(3, 0, 5, 1, 1), K(3, 4, 5, 1, 1), K(3, 5, 5, 1, 1), - "AFSR1_EL1", "AFSR1_EL2", "AFSR1_EL12" }, - { K(3, 0, 5, 2, 0), K(3, 4, 5, 2, 0), K(3, 5, 5, 2, 0), - "ESR_EL1", "ESR_EL2", "ESR_EL12" }, - { K(3, 0, 6, 0, 0), K(3, 4, 6, 0, 0), K(3, 5, 6, 0, 0), - "FAR_EL1", "FAR_EL2", "FAR_EL12" }, - { K(3, 0, 10, 2, 0), K(3, 4, 10, 2, 0), K(3, 5, 10, 2, 0), - "MAIR_EL1", "MAIR_EL2", "MAIR_EL12" }, - { K(3, 0, 10, 3, 0), K(3, 4, 10, 3, 0), K(3, 5, 10, 3, 0), - "AMAIR_EL1", "AMAIR_EL2", "AMAIR_EL12" }, - { K(3, 0, 12, 0, 0), K(3, 4, 12, 0, 0), K(3, 5, 12, 0, 0), - "VBAR_EL1", "VBAR_EL2", "VBAR_EL12" }, - { K(3, 0, 13, 0, 1), K(3, 4, 13, 0, 1), K(3, 5, 13, 0, 1), - "CONTEXTIDR_EL1", "CONTEXTIDR_EL2", "CONTEXTIDR_EL12" }, - { K(3, 0, 14, 1, 0), K(3, 4, 14, 1, 0), K(3, 5, 14, 1, 0), - "CNTKCTL_EL1", "CNTHCTL_EL2", "CNTKCTL_EL12" }, - - { K(3, 0, 1, 2, 0), K(3, 4, 1, 2, 0), K(3, 5, 1, 2, 0), - "ZCR_EL1", "ZCR_EL2", "ZCR_EL12", isar_feature_aa64_sve }, - { K(3, 0, 1, 2, 6), K(3, 4, 1, 2, 6), K(3, 5, 1, 2, 6), - "SMCR_EL1", "SMCR_EL2", "SMCR_EL12", isar_feature_aa64_sme }, - - { K(3, 0, 5, 6, 0), K(3, 4, 5, 6, 0), K(3, 5, 5, 6, 0), - "TFSR_EL1", "TFSR_EL2", "TFSR_EL12", isar_feature_aa64_mte }, - - { K(3, 0, 13, 0, 7), K(3, 4, 13, 0, 7), K(3, 5, 13, 0, 7), - "SCXTNUM_EL1", "SCXTNUM_EL2", "SCXTNUM_EL12", - isar_feature_aa64_scxtnum }, - - /* TODO: ARMv8.2-SPE -- PMSCR_EL2 */ - /* TODO: ARMv8.4-Trace -- TRFCR_EL2 */ - }; -#undef K - - size_t i; - - for (i =3D 0; i < ARRAY_SIZE(aliases); i++) { - const struct E2HAlias *a =3D &aliases[i]; - ARMCPRegInfo *src_reg, *dst_reg, *new_reg; - bool ok; - - if (a->feature && !a->feature(&cpu->isar)) { - continue; - } - - src_reg =3D g_hash_table_lookup(cpu->cp_regs, - (gpointer)(uintptr_t)a->src_key); - dst_reg =3D g_hash_table_lookup(cpu->cp_regs, - (gpointer)(uintptr_t)a->dst_key); - g_assert(src_reg !=3D NULL); - g_assert(dst_reg !=3D NULL); - - /* Cross-compare names to detect typos in the keys. */ - g_assert(strcmp(src_reg->name, a->src_name) =3D=3D 0); - g_assert(strcmp(dst_reg->name, a->dst_name) =3D=3D 0); - - /* Create alias before redirection so we dup the right data. */ - new_reg =3D g_memdup(src_reg, sizeof(ARMCPRegInfo)); - - new_reg->name =3D a->new_name; - new_reg->type |=3D ARM_CP_ALIAS; - /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place. */ - new_reg->access &=3D PL2_RW | PL3_RW; - /* The new_reg op fields are as per new_key, not the target reg */ - new_reg->crn =3D (a->new_key & CP_REG_ARM64_SYSREG_CRN_MASK) - >> CP_REG_ARM64_SYSREG_CRN_SHIFT; - new_reg->crm =3D (a->new_key & CP_REG_ARM64_SYSREG_CRM_MASK) - >> CP_REG_ARM64_SYSREG_CRM_SHIFT; - new_reg->opc0 =3D (a->new_key & CP_REG_ARM64_SYSREG_OP0_MASK) - >> CP_REG_ARM64_SYSREG_OP0_SHIFT; - new_reg->opc1 =3D (a->new_key & CP_REG_ARM64_SYSREG_OP1_MASK) - >> CP_REG_ARM64_SYSREG_OP1_SHIFT; - new_reg->opc2 =3D (a->new_key & CP_REG_ARM64_SYSREG_OP2_MASK) - >> CP_REG_ARM64_SYSREG_OP2_SHIFT; - new_reg->vhe_redir_to_el01 =3D a->src_key; - new_reg->readfn =3D NULL; - new_reg->writefn =3D NULL; - new_reg->accessfn =3D NULL; - new_reg->fieldoffset =3D 0; - - /* - * If the _EL1 register is redirected to memory by FEAT_NV2, - * then it shares the offset with the _EL12 register, - * and which one is redirected depends on HCR_EL2.NV1. - */ - if (new_reg->nv2_redirect_offset) { - assert(new_reg->nv2_redirect_offset & NV2_REDIR_NV1); - new_reg->nv2_redirect_offset &=3D ~NV2_REDIR_NV1; - new_reg->nv2_redirect_offset |=3D NV2_REDIR_NO_NV1; - } - - ok =3D g_hash_table_insert(cpu->cp_regs, - (gpointer)(uintptr_t)a->new_key, new_reg); - g_assert(ok); - - src_reg->vhe_redir_to_el2 =3D a->dst_key; - } -} #endif =20 static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo = *ri, @@ -4839,6 +4737,8 @@ static const ARMCPRegInfo zcr_reginfo[] =3D { { .name =3D "ZCR_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, .nv2_redirect_offset =3D 0x1e0 | NV2_REDIR_NV1, + .vhe_redir_to_el2 =3D ENCODE_AA64_CP_REG(3, 4, 1, 2, 0), + .vhe_redir_to_el01 =3D ENCODE_AA64_CP_REG(3, 5, 1, 2, 0), .access =3D PL1_RW, .type =3D ARM_CP_SVE, .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[1]), .writefn =3D zcr_write, .raw_writefn =3D raw_write }, @@ -4984,6 +4884,8 @@ static const ARMCPRegInfo sme_reginfo[] =3D { { .name =3D "SMCR_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 1, .crm =3D 2, .opc2 =3D 6, .nv2_redirect_offset =3D 0x1f0 | NV2_REDIR_NV1, + .vhe_redir_to_el2 =3D ENCODE_AA64_CP_REG(3, 4, 1, 2, 6), + .vhe_redir_to_el01 =3D ENCODE_AA64_CP_REG(3, 5, 1, 2, 6), .access =3D PL1_RW, .type =3D ARM_CP_SME, .fieldoffset =3D offsetof(CPUARMState, vfp.smcr_el[1]), .writefn =3D smcr_write, .raw_writefn =3D raw_write }, @@ -5429,6 +5331,8 @@ static const ARMCPRegInfo mte_reginfo[] =3D { .opc0 =3D 3, .opc1 =3D 0, .crn =3D 5, .crm =3D 6, .opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_tfsr_el1, .nv2_redirect_offset =3D 0x190 | NV2_REDIR_NV1, + .vhe_redir_to_el2 =3D ENCODE_AA64_CP_REG(3, 4, 5, 6, 0), + .vhe_redir_to_el01 =3D ENCODE_AA64_CP_REG(3, 5, 5, 6, 0), .fieldoffset =3D offsetof(CPUARMState, cp15.tfsr_el[1]) }, { .name =3D "TFSR_EL2", .state =3D ARM_CP_STATE_AA64, .type =3D ARM_CP_NV2_REDIRECT, @@ -5604,6 +5508,8 @@ static const ARMCPRegInfo scxtnum_reginfo[] =3D { .access =3D PL1_RW, .accessfn =3D access_scxtnum_el1, .fgt =3D FGT_SCXTNUM_EL1, .nv2_redirect_offset =3D 0x188 | NV2_REDIR_NV1, + .vhe_redir_to_el2 =3D ENCODE_AA64_CP_REG(3, 4, 13, 0, 7), + .vhe_redir_to_el01 =3D ENCODE_AA64_CP_REG(3, 5, 13, 0, 7), .fieldoffset =3D offsetof(CPUARMState, scxtnum_el[1]) }, { .name =3D "SCXTNUM_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 13, .crm =3D 0, .opc2 =3D 7, @@ -5948,6 +5854,8 @@ static const ARMCPRegInfo sctlr2_reginfo[] =3D { .opc0 =3D 3, .opc1 =3D 0, .opc2 =3D 3, .crn =3D 1, .crm =3D 0, .access =3D PL1_RW, .accessfn =3D sctlr2_el1_access, .writefn =3D sctlr2_el1_write, .fgt =3D FGT_SCTLR_EL1, + .vhe_redir_to_el2 =3D ENCODE_AA64_CP_REG(3, 4, 1, 0, 3), + .vhe_redir_to_el01 =3D ENCODE_AA64_CP_REG(3, 5, 1, 0, 3), .nv2_redirect_offset =3D 0x278 | NV2_REDIR_NV1, .fieldoffset =3D offsetof(CPUARMState, cp15.sctlr2_el[1]) }, { .name =3D "SCTLR2_EL2", .state =3D ARM_CP_STATE_AA64, @@ -6008,6 +5916,8 @@ static const ARMCPRegInfo tcr2_reginfo[] =3D { .opc0 =3D 3, .opc1 =3D 0, .opc2 =3D 3, .crn =3D 2, .crm =3D 0, .access =3D PL1_RW, .accessfn =3D tcr2_el1_access, .writefn =3D tcr2_el1_write, .fgt =3D FGT_TCR_EL1, + .vhe_redir_to_el2 =3D ENCODE_AA64_CP_REG(3, 4, 2, 0, 3), + .vhe_redir_to_el01 =3D ENCODE_AA64_CP_REG(3, 5, 2, 0, 3), .nv2_redirect_offset =3D 0x270 | NV2_REDIR_NV1, .fieldoffset =3D offsetof(CPUARMState, cp15.tcr2_el[1]) }, { .name =3D "TCR2_EL2", .state =3D ARM_CP_STATE_AA64, @@ -7104,6 +7014,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) .accessfn =3D access_nv1, .fgt =3D FGT_VBAR_EL1, .nv2_redirect_offset =3D 0x250 | NV2_REDIR_NV1, + .vhe_redir_to_el2 =3D ENCODE_AA64_CP_REG(3, 4, 12, 0, 0), + .vhe_redir_to_el01 =3D ENCODE_AA64_CP_REG(3, 5, 12, 0, 0), .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.vbar_s), offsetof(CPUARMState, cp15.vbar_ns) }, .resetvalue =3D 0 }, @@ -7118,6 +7030,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 1, .crm =3D 0, .opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .fgt =3D FGT_SCTLR_EL1, + .vhe_redir_to_el2 =3D ENCODE_AA64_CP_REG(3, 4, 1, 0, 0), + .vhe_redir_to_el01 =3D ENCODE_AA64_CP_REG(3, 5, 1, 0, 0), .nv2_redirect_offset =3D 0x110 | NV2_REDIR_NV1, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.sctlr_s), offsetof(CPUARMState, cp15.sctlr_ns) }, @@ -7252,16 +7166,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) } =20 define_pm_cpregs(cpu); - -#ifndef CONFIG_USER_ONLY - /* - * Register redirections and aliases must be done last, - * after the registers from the other extensions have been defined. - */ - if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu= )) { - define_arm_vh_e2h_redirects_aliases(cpu); - } -#endif } =20 /* @@ -7394,6 +7298,8 @@ static void add_cpreg_to_hashtable_aa32(ARMCPU *cpu, = ARMCPRegInfo *r) r->crm, r->opc1, r->opc2); =20 assert(!(r->type & ARM_CP_ADD_TLBI_NXS)); /* aa64 only */ + r->vhe_redir_to_el2 =3D 0; + r->vhe_redir_to_el01 =3D 0; =20 switch (r->secure) { case ARM_CP_SECSTATE_NS: @@ -7448,6 +7354,63 @@ static void add_cpreg_to_hashtable_aa64(ARMCPU *cpu,= ARMCPRegInfo *r) ARM_CP_SECSTATE_NS, nxs_key); } =20 + if (!r->vhe_redir_to_el01) { + assert(!r->vhe_redir_to_el2); + } else if (!arm_feature(&cpu->env, ARM_FEATURE_EL2) || + !cpu_isar_feature(aa64_vh, cpu)) { + r->vhe_redir_to_el2 =3D 0; + r->vhe_redir_to_el01 =3D 0; + } else { + /* Create the FOO_EL12 alias. */ + ARMCPRegInfo *r2 =3D alloc_cpreg(r, "2"); + uint32_t key2 =3D r->vhe_redir_to_el01; + + /* + * Clear EL1 redirection on the FOO_EL1 reg; + * Clear EL2 redirection on the FOO_EL12 reg; + * Install redirection from FOO_EL12 back to FOO_EL1. + */ + r->vhe_redir_to_el01 =3D 0; + r2->vhe_redir_to_el2 =3D 0; + r2->vhe_redir_to_el01 =3D key; + + r2->type |=3D ARM_CP_ALIAS | ARM_CP_NO_RAW; + /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place. */ + r2->access &=3D PL2_RW | PL3_RW; + /* The new_reg op fields are as per new_key, not the target reg */ + r2->crn =3D (key2 & CP_REG_ARM64_SYSREG_CRN_MASK) + >> CP_REG_ARM64_SYSREG_CRN_SHIFT; + r2->crm =3D (key2 & CP_REG_ARM64_SYSREG_CRM_MASK) + >> CP_REG_ARM64_SYSREG_CRM_SHIFT; + r2->opc0 =3D (key2 & CP_REG_ARM64_SYSREG_OP0_MASK) + >> CP_REG_ARM64_SYSREG_OP0_SHIFT; + r2->opc1 =3D (key2 & CP_REG_ARM64_SYSREG_OP1_MASK) + >> CP_REG_ARM64_SYSREG_OP1_SHIFT; + r2->opc2 =3D (key2 & CP_REG_ARM64_SYSREG_OP2_MASK) + >> CP_REG_ARM64_SYSREG_OP2_SHIFT; + + /* Non-redirected access to this register will abort. */ + r2->readfn =3D NULL; + r2->writefn =3D NULL; + r2->raw_readfn =3D NULL; + r2->raw_writefn =3D NULL; + r2->accessfn =3D NULL; + r2->fieldoffset =3D 0; + + /* + * If the _EL1 register is redirected to memory by FEAT_NV2, + * then it shares the offset with the _EL12 register, + * and which one is redirected depends on HCR_EL2.NV1. + */ + if (r2->nv2_redirect_offset) { + assert(r2->nv2_redirect_offset & NV2_REDIR_NV1); + r2->nv2_redirect_offset &=3D ~NV2_REDIR_NV1; + r2->nv2_redirect_offset |=3D NV2_REDIR_NO_NV1; + } + add_cpreg_to_hashtable(cpu, r2, ARM_CP_STATE_AA64, + ARM_CP_SECSTATE_NS, key2); + } + add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA64, ARM_CP_SECSTATE_NS, key); } --=20 2.43.0 From nobody Sun Sep 28 15:26:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell --- target/arm/helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index c5a8ef50493..a18d920ac18 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5007,7 +5007,7 @@ static uint64_t id_pfr1_read(CPUARMState *env, const = ARMCPRegInfo *ri) uint64_t pfr1 =3D GET_IDREG(&cpu->isar, ID_PFR1); =20 if (env->gicv3state) { - pfr1 |=3D 1 << 28; + pfr1 =3D FIELD_DP64(pfr1, ID_PFR1, GIC, 1); } return pfr1; } @@ -5018,7 +5018,7 @@ static uint64_t id_aa64pfr0_read(CPUARMState *env, co= nst ARMCPRegInfo *ri) uint64_t pfr0 =3D GET_IDREG(&cpu->isar, ID_AA64PFR0); =20 if (env->gicv3state) { - pfr0 |=3D 1 << 24; + pfr0 =3D FIELD_DP64(pfr0, ID_AA64PFR0, GIC, 1); } return pfr0; } --=20 2.43.0 From nobody Sun Sep 28 15:26:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758896154; cv=none; d=zohomail.com; s=zohoarc; b=QHhhFNYWFxwrwXXQiqx2dQ+AkuNDwHeHLamgOd9mMMH/VunJk5s8k3l7AdHxu9np7sblRvA7fFyvBhwZxo13TXRqJoc+cHYXour57ZAooUhH6qSfUUXp4uOv51elo86AKanlTTfQ5n45fCoVYZWBuQfg/1sQEfTEkpDXJkMPpRE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758896154; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=71SPKxC6TrHmGazKirT7T3wwRBAuIbbjNemK5xYBRvE=; b=B3uk221XdO2TIPpEEWWyKdQkF8bOrpOEj+r2v6FatYkOcw2R9y8+doutPZ+i/vGn8k6efnu4dn15Nux65LbflyX7v7Hs/QtM2LBm6OjFbQDF6V6fjEAeD8PAukzidEFEIV2XSEtk81rdR3vLwzhgX9whWvfz23cBtueQ6VaOOEs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17588961547802.2964077065969377; Fri, 26 Sep 2025 07:15:54 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v299t-0000jr-Q1; Fri, 26 Sep 2025 10:10:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v299Z-0000Ih-No for qemu-devel@nongnu.org; Fri, 26 Sep 2025 10:10:30 -0400 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1v298f-0005nH-Lq for qemu-devel@nongnu.org; Fri, 26 Sep 2025 10:10:21 -0400 Received: by mail-wr1-x42d.google.com with SMTP id ffacd0b85a97d-3b9edf4cf6cso2254996f8f.3 for ; Fri, 26 Sep 2025 07:09:30 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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Fri, 26 Sep 2025 07:09:27 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 40/44] target/arm: Convert power control DPRINTF() uses to trace events Date: Fri, 26 Sep 2025 15:08:40 +0100 Message-ID: <20250926140844.1493020-41-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250926140844.1493020-1-peter.maydell@linaro.org> References: <20250926140844.1493020-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758896155286116600 From: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/arm-powerctl.c | 26 ++++++++------------------ target/arm/trace-events | 6 ++++++ 2 files changed, 14 insertions(+), 18 deletions(-) diff --git a/target/arm/arm-powerctl.c b/target/arm/arm-powerctl.c index 20c70c7d6bb..a788376d1d3 100644 --- a/target/arm/arm-powerctl.c +++ b/target/arm/arm-powerctl.c @@ -17,24 +17,12 @@ #include "qemu/main-loop.h" #include "system/tcg.h" #include "target/arm/multiprocessing.h" - -#ifndef DEBUG_ARM_POWERCTL -#define DEBUG_ARM_POWERCTL 0 -#endif - -#define DPRINTF(fmt, args...) \ - do { \ - if (DEBUG_ARM_POWERCTL) { \ - fprintf(stderr, "[ARM]%s: " fmt , __func__, ##args); \ - } \ - } while (0) +#include "trace.h" =20 CPUState *arm_get_cpu_by_id(uint64_t id) { CPUState *cpu; =20 - DPRINTF("cpu %" PRId64 "\n", id); - CPU_FOREACH(cpu) { ARMCPU *armcpu =3D ARM_CPU(cpu); =20 @@ -102,9 +90,9 @@ int arm_set_cpu_on(uint64_t cpuid, uint64_t entry, uint6= 4_t context_id, =20 assert(bql_locked()); =20 - DPRINTF("cpu %" PRId64 " (EL %d, %s) @ 0x%" PRIx64 " with R0 =3D 0x%" = PRIx64 - "\n", cpuid, target_el, target_aa64 ? "aarch64" : "aarch32", e= ntry, - context_id); + trace_arm_powerctl_set_cpu_on(cpuid, target_el, + target_aa64 ? "aarch64" : "aarch32", + entry, context_id); =20 /* requested EL level need to be in the 1 to 3 range */ assert((target_el > 0) && (target_el < 4)); @@ -208,6 +196,8 @@ int arm_set_cpu_on_and_reset(uint64_t cpuid) =20 assert(bql_locked()); =20 + trace_arm_powerctl_set_cpu_on_and_reset(cpuid); + /* Retrieve the cpu we are powering up */ target_cpu_state =3D arm_get_cpu_by_id(cpuid); if (!target_cpu_state) { @@ -261,7 +251,7 @@ int arm_set_cpu_off(uint64_t cpuid) =20 assert(bql_locked()); =20 - DPRINTF("cpu %" PRId64 "\n", cpuid); + trace_arm_powerctl_set_cpu_off(cpuid); =20 /* change to the cpu we are powering up */ target_cpu_state =3D arm_get_cpu_by_id(cpuid); @@ -297,7 +287,7 @@ int arm_reset_cpu(uint64_t cpuid) =20 assert(bql_locked()); =20 - DPRINTF("cpu %" PRId64 "\n", cpuid); + trace_arm_powerctl_set_cpu_off(cpuid); =20 /* change to the cpu we are resetting */ target_cpu_state =3D arm_get_cpu_by_id(cpuid); diff --git a/target/arm/trace-events b/target/arm/trace-events index 4438dce7bec..252c05a9ebe 100644 --- a/target/arm/trace-events +++ b/target/arm/trace-events @@ -13,3 +13,9 @@ arm_gt_update_irq(int timer, int irqstate) "gt_update_irq= : timer %d irqstate %d" =20 # kvm.c kvm_arm_fixup_msi_route(uint64_t iova, uint64_t gpa) "MSI iova =3D 0x%"PRI= x64" is translated into 0x%"PRIx64 + +# arm-powerctl.c +arm_powerctl_set_cpu_on(uint64_t mp_aff, unsigned target_el, const char *m= ode, uint64_t entry, uint64_t context_id) "cpu %" PRIu64 " (EL %u, %s) @ 0x= %" PRIx64 " with R0 =3D 0x%" PRIx64 +arm_powerctl_set_cpu_on_and_reset(uint64_t mp_aff) "cpu %" PRIu64 +arm_powerctl_set_cpu_off(uint64_t mp_aff) "cpu %" PRIu64 +arm_powerctl_reset_cpu(uint64_t mp_aff) "cpu %" PRIu64 --=20 2.43.0 From nobody Sun Sep 28 15:26:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758895954; cv=none; d=zohomail.com; s=zohoarc; b=LL2aG+mqABsgPUVu5qCrp2AMJhGUAVOMfbBqpntn5z/31VTqJU/XU6YiXrUk9OTRS4ZFMs03lCHqptzHMI8XNcHgjjCZTIOcSca00apov46tpIoG06MFXx9y5B2WeZn1BQGoDi6EsP3JOAhdgmr7ktKD7gHToCuW58CToeiZ0TU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758895954; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=r1Aatavlnp9I8vVGVCmlOFy7hlPRhQsimFryDicIoL4=; b=mN2CnK2ZFcJ0Bu4rbPcTe+Jc8rp+U3opfZl2UVMC9f84Pkm6SmlTK/LgaFKwOCFqi/0gUwMDy/u1PRxzqhGfluumpeDD3+gyxFVMSVz9kHuZnUEo0uaKhqBh+792sJm0eip8C36/RqleJ+wEycCrNQtOKCB0uGFPVf9NDhHGAHM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1758895954264309.0827644602823; Fri, 26 Sep 2025 07:12:34 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v29AF-00014Z-DI; Fri, 26 Sep 2025 10:11:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v299R-0000Gu-7z for qemu-devel@nongnu.org; Fri, 26 Sep 2025 10:10:21 -0400 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1v298g-0005nc-P4 for qemu-devel@nongnu.org; Fri, 26 Sep 2025 10:10:20 -0400 Received: by mail-wr1-x42c.google.com with SMTP id ffacd0b85a97d-3fa528f127fso1672914f8f.1 for ; Fri, 26 Sep 2025 07:09:30 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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If that is the * highest implemented EL, then cpu_reset has already done diff --git a/target/arm/trace-events b/target/arm/trace-events index 252c05a9ebe..badff2b2e46 100644 --- a/target/arm/trace-events +++ b/target/arm/trace-events @@ -14,6 +14,9 @@ arm_gt_update_irq(int timer, int irqstate) "gt_update_irq= : timer %d irqstate %d" # kvm.c kvm_arm_fixup_msi_route(uint64_t iova, uint64_t gpa) "MSI iova =3D 0x%"PRI= x64" is translated into 0x%"PRIx64 =20 +# cpu.c +arm_emulate_firmware_reset(uint64_t mp_aff, unsigned target_el) "cpu %" PR= Iu64 " @EL%u" + # arm-powerctl.c arm_powerctl_set_cpu_on(uint64_t mp_aff, unsigned target_el, const char *m= ode, uint64_t entry, uint64_t context_id) "cpu %" PRIu64 " (EL %u, %s) @ 0x= %" PRIx64 " with R0 =3D 0x%" PRIx64 arm_powerctl_set_cpu_on_and_reset(uint64_t mp_aff) "cpu %" PRIu64 --=20 2.43.0 From nobody Sun Sep 28 15:26:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758896555; cv=none; d=zohomail.com; s=zohoarc; b=jbZfXIUb/+VWNahA7wXXkmnc4qjxDoz7QEGhHur0zd4pOXZ3nXg2GP4K8l3mwssHoqgD3xSV8m4clUvnhSWcoeAsTZTmpfcwVkDPVFgDpWDm/VfJw94vABIF2M7tD7lKp/jW7WYqxNmClnWTciwvoNefXefw+qJAXe7wWQxs3i4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758896555; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=IHG8pw94kQh9rgj79VlxQY7WE57C9ajUY74LgQzgrVQ=; b=O5/X0Jmio64yffWCedfILTIP7MUyRWRW9e/a/8wrjPTOChSLzpYSkXCUvU1uKHCIdow1G+6usAN+p0BLJO/xHUy9x41Mf1IZuxG135fU4wx09DPX0mQqOIDTWVw+BFA0F2LiK27+VD/TFq7tOQnA3HaVqGfigjsswXTxe1hJg/E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1758896555914747.1278407891947; Fri, 26 Sep 2025 07:22:35 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v29AL-0001Ko-8F; Fri, 26 Sep 2025 10:11:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v299Y-0000Ij-Nb for qemu-devel@nongnu.org; Fri, 26 Sep 2025 10:10:30 -0400 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1v298g-0005nn-35 for qemu-devel@nongnu.org; Fri, 26 Sep 2025 10:10:25 -0400 Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-46e37d10f3eso13722505e9.0 for ; Fri, 26 Sep 2025 07:09:32 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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Fri, 26 Sep 2025 07:09:28 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 42/44] target/arm: Trace vCPU reset call Date: Fri, 26 Sep 2025 15:08:42 +0100 Message-ID: <20250926140844.1493020-43-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250926140844.1493020-1-peter.maydell@linaro.org> References: <20250926140844.1493020-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758896556843116600 From: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/cpu.c | 2 ++ target/arm/trace-events | 1 + 2 files changed, 3 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index f8e6749ff99..30e29fd3153 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -227,6 +227,8 @@ static void arm_cpu_reset_hold(Object *obj, ResetType t= ype) ARMCPUClass *acc =3D ARM_CPU_GET_CLASS(obj); CPUARMState *env =3D &cpu->env; =20 + trace_arm_cpu_reset(arm_cpu_mp_affinity(cpu)); + if (acc->parent_phases.hold) { acc->parent_phases.hold(obj, type); } diff --git a/target/arm/trace-events b/target/arm/trace-events index badff2b2e46..72a2c7d0969 100644 --- a/target/arm/trace-events +++ b/target/arm/trace-events @@ -15,6 +15,7 @@ arm_gt_update_irq(int timer, int irqstate) "gt_update_irq= : timer %d irqstate %d" kvm_arm_fixup_msi_route(uint64_t iova, uint64_t gpa) "MSI iova =3D 0x%"PRI= x64" is translated into 0x%"PRIx64 =20 # cpu.c +arm_cpu_reset(uint64_t mp_aff) "cpu %" PRIu64 arm_emulate_firmware_reset(uint64_t mp_aff, unsigned target_el) "cpu %" PR= Iu64 " @EL%u" =20 # arm-powerctl.c --=20 2.43.0 From nobody Sun Sep 28 15:26:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-410f2007372sm6338315f8f.16.2025.09.26.07.09.28 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Sep 2025 07:09:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758895770; x=1759500570; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Cc4zcF01yl9yKBh5po4rjcKYcL0XdnxPSWdnvEOIBH0=; b=UpzUPTnBHOb6LKebrWUgN1tTlLLgbmCQk66Tcb+1FDrBbfMwleuHKuQrixVinvKOJJ yfQztNiC5PX0qXEVyjlk/VDKqm8RnT1irpZETZp76JYGPFUpgTutAWB2KIBU8at6ltZ6 LyHMAT/acMvh3MuHWAhqtzGm+VlW4OUkr08BQ+BZPJMGgbq259UN4bBGSxcZB9ab0eT0 /GPTxqQ+22RGM/G8Or9OLx5rKCmey2pXlUtTTCVCZmD2M91cfeGqB1UA1WsL2AUns/cW ZjA/t4FyQHZ0GuqR3kh/11j7Eljm3q28+Zba2vCWIESq6rKsn5o52JD89mYQbYkvY0Lh Wk2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758895770; x=1759500570; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Cc4zcF01yl9yKBh5po4rjcKYcL0XdnxPSWdnvEOIBH0=; b=NQATjZxrW4XJs0iVRiZeEkFiQufB9OzqwW3/omyrv/EGZr2ggeyi7WixrmxRhm6VpA xNJqmxYFpdPSPtm8KP4d4GX76tun7j8jf7piUUqY2obHJ4ATyN8/EP+++TMdE115d6IM Gw4A1mhc7PAr1oDBSj16iitTs4HrBmXh5p3LxEgqJnMIpa9363UFsKOMPKOXd91fW7FC kUhbkkKZ77gzfY2shrOhK1hvmmaz2RaHIKqmF3N3SI3I5yFySbOffVA1mhXqgAlPvJV3 af7hZ5R1h34omoBPeSksRd6epeKDtBx/0ICangbvv8nyVR6DrtQTO8kpqzhM2+91G+2x OliQ== X-Gm-Message-State: AOJu0Yy15AV5ClS5azkxiZ6mq9k/XsFT/DT9se2ufZRmq6hsVXaXvYVR h5oSvMnSccdoESoDCHZIMgQtC29uHEe3k2n7kYg2ZmaQ5KRL5dHlhpwG6HPpYE772oStxpaKTtd Li20d X-Gm-Gg: ASbGncvUCTZuZfvHsopGBbRcMA3MvRvNtOA5wHWyfWam0KQtDNB6suAIUyFpdEya7c7 k30R2F3+D8V4REUZqHKARbDq//tStUUdRFe/zFcjXlvY4hicyubwE6yAt9hxodWtK+jAAfhe35b u29LUASt7bColzhQKp3+lT7oowLvxxD2Wv/njufGEG/l4xBZlxIFiutSiNfPTfQhieQyRlujcUn WBpgEMUTuhiNwrjaeZ+zLEddgQL8LDJQYmtFt73sk01Vsy06BKrg5BhwoaOw0Dx08x+NFHwMB4M ZaFVRKzWwkfL42q7f7O063GV/L+mcXIh71AAxHZEoAD3KGuoFteBbgXG+AarRTCpcGyKD22TT4X kZIKGrHkWJFJLwPyK5z+aC7FuuFTakfEv9tACE/M= X-Google-Smtp-Source: AGHT+IFMsgxsgjWFRf73ikZVdJIkiMzGTnHvEQrGZWzXmtYrvC5jrwuBffnvZBXAiu+35ObFxkRQpg== X-Received: by 2002:a05:600c:46cf:b0:46e:35eb:43a with SMTP id 5b1f17b1804b1-46e35eb07b0mr58298165e9.15.1758895769920; Fri, 26 Sep 2025 07:09:29 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 43/44] target/arm: Move ID register field defs to cpu-features.h Date: Fri, 26 Sep 2025 15:08:43 +0100 Message-ID: <20250926140844.1493020-44-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250926140844.1493020-1-peter.maydell@linaro.org> References: <20250926140844.1493020-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, T_SPF_HELO_TEMPERROR=0.01, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758896733121116600 Currently we define constants for the ID register fields in cpu.h. This means they're defined for a lot more code in QEMU than actually needs them. Move them to cpu-features.h, which is where we define the feature functions that test fields in these registers. There's only one place where we need to use some of these macro definitions that we weren't already including cpu-features.h: linux-user/arm/target_proc.h. Otherwise this patch is a pure movement of code from one file to the other. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- linux-user/arm/target_proc.h | 2 + target/arm/cpu-features.h | 410 +++++++++++++++++++++++++++++++++++ target/arm/cpu.h | 410 ----------------------------------- 3 files changed, 412 insertions(+), 410 deletions(-) diff --git a/linux-user/arm/target_proc.h b/linux-user/arm/target_proc.h index a4cd6948c60..a28d7231cdc 100644 --- a/linux-user/arm/target_proc.h +++ b/linux-user/arm/target_proc.h @@ -6,6 +6,8 @@ #ifndef ARM_TARGET_PROC_H #define ARM_TARGET_PROC_H =20 +#include "target/arm/cpu-features.h" /* for MIDR_EL1 field definitions */ + static int open_cpuinfo(CPUArchState *cpu_env, int fd) { ARMCPU *cpu =3D env_archcpu(cpu_env); diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 512eeaf551e..ad571e2ffee 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -25,6 +25,416 @@ #include "cpu.h" #include "cpu-sysregs.h" =20 +/* + * System register ID fields. + */ +FIELD(CLIDR_EL1, CTYPE1, 0, 3) +FIELD(CLIDR_EL1, CTYPE2, 3, 3) +FIELD(CLIDR_EL1, CTYPE3, 6, 3) +FIELD(CLIDR_EL1, CTYPE4, 9, 3) +FIELD(CLIDR_EL1, CTYPE5, 12, 3) +FIELD(CLIDR_EL1, CTYPE6, 15, 3) +FIELD(CLIDR_EL1, CTYPE7, 18, 3) +FIELD(CLIDR_EL1, LOUIS, 21, 3) +FIELD(CLIDR_EL1, LOC, 24, 3) +FIELD(CLIDR_EL1, LOUU, 27, 3) +FIELD(CLIDR_EL1, ICB, 30, 3) + +/* When FEAT_CCIDX is implemented */ +FIELD(CCSIDR_EL1, CCIDX_LINESIZE, 0, 3) +FIELD(CCSIDR_EL1, CCIDX_ASSOCIATIVITY, 3, 21) +FIELD(CCSIDR_EL1, CCIDX_NUMSETS, 32, 24) + +/* When FEAT_CCIDX is not implemented */ +FIELD(CCSIDR_EL1, LINESIZE, 0, 3) +FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10) +FIELD(CCSIDR_EL1, NUMSETS, 13, 15) + +FIELD(CTR_EL0, IMINLINE, 0, 4) +FIELD(CTR_EL0, L1IP, 14, 2) +FIELD(CTR_EL0, DMINLINE, 16, 4) +FIELD(CTR_EL0, ERG, 20, 4) +FIELD(CTR_EL0, CWG, 24, 4) +FIELD(CTR_EL0, IDC, 28, 1) +FIELD(CTR_EL0, DIC, 29, 1) +FIELD(CTR_EL0, TMINLINE, 32, 6) + +FIELD(MIDR_EL1, REVISION, 0, 4) +FIELD(MIDR_EL1, PARTNUM, 4, 12) +FIELD(MIDR_EL1, ARCHITECTURE, 16, 4) +FIELD(MIDR_EL1, VARIANT, 20, 4) +FIELD(MIDR_EL1, IMPLEMENTER, 24, 8) + +FIELD(ID_ISAR0, SWAP, 0, 4) +FIELD(ID_ISAR0, BITCOUNT, 4, 4) +FIELD(ID_ISAR0, BITFIELD, 8, 4) +FIELD(ID_ISAR0, CMPBRANCH, 12, 4) +FIELD(ID_ISAR0, COPROC, 16, 4) +FIELD(ID_ISAR0, DEBUG, 20, 4) +FIELD(ID_ISAR0, DIVIDE, 24, 4) + +FIELD(ID_ISAR1, ENDIAN, 0, 4) +FIELD(ID_ISAR1, EXCEPT, 4, 4) +FIELD(ID_ISAR1, EXCEPT_AR, 8, 4) +FIELD(ID_ISAR1, EXTEND, 12, 4) +FIELD(ID_ISAR1, IFTHEN, 16, 4) +FIELD(ID_ISAR1, IMMEDIATE, 20, 4) +FIELD(ID_ISAR1, INTERWORK, 24, 4) +FIELD(ID_ISAR1, JAZELLE, 28, 4) + +FIELD(ID_ISAR2, LOADSTORE, 0, 4) +FIELD(ID_ISAR2, MEMHINT, 4, 4) +FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4) +FIELD(ID_ISAR2, MULT, 12, 4) +FIELD(ID_ISAR2, MULTS, 16, 4) +FIELD(ID_ISAR2, MULTU, 20, 4) +FIELD(ID_ISAR2, PSR_AR, 24, 4) +FIELD(ID_ISAR2, REVERSAL, 28, 4) + +FIELD(ID_ISAR3, SATURATE, 0, 4) +FIELD(ID_ISAR3, SIMD, 4, 4) +FIELD(ID_ISAR3, SVC, 8, 4) +FIELD(ID_ISAR3, SYNCHPRIM, 12, 4) +FIELD(ID_ISAR3, TABBRANCH, 16, 4) +FIELD(ID_ISAR3, T32COPY, 20, 4) +FIELD(ID_ISAR3, TRUENOP, 24, 4) +FIELD(ID_ISAR3, T32EE, 28, 4) + +FIELD(ID_ISAR4, UNPRIV, 0, 4) +FIELD(ID_ISAR4, WITHSHIFTS, 4, 4) +FIELD(ID_ISAR4, WRITEBACK, 8, 4) +FIELD(ID_ISAR4, SMC, 12, 4) +FIELD(ID_ISAR4, BARRIER, 16, 4) +FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4) +FIELD(ID_ISAR4, PSR_M, 24, 4) +FIELD(ID_ISAR4, SWP_FRAC, 28, 4) + +FIELD(ID_ISAR5, SEVL, 0, 4) +FIELD(ID_ISAR5, AES, 4, 4) +FIELD(ID_ISAR5, SHA1, 8, 4) +FIELD(ID_ISAR5, SHA2, 12, 4) +FIELD(ID_ISAR5, CRC32, 16, 4) +FIELD(ID_ISAR5, RDM, 24, 4) +FIELD(ID_ISAR5, VCMA, 28, 4) + +FIELD(ID_ISAR6, JSCVT, 0, 4) +FIELD(ID_ISAR6, DP, 4, 4) +FIELD(ID_ISAR6, FHM, 8, 4) +FIELD(ID_ISAR6, SB, 12, 4) +FIELD(ID_ISAR6, SPECRES, 16, 4) +FIELD(ID_ISAR6, BF16, 20, 4) +FIELD(ID_ISAR6, I8MM, 24, 4) + +FIELD(ID_MMFR0, VMSA, 0, 4) +FIELD(ID_MMFR0, PMSA, 4, 4) +FIELD(ID_MMFR0, OUTERSHR, 8, 4) +FIELD(ID_MMFR0, SHARELVL, 12, 4) +FIELD(ID_MMFR0, TCM, 16, 4) +FIELD(ID_MMFR0, AUXREG, 20, 4) +FIELD(ID_MMFR0, FCSE, 24, 4) +FIELD(ID_MMFR0, INNERSHR, 28, 4) + +FIELD(ID_MMFR1, L1HVDVA, 0, 4) +FIELD(ID_MMFR1, L1UNIVA, 4, 4) +FIELD(ID_MMFR1, L1HVDSW, 8, 4) +FIELD(ID_MMFR1, L1UNISW, 12, 4) +FIELD(ID_MMFR1, L1HVD, 16, 4) +FIELD(ID_MMFR1, L1UNI, 20, 4) +FIELD(ID_MMFR1, L1TSTCLN, 24, 4) +FIELD(ID_MMFR1, BPRED, 28, 4) + +FIELD(ID_MMFR2, L1HVDFG, 0, 4) +FIELD(ID_MMFR2, L1HVDBG, 4, 4) +FIELD(ID_MMFR2, L1HVDRNG, 8, 4) +FIELD(ID_MMFR2, HVDTLB, 12, 4) +FIELD(ID_MMFR2, UNITLB, 16, 4) +FIELD(ID_MMFR2, MEMBARR, 20, 4) +FIELD(ID_MMFR2, WFISTALL, 24, 4) +FIELD(ID_MMFR2, HWACCFLG, 28, 4) + +FIELD(ID_MMFR3, CMAINTVA, 0, 4) +FIELD(ID_MMFR3, CMAINTSW, 4, 4) +FIELD(ID_MMFR3, BPMAINT, 8, 4) +FIELD(ID_MMFR3, MAINTBCST, 12, 4) +FIELD(ID_MMFR3, PAN, 16, 4) +FIELD(ID_MMFR3, COHWALK, 20, 4) +FIELD(ID_MMFR3, CMEMSZ, 24, 4) +FIELD(ID_MMFR3, SUPERSEC, 28, 4) + +FIELD(ID_MMFR4, SPECSEI, 0, 4) +FIELD(ID_MMFR4, AC2, 4, 4) +FIELD(ID_MMFR4, XNX, 8, 4) +FIELD(ID_MMFR4, CNP, 12, 4) +FIELD(ID_MMFR4, HPDS, 16, 4) +FIELD(ID_MMFR4, LSM, 20, 4) +FIELD(ID_MMFR4, CCIDX, 24, 4) +FIELD(ID_MMFR4, EVT, 28, 4) + +FIELD(ID_MMFR5, ETS, 0, 4) +FIELD(ID_MMFR5, NTLBPA, 4, 4) + +FIELD(ID_PFR0, STATE0, 0, 4) +FIELD(ID_PFR0, STATE1, 4, 4) +FIELD(ID_PFR0, STATE2, 8, 4) +FIELD(ID_PFR0, STATE3, 12, 4) +FIELD(ID_PFR0, CSV2, 16, 4) +FIELD(ID_PFR0, AMU, 20, 4) +FIELD(ID_PFR0, DIT, 24, 4) +FIELD(ID_PFR0, RAS, 28, 4) + +FIELD(ID_PFR1, PROGMOD, 0, 4) +FIELD(ID_PFR1, SECURITY, 4, 4) +FIELD(ID_PFR1, MPROGMOD, 8, 4) +FIELD(ID_PFR1, VIRTUALIZATION, 12, 4) +FIELD(ID_PFR1, GENTIMER, 16, 4) +FIELD(ID_PFR1, SEC_FRAC, 20, 4) +FIELD(ID_PFR1, VIRT_FRAC, 24, 4) +FIELD(ID_PFR1, GIC, 28, 4) + +FIELD(ID_PFR2, CSV3, 0, 4) +FIELD(ID_PFR2, SSBS, 4, 4) +FIELD(ID_PFR2, RAS_FRAC, 8, 4) + +FIELD(ID_AA64ISAR0, AES, 4, 4) +FIELD(ID_AA64ISAR0, SHA1, 8, 4) +FIELD(ID_AA64ISAR0, SHA2, 12, 4) +FIELD(ID_AA64ISAR0, CRC32, 16, 4) +FIELD(ID_AA64ISAR0, ATOMIC, 20, 4) +FIELD(ID_AA64ISAR0, TME, 24, 4) +FIELD(ID_AA64ISAR0, RDM, 28, 4) +FIELD(ID_AA64ISAR0, SHA3, 32, 4) +FIELD(ID_AA64ISAR0, SM3, 36, 4) +FIELD(ID_AA64ISAR0, SM4, 40, 4) +FIELD(ID_AA64ISAR0, DP, 44, 4) +FIELD(ID_AA64ISAR0, FHM, 48, 4) +FIELD(ID_AA64ISAR0, TS, 52, 4) +FIELD(ID_AA64ISAR0, TLB, 56, 4) +FIELD(ID_AA64ISAR0, RNDR, 60, 4) + +FIELD(ID_AA64ISAR1, DPB, 0, 4) +FIELD(ID_AA64ISAR1, APA, 4, 4) +FIELD(ID_AA64ISAR1, API, 8, 4) +FIELD(ID_AA64ISAR1, JSCVT, 12, 4) +FIELD(ID_AA64ISAR1, FCMA, 16, 4) +FIELD(ID_AA64ISAR1, LRCPC, 20, 4) +FIELD(ID_AA64ISAR1, GPA, 24, 4) +FIELD(ID_AA64ISAR1, GPI, 28, 4) +FIELD(ID_AA64ISAR1, FRINTTS, 32, 4) +FIELD(ID_AA64ISAR1, SB, 36, 4) +FIELD(ID_AA64ISAR1, SPECRES, 40, 4) +FIELD(ID_AA64ISAR1, BF16, 44, 4) +FIELD(ID_AA64ISAR1, DGH, 48, 4) +FIELD(ID_AA64ISAR1, I8MM, 52, 4) +FIELD(ID_AA64ISAR1, XS, 56, 4) +FIELD(ID_AA64ISAR1, LS64, 60, 4) + +FIELD(ID_AA64ISAR2, WFXT, 0, 4) +FIELD(ID_AA64ISAR2, RPRES, 4, 4) +FIELD(ID_AA64ISAR2, GPA3, 8, 4) +FIELD(ID_AA64ISAR2, APA3, 12, 4) +FIELD(ID_AA64ISAR2, MOPS, 16, 4) +FIELD(ID_AA64ISAR2, BC, 20, 4) +FIELD(ID_AA64ISAR2, PAC_FRAC, 24, 4) +FIELD(ID_AA64ISAR2, CLRBHB, 28, 4) +FIELD(ID_AA64ISAR2, SYSREG_128, 32, 4) +FIELD(ID_AA64ISAR2, SYSINSTR_128, 36, 4) +FIELD(ID_AA64ISAR2, PRFMSLC, 40, 4) +FIELD(ID_AA64ISAR2, RPRFM, 48, 4) +FIELD(ID_AA64ISAR2, CSSC, 52, 4) +FIELD(ID_AA64ISAR2, LUT, 56, 4) +FIELD(ID_AA64ISAR2, ATS1A, 60, 4) + +FIELD(ID_AA64PFR0, EL0, 0, 4) +FIELD(ID_AA64PFR0, EL1, 4, 4) +FIELD(ID_AA64PFR0, EL2, 8, 4) +FIELD(ID_AA64PFR0, EL3, 12, 4) +FIELD(ID_AA64PFR0, FP, 16, 4) +FIELD(ID_AA64PFR0, ADVSIMD, 20, 4) +FIELD(ID_AA64PFR0, GIC, 24, 4) +FIELD(ID_AA64PFR0, RAS, 28, 4) +FIELD(ID_AA64PFR0, SVE, 32, 4) +FIELD(ID_AA64PFR0, SEL2, 36, 4) +FIELD(ID_AA64PFR0, MPAM, 40, 4) +FIELD(ID_AA64PFR0, AMU, 44, 4) +FIELD(ID_AA64PFR0, DIT, 48, 4) +FIELD(ID_AA64PFR0, RME, 52, 4) +FIELD(ID_AA64PFR0, CSV2, 56, 4) +FIELD(ID_AA64PFR0, CSV3, 60, 4) + +FIELD(ID_AA64PFR1, BT, 0, 4) +FIELD(ID_AA64PFR1, SSBS, 4, 4) +FIELD(ID_AA64PFR1, MTE, 8, 4) +FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4) +FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4) +FIELD(ID_AA64PFR1, SME, 24, 4) +FIELD(ID_AA64PFR1, RNDR_TRAP, 28, 4) +FIELD(ID_AA64PFR1, CSV2_FRAC, 32, 4) +FIELD(ID_AA64PFR1, NMI, 36, 4) +FIELD(ID_AA64PFR1, MTE_FRAC, 40, 4) +FIELD(ID_AA64PFR1, GCS, 44, 4) +FIELD(ID_AA64PFR1, THE, 48, 4) +FIELD(ID_AA64PFR1, MTEX, 52, 4) +FIELD(ID_AA64PFR1, DF2, 56, 4) +FIELD(ID_AA64PFR1, PFAR, 60, 4) + +FIELD(ID_AA64MMFR0, PARANGE, 0, 4) +FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) +FIELD(ID_AA64MMFR0, BIGEND, 8, 4) +FIELD(ID_AA64MMFR0, SNSMEM, 12, 4) +FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4) +FIELD(ID_AA64MMFR0, TGRAN16, 20, 4) +FIELD(ID_AA64MMFR0, TGRAN64, 24, 4) +FIELD(ID_AA64MMFR0, TGRAN4, 28, 4) +FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4) +FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4) +FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4) +FIELD(ID_AA64MMFR0, EXS, 44, 4) +FIELD(ID_AA64MMFR0, FGT, 56, 4) +FIELD(ID_AA64MMFR0, ECV, 60, 4) + +FIELD(ID_AA64MMFR1, HAFDBS, 0, 4) +FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4) +FIELD(ID_AA64MMFR1, VH, 8, 4) +FIELD(ID_AA64MMFR1, HPDS, 12, 4) +FIELD(ID_AA64MMFR1, LO, 16, 4) +FIELD(ID_AA64MMFR1, PAN, 20, 4) +FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) +FIELD(ID_AA64MMFR1, XNX, 28, 4) +FIELD(ID_AA64MMFR1, TWED, 32, 4) +FIELD(ID_AA64MMFR1, ETS, 36, 4) +FIELD(ID_AA64MMFR1, HCX, 40, 4) +FIELD(ID_AA64MMFR1, AFP, 44, 4) +FIELD(ID_AA64MMFR1, NTLBPA, 48, 4) +FIELD(ID_AA64MMFR1, TIDCP1, 52, 4) +FIELD(ID_AA64MMFR1, CMOW, 56, 4) +FIELD(ID_AA64MMFR1, ECBHB, 60, 4) + +FIELD(ID_AA64MMFR2, CNP, 0, 4) +FIELD(ID_AA64MMFR2, UAO, 4, 4) +FIELD(ID_AA64MMFR2, LSM, 8, 4) +FIELD(ID_AA64MMFR2, IESB, 12, 4) +FIELD(ID_AA64MMFR2, VARANGE, 16, 4) +FIELD(ID_AA64MMFR2, CCIDX, 20, 4) +FIELD(ID_AA64MMFR2, NV, 24, 4) +FIELD(ID_AA64MMFR2, ST, 28, 4) +FIELD(ID_AA64MMFR2, AT, 32, 4) +FIELD(ID_AA64MMFR2, IDS, 36, 4) +FIELD(ID_AA64MMFR2, FWB, 40, 4) +FIELD(ID_AA64MMFR2, TTL, 48, 4) +FIELD(ID_AA64MMFR2, BBM, 52, 4) +FIELD(ID_AA64MMFR2, EVT, 56, 4) +FIELD(ID_AA64MMFR2, E0PD, 60, 4) + +FIELD(ID_AA64MMFR3, TCRX, 0, 4) +FIELD(ID_AA64MMFR3, SCTLRX, 4, 4) +FIELD(ID_AA64MMFR3, S1PIE, 8, 4) +FIELD(ID_AA64MMFR3, S2PIE, 12, 4) +FIELD(ID_AA64MMFR3, S1POE, 16, 4) +FIELD(ID_AA64MMFR3, S2POE, 20, 4) +FIELD(ID_AA64MMFR3, AIE, 24, 4) +FIELD(ID_AA64MMFR3, MEC, 28, 4) +FIELD(ID_AA64MMFR3, D128, 32, 4) +FIELD(ID_AA64MMFR3, D128_2, 36, 4) +FIELD(ID_AA64MMFR3, SNERR, 40, 4) +FIELD(ID_AA64MMFR3, ANERR, 44, 4) +FIELD(ID_AA64MMFR3, SDERR, 52, 4) +FIELD(ID_AA64MMFR3, ADERR, 56, 4) +FIELD(ID_AA64MMFR3, SPEC_FPACC, 60, 4) + +FIELD(ID_AA64DFR0, DEBUGVER, 0, 4) +FIELD(ID_AA64DFR0, TRACEVER, 4, 4) +FIELD(ID_AA64DFR0, PMUVER, 8, 4) +FIELD(ID_AA64DFR0, BRPS, 12, 4) +FIELD(ID_AA64DFR0, PMSS, 16, 4) +FIELD(ID_AA64DFR0, WRPS, 20, 4) +FIELD(ID_AA64DFR0, SEBEP, 24, 4) +FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4) +FIELD(ID_AA64DFR0, PMSVER, 32, 4) +FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4) +FIELD(ID_AA64DFR0, TRACEFILT, 40, 4) +FIELD(ID_AA64DFR0, TRACEBUFFER, 44, 4) +FIELD(ID_AA64DFR0, MTPMU, 48, 4) +FIELD(ID_AA64DFR0, BRBE, 52, 4) +FIELD(ID_AA64DFR0, EXTTRCBUFF, 56, 4) +FIELD(ID_AA64DFR0, HPMN0, 60, 4) + +FIELD(ID_AA64ZFR0, SVEVER, 0, 4) +FIELD(ID_AA64ZFR0, AES, 4, 4) +FIELD(ID_AA64ZFR0, BITPERM, 16, 4) +FIELD(ID_AA64ZFR0, BFLOAT16, 20, 4) +FIELD(ID_AA64ZFR0, B16B16, 24, 4) +FIELD(ID_AA64ZFR0, SHA3, 32, 4) +FIELD(ID_AA64ZFR0, SM4, 40, 4) +FIELD(ID_AA64ZFR0, I8MM, 44, 4) +FIELD(ID_AA64ZFR0, F32MM, 52, 4) +FIELD(ID_AA64ZFR0, F64MM, 56, 4) + +FIELD(ID_AA64SMFR0, F32F32, 32, 1) +FIELD(ID_AA64SMFR0, BI32I32, 33, 1) +FIELD(ID_AA64SMFR0, B16F32, 34, 1) +FIELD(ID_AA64SMFR0, F16F32, 35, 1) +FIELD(ID_AA64SMFR0, I8I32, 36, 4) +FIELD(ID_AA64SMFR0, F16F16, 42, 1) +FIELD(ID_AA64SMFR0, B16B16, 43, 1) +FIELD(ID_AA64SMFR0, I16I32, 44, 4) +FIELD(ID_AA64SMFR0, F64F64, 48, 1) +FIELD(ID_AA64SMFR0, I16I64, 52, 4) +FIELD(ID_AA64SMFR0, SMEVER, 56, 4) +FIELD(ID_AA64SMFR0, FA64, 63, 1) + +FIELD(ID_DFR0, COPDBG, 0, 4) +FIELD(ID_DFR0, COPSDBG, 4, 4) +FIELD(ID_DFR0, MMAPDBG, 8, 4) +FIELD(ID_DFR0, COPTRC, 12, 4) +FIELD(ID_DFR0, MMAPTRC, 16, 4) +FIELD(ID_DFR0, MPROFDBG, 20, 4) +FIELD(ID_DFR0, PERFMON, 24, 4) +FIELD(ID_DFR0, TRACEFILT, 28, 4) + +FIELD(ID_DFR1, MTPMU, 0, 4) +FIELD(ID_DFR1, HPMN0, 4, 4) + +FIELD(DBGDIDR, SE_IMP, 12, 1) +FIELD(DBGDIDR, NSUHD_IMP, 14, 1) +FIELD(DBGDIDR, VERSION, 16, 4) +FIELD(DBGDIDR, CTX_CMPS, 20, 4) +FIELD(DBGDIDR, BRPS, 24, 4) +FIELD(DBGDIDR, WRPS, 28, 4) + +FIELD(DBGDEVID, PCSAMPLE, 0, 4) +FIELD(DBGDEVID, WPADDRMASK, 4, 4) +FIELD(DBGDEVID, BPADDRMASK, 8, 4) +FIELD(DBGDEVID, VECTORCATCH, 12, 4) +FIELD(DBGDEVID, VIRTEXTNS, 16, 4) +FIELD(DBGDEVID, DOUBLELOCK, 20, 4) +FIELD(DBGDEVID, AUXREGS, 24, 4) +FIELD(DBGDEVID, CIDMASK, 28, 4) + +FIELD(DBGDEVID1, PCSROFFSET, 0, 4) + +FIELD(MVFR0, SIMDREG, 0, 4) +FIELD(MVFR0, FPSP, 4, 4) +FIELD(MVFR0, FPDP, 8, 4) +FIELD(MVFR0, FPTRAP, 12, 4) +FIELD(MVFR0, FPDIVIDE, 16, 4) +FIELD(MVFR0, FPSQRT, 20, 4) +FIELD(MVFR0, FPSHVEC, 24, 4) +FIELD(MVFR0, FPROUND, 28, 4) + +FIELD(MVFR1, FPFTZ, 0, 4) +FIELD(MVFR1, FPDNAN, 4, 4) +FIELD(MVFR1, SIMDLS, 8, 4) /* A-profile only */ +FIELD(MVFR1, SIMDINT, 12, 4) /* A-profile only */ +FIELD(MVFR1, SIMDSP, 16, 4) /* A-profile only */ +FIELD(MVFR1, SIMDHP, 20, 4) /* A-profile only */ +FIELD(MVFR1, MVE, 8, 4) /* M-profile only */ +FIELD(MVFR1, FP16, 20, 4) /* M-profile only */ +FIELD(MVFR1, FPHP, 24, 4) +FIELD(MVFR1, SIMDFMAC, 28, 4) + +FIELD(MVFR2, SIMDMISC, 0, 4) +FIELD(MVFR2, FPMISC, 4, 4) + /* * Naming convention for isar_feature functions: * Functions which test 32-bit ID registers should have _aa32_ in diff --git a/target/arm/cpu.h b/target/arm/cpu.h index d5534e35804..2b9585dc80a 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1994,416 +1994,6 @@ FIELD(V7M_VPR, P0, 0, 16) FIELD(V7M_VPR, MASK01, 16, 4) FIELD(V7M_VPR, MASK23, 20, 4) =20 -/* - * System register ID fields. - */ -FIELD(CLIDR_EL1, CTYPE1, 0, 3) -FIELD(CLIDR_EL1, CTYPE2, 3, 3) -FIELD(CLIDR_EL1, CTYPE3, 6, 3) -FIELD(CLIDR_EL1, CTYPE4, 9, 3) -FIELD(CLIDR_EL1, CTYPE5, 12, 3) -FIELD(CLIDR_EL1, CTYPE6, 15, 3) -FIELD(CLIDR_EL1, CTYPE7, 18, 3) -FIELD(CLIDR_EL1, LOUIS, 21, 3) -FIELD(CLIDR_EL1, LOC, 24, 3) -FIELD(CLIDR_EL1, LOUU, 27, 3) -FIELD(CLIDR_EL1, ICB, 30, 3) - -/* When FEAT_CCIDX is implemented */ -FIELD(CCSIDR_EL1, CCIDX_LINESIZE, 0, 3) -FIELD(CCSIDR_EL1, CCIDX_ASSOCIATIVITY, 3, 21) -FIELD(CCSIDR_EL1, CCIDX_NUMSETS, 32, 24) - -/* When FEAT_CCIDX is not implemented */ -FIELD(CCSIDR_EL1, LINESIZE, 0, 3) -FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10) -FIELD(CCSIDR_EL1, NUMSETS, 13, 15) - -FIELD(CTR_EL0, IMINLINE, 0, 4) -FIELD(CTR_EL0, L1IP, 14, 2) -FIELD(CTR_EL0, DMINLINE, 16, 4) -FIELD(CTR_EL0, ERG, 20, 4) -FIELD(CTR_EL0, CWG, 24, 4) -FIELD(CTR_EL0, IDC, 28, 1) -FIELD(CTR_EL0, DIC, 29, 1) -FIELD(CTR_EL0, TMINLINE, 32, 6) - -FIELD(MIDR_EL1, REVISION, 0, 4) -FIELD(MIDR_EL1, PARTNUM, 4, 12) -FIELD(MIDR_EL1, ARCHITECTURE, 16, 4) -FIELD(MIDR_EL1, VARIANT, 20, 4) -FIELD(MIDR_EL1, IMPLEMENTER, 24, 8) - -FIELD(ID_ISAR0, SWAP, 0, 4) -FIELD(ID_ISAR0, BITCOUNT, 4, 4) -FIELD(ID_ISAR0, BITFIELD, 8, 4) -FIELD(ID_ISAR0, CMPBRANCH, 12, 4) -FIELD(ID_ISAR0, COPROC, 16, 4) -FIELD(ID_ISAR0, DEBUG, 20, 4) -FIELD(ID_ISAR0, DIVIDE, 24, 4) - -FIELD(ID_ISAR1, ENDIAN, 0, 4) -FIELD(ID_ISAR1, EXCEPT, 4, 4) -FIELD(ID_ISAR1, EXCEPT_AR, 8, 4) -FIELD(ID_ISAR1, EXTEND, 12, 4) -FIELD(ID_ISAR1, IFTHEN, 16, 4) -FIELD(ID_ISAR1, IMMEDIATE, 20, 4) -FIELD(ID_ISAR1, INTERWORK, 24, 4) -FIELD(ID_ISAR1, JAZELLE, 28, 4) - -FIELD(ID_ISAR2, LOADSTORE, 0, 4) -FIELD(ID_ISAR2, MEMHINT, 4, 4) -FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4) -FIELD(ID_ISAR2, MULT, 12, 4) -FIELD(ID_ISAR2, MULTS, 16, 4) -FIELD(ID_ISAR2, MULTU, 20, 4) -FIELD(ID_ISAR2, PSR_AR, 24, 4) -FIELD(ID_ISAR2, REVERSAL, 28, 4) - -FIELD(ID_ISAR3, SATURATE, 0, 4) -FIELD(ID_ISAR3, SIMD, 4, 4) -FIELD(ID_ISAR3, SVC, 8, 4) -FIELD(ID_ISAR3, SYNCHPRIM, 12, 4) -FIELD(ID_ISAR3, TABBRANCH, 16, 4) -FIELD(ID_ISAR3, T32COPY, 20, 4) -FIELD(ID_ISAR3, TRUENOP, 24, 4) -FIELD(ID_ISAR3, T32EE, 28, 4) - -FIELD(ID_ISAR4, UNPRIV, 0, 4) -FIELD(ID_ISAR4, WITHSHIFTS, 4, 4) -FIELD(ID_ISAR4, WRITEBACK, 8, 4) -FIELD(ID_ISAR4, SMC, 12, 4) -FIELD(ID_ISAR4, BARRIER, 16, 4) -FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4) -FIELD(ID_ISAR4, PSR_M, 24, 4) -FIELD(ID_ISAR4, SWP_FRAC, 28, 4) - -FIELD(ID_ISAR5, SEVL, 0, 4) -FIELD(ID_ISAR5, AES, 4, 4) -FIELD(ID_ISAR5, SHA1, 8, 4) -FIELD(ID_ISAR5, SHA2, 12, 4) -FIELD(ID_ISAR5, CRC32, 16, 4) -FIELD(ID_ISAR5, RDM, 24, 4) -FIELD(ID_ISAR5, VCMA, 28, 4) - -FIELD(ID_ISAR6, JSCVT, 0, 4) -FIELD(ID_ISAR6, DP, 4, 4) -FIELD(ID_ISAR6, FHM, 8, 4) -FIELD(ID_ISAR6, SB, 12, 4) -FIELD(ID_ISAR6, SPECRES, 16, 4) -FIELD(ID_ISAR6, BF16, 20, 4) -FIELD(ID_ISAR6, I8MM, 24, 4) - -FIELD(ID_MMFR0, VMSA, 0, 4) -FIELD(ID_MMFR0, PMSA, 4, 4) -FIELD(ID_MMFR0, OUTERSHR, 8, 4) -FIELD(ID_MMFR0, SHARELVL, 12, 4) -FIELD(ID_MMFR0, TCM, 16, 4) -FIELD(ID_MMFR0, AUXREG, 20, 4) -FIELD(ID_MMFR0, FCSE, 24, 4) -FIELD(ID_MMFR0, INNERSHR, 28, 4) - -FIELD(ID_MMFR1, L1HVDVA, 0, 4) -FIELD(ID_MMFR1, L1UNIVA, 4, 4) -FIELD(ID_MMFR1, L1HVDSW, 8, 4) -FIELD(ID_MMFR1, L1UNISW, 12, 4) -FIELD(ID_MMFR1, L1HVD, 16, 4) -FIELD(ID_MMFR1, L1UNI, 20, 4) -FIELD(ID_MMFR1, L1TSTCLN, 24, 4) -FIELD(ID_MMFR1, BPRED, 28, 4) - -FIELD(ID_MMFR2, L1HVDFG, 0, 4) -FIELD(ID_MMFR2, L1HVDBG, 4, 4) -FIELD(ID_MMFR2, L1HVDRNG, 8, 4) -FIELD(ID_MMFR2, HVDTLB, 12, 4) -FIELD(ID_MMFR2, UNITLB, 16, 4) -FIELD(ID_MMFR2, MEMBARR, 20, 4) -FIELD(ID_MMFR2, WFISTALL, 24, 4) -FIELD(ID_MMFR2, HWACCFLG, 28, 4) - -FIELD(ID_MMFR3, CMAINTVA, 0, 4) -FIELD(ID_MMFR3, CMAINTSW, 4, 4) -FIELD(ID_MMFR3, BPMAINT, 8, 4) -FIELD(ID_MMFR3, MAINTBCST, 12, 4) -FIELD(ID_MMFR3, PAN, 16, 4) -FIELD(ID_MMFR3, COHWALK, 20, 4) -FIELD(ID_MMFR3, CMEMSZ, 24, 4) -FIELD(ID_MMFR3, SUPERSEC, 28, 4) - -FIELD(ID_MMFR4, SPECSEI, 0, 4) -FIELD(ID_MMFR4, AC2, 4, 4) -FIELD(ID_MMFR4, XNX, 8, 4) -FIELD(ID_MMFR4, CNP, 12, 4) -FIELD(ID_MMFR4, HPDS, 16, 4) -FIELD(ID_MMFR4, LSM, 20, 4) -FIELD(ID_MMFR4, CCIDX, 24, 4) -FIELD(ID_MMFR4, EVT, 28, 4) - -FIELD(ID_MMFR5, ETS, 0, 4) -FIELD(ID_MMFR5, NTLBPA, 4, 4) - -FIELD(ID_PFR0, STATE0, 0, 4) -FIELD(ID_PFR0, STATE1, 4, 4) -FIELD(ID_PFR0, STATE2, 8, 4) -FIELD(ID_PFR0, STATE3, 12, 4) -FIELD(ID_PFR0, CSV2, 16, 4) -FIELD(ID_PFR0, AMU, 20, 4) -FIELD(ID_PFR0, DIT, 24, 4) -FIELD(ID_PFR0, RAS, 28, 4) - -FIELD(ID_PFR1, PROGMOD, 0, 4) -FIELD(ID_PFR1, SECURITY, 4, 4) -FIELD(ID_PFR1, MPROGMOD, 8, 4) -FIELD(ID_PFR1, VIRTUALIZATION, 12, 4) -FIELD(ID_PFR1, GENTIMER, 16, 4) -FIELD(ID_PFR1, SEC_FRAC, 20, 4) -FIELD(ID_PFR1, VIRT_FRAC, 24, 4) -FIELD(ID_PFR1, GIC, 28, 4) - -FIELD(ID_PFR2, CSV3, 0, 4) -FIELD(ID_PFR2, SSBS, 4, 4) -FIELD(ID_PFR2, RAS_FRAC, 8, 4) - -FIELD(ID_AA64ISAR0, AES, 4, 4) -FIELD(ID_AA64ISAR0, SHA1, 8, 4) -FIELD(ID_AA64ISAR0, SHA2, 12, 4) -FIELD(ID_AA64ISAR0, CRC32, 16, 4) -FIELD(ID_AA64ISAR0, ATOMIC, 20, 4) -FIELD(ID_AA64ISAR0, TME, 24, 4) -FIELD(ID_AA64ISAR0, RDM, 28, 4) -FIELD(ID_AA64ISAR0, SHA3, 32, 4) -FIELD(ID_AA64ISAR0, SM3, 36, 4) -FIELD(ID_AA64ISAR0, SM4, 40, 4) -FIELD(ID_AA64ISAR0, DP, 44, 4) -FIELD(ID_AA64ISAR0, FHM, 48, 4) -FIELD(ID_AA64ISAR0, TS, 52, 4) -FIELD(ID_AA64ISAR0, TLB, 56, 4) -FIELD(ID_AA64ISAR0, RNDR, 60, 4) - -FIELD(ID_AA64ISAR1, DPB, 0, 4) -FIELD(ID_AA64ISAR1, APA, 4, 4) -FIELD(ID_AA64ISAR1, API, 8, 4) -FIELD(ID_AA64ISAR1, JSCVT, 12, 4) -FIELD(ID_AA64ISAR1, FCMA, 16, 4) -FIELD(ID_AA64ISAR1, LRCPC, 20, 4) -FIELD(ID_AA64ISAR1, GPA, 24, 4) -FIELD(ID_AA64ISAR1, GPI, 28, 4) -FIELD(ID_AA64ISAR1, FRINTTS, 32, 4) -FIELD(ID_AA64ISAR1, SB, 36, 4) -FIELD(ID_AA64ISAR1, SPECRES, 40, 4) -FIELD(ID_AA64ISAR1, BF16, 44, 4) -FIELD(ID_AA64ISAR1, DGH, 48, 4) -FIELD(ID_AA64ISAR1, I8MM, 52, 4) -FIELD(ID_AA64ISAR1, XS, 56, 4) -FIELD(ID_AA64ISAR1, LS64, 60, 4) - -FIELD(ID_AA64ISAR2, WFXT, 0, 4) -FIELD(ID_AA64ISAR2, RPRES, 4, 4) -FIELD(ID_AA64ISAR2, GPA3, 8, 4) -FIELD(ID_AA64ISAR2, APA3, 12, 4) -FIELD(ID_AA64ISAR2, MOPS, 16, 4) -FIELD(ID_AA64ISAR2, BC, 20, 4) -FIELD(ID_AA64ISAR2, PAC_FRAC, 24, 4) -FIELD(ID_AA64ISAR2, CLRBHB, 28, 4) -FIELD(ID_AA64ISAR2, SYSREG_128, 32, 4) -FIELD(ID_AA64ISAR2, SYSINSTR_128, 36, 4) -FIELD(ID_AA64ISAR2, PRFMSLC, 40, 4) -FIELD(ID_AA64ISAR2, RPRFM, 48, 4) -FIELD(ID_AA64ISAR2, CSSC, 52, 4) -FIELD(ID_AA64ISAR2, LUT, 56, 4) -FIELD(ID_AA64ISAR2, ATS1A, 60, 4) - -FIELD(ID_AA64PFR0, EL0, 0, 4) -FIELD(ID_AA64PFR0, EL1, 4, 4) -FIELD(ID_AA64PFR0, EL2, 8, 4) -FIELD(ID_AA64PFR0, EL3, 12, 4) -FIELD(ID_AA64PFR0, FP, 16, 4) -FIELD(ID_AA64PFR0, ADVSIMD, 20, 4) -FIELD(ID_AA64PFR0, GIC, 24, 4) -FIELD(ID_AA64PFR0, RAS, 28, 4) -FIELD(ID_AA64PFR0, SVE, 32, 4) -FIELD(ID_AA64PFR0, SEL2, 36, 4) -FIELD(ID_AA64PFR0, MPAM, 40, 4) -FIELD(ID_AA64PFR0, AMU, 44, 4) -FIELD(ID_AA64PFR0, DIT, 48, 4) -FIELD(ID_AA64PFR0, RME, 52, 4) -FIELD(ID_AA64PFR0, CSV2, 56, 4) -FIELD(ID_AA64PFR0, CSV3, 60, 4) - -FIELD(ID_AA64PFR1, BT, 0, 4) -FIELD(ID_AA64PFR1, SSBS, 4, 4) -FIELD(ID_AA64PFR1, MTE, 8, 4) -FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4) -FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4) -FIELD(ID_AA64PFR1, SME, 24, 4) -FIELD(ID_AA64PFR1, RNDR_TRAP, 28, 4) -FIELD(ID_AA64PFR1, CSV2_FRAC, 32, 4) -FIELD(ID_AA64PFR1, NMI, 36, 4) -FIELD(ID_AA64PFR1, MTE_FRAC, 40, 4) -FIELD(ID_AA64PFR1, GCS, 44, 4) -FIELD(ID_AA64PFR1, THE, 48, 4) -FIELD(ID_AA64PFR1, MTEX, 52, 4) -FIELD(ID_AA64PFR1, DF2, 56, 4) -FIELD(ID_AA64PFR1, PFAR, 60, 4) - -FIELD(ID_AA64MMFR0, PARANGE, 0, 4) -FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) -FIELD(ID_AA64MMFR0, BIGEND, 8, 4) -FIELD(ID_AA64MMFR0, SNSMEM, 12, 4) -FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4) -FIELD(ID_AA64MMFR0, TGRAN16, 20, 4) -FIELD(ID_AA64MMFR0, TGRAN64, 24, 4) -FIELD(ID_AA64MMFR0, TGRAN4, 28, 4) -FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4) -FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4) -FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4) -FIELD(ID_AA64MMFR0, EXS, 44, 4) -FIELD(ID_AA64MMFR0, FGT, 56, 4) -FIELD(ID_AA64MMFR0, ECV, 60, 4) - -FIELD(ID_AA64MMFR1, HAFDBS, 0, 4) -FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4) -FIELD(ID_AA64MMFR1, VH, 8, 4) -FIELD(ID_AA64MMFR1, HPDS, 12, 4) -FIELD(ID_AA64MMFR1, LO, 16, 4) -FIELD(ID_AA64MMFR1, PAN, 20, 4) -FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) -FIELD(ID_AA64MMFR1, XNX, 28, 4) -FIELD(ID_AA64MMFR1, TWED, 32, 4) -FIELD(ID_AA64MMFR1, ETS, 36, 4) -FIELD(ID_AA64MMFR1, HCX, 40, 4) -FIELD(ID_AA64MMFR1, AFP, 44, 4) -FIELD(ID_AA64MMFR1, NTLBPA, 48, 4) -FIELD(ID_AA64MMFR1, TIDCP1, 52, 4) -FIELD(ID_AA64MMFR1, CMOW, 56, 4) -FIELD(ID_AA64MMFR1, ECBHB, 60, 4) - -FIELD(ID_AA64MMFR2, CNP, 0, 4) -FIELD(ID_AA64MMFR2, UAO, 4, 4) -FIELD(ID_AA64MMFR2, LSM, 8, 4) -FIELD(ID_AA64MMFR2, IESB, 12, 4) -FIELD(ID_AA64MMFR2, VARANGE, 16, 4) -FIELD(ID_AA64MMFR2, CCIDX, 20, 4) -FIELD(ID_AA64MMFR2, NV, 24, 4) -FIELD(ID_AA64MMFR2, ST, 28, 4) -FIELD(ID_AA64MMFR2, AT, 32, 4) -FIELD(ID_AA64MMFR2, IDS, 36, 4) -FIELD(ID_AA64MMFR2, FWB, 40, 4) -FIELD(ID_AA64MMFR2, TTL, 48, 4) -FIELD(ID_AA64MMFR2, BBM, 52, 4) -FIELD(ID_AA64MMFR2, EVT, 56, 4) -FIELD(ID_AA64MMFR2, E0PD, 60, 4) - -FIELD(ID_AA64MMFR3, TCRX, 0, 4) -FIELD(ID_AA64MMFR3, SCTLRX, 4, 4) -FIELD(ID_AA64MMFR3, S1PIE, 8, 4) -FIELD(ID_AA64MMFR3, S2PIE, 12, 4) -FIELD(ID_AA64MMFR3, S1POE, 16, 4) -FIELD(ID_AA64MMFR3, S2POE, 20, 4) -FIELD(ID_AA64MMFR3, AIE, 24, 4) -FIELD(ID_AA64MMFR3, MEC, 28, 4) -FIELD(ID_AA64MMFR3, D128, 32, 4) -FIELD(ID_AA64MMFR3, D128_2, 36, 4) -FIELD(ID_AA64MMFR3, SNERR, 40, 4) -FIELD(ID_AA64MMFR3, ANERR, 44, 4) -FIELD(ID_AA64MMFR3, SDERR, 52, 4) -FIELD(ID_AA64MMFR3, ADERR, 56, 4) -FIELD(ID_AA64MMFR3, SPEC_FPACC, 60, 4) - -FIELD(ID_AA64DFR0, DEBUGVER, 0, 4) -FIELD(ID_AA64DFR0, TRACEVER, 4, 4) -FIELD(ID_AA64DFR0, PMUVER, 8, 4) -FIELD(ID_AA64DFR0, BRPS, 12, 4) -FIELD(ID_AA64DFR0, PMSS, 16, 4) -FIELD(ID_AA64DFR0, WRPS, 20, 4) -FIELD(ID_AA64DFR0, SEBEP, 24, 4) -FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4) -FIELD(ID_AA64DFR0, PMSVER, 32, 4) -FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4) -FIELD(ID_AA64DFR0, TRACEFILT, 40, 4) -FIELD(ID_AA64DFR0, TRACEBUFFER, 44, 4) -FIELD(ID_AA64DFR0, MTPMU, 48, 4) -FIELD(ID_AA64DFR0, BRBE, 52, 4) -FIELD(ID_AA64DFR0, EXTTRCBUFF, 56, 4) -FIELD(ID_AA64DFR0, HPMN0, 60, 4) - -FIELD(ID_AA64ZFR0, SVEVER, 0, 4) -FIELD(ID_AA64ZFR0, AES, 4, 4) -FIELD(ID_AA64ZFR0, BITPERM, 16, 4) -FIELD(ID_AA64ZFR0, BFLOAT16, 20, 4) -FIELD(ID_AA64ZFR0, B16B16, 24, 4) -FIELD(ID_AA64ZFR0, SHA3, 32, 4) -FIELD(ID_AA64ZFR0, SM4, 40, 4) -FIELD(ID_AA64ZFR0, I8MM, 44, 4) -FIELD(ID_AA64ZFR0, F32MM, 52, 4) -FIELD(ID_AA64ZFR0, F64MM, 56, 4) - -FIELD(ID_AA64SMFR0, F32F32, 32, 1) -FIELD(ID_AA64SMFR0, BI32I32, 33, 1) -FIELD(ID_AA64SMFR0, B16F32, 34, 1) -FIELD(ID_AA64SMFR0, F16F32, 35, 1) -FIELD(ID_AA64SMFR0, I8I32, 36, 4) -FIELD(ID_AA64SMFR0, F16F16, 42, 1) -FIELD(ID_AA64SMFR0, B16B16, 43, 1) -FIELD(ID_AA64SMFR0, I16I32, 44, 4) -FIELD(ID_AA64SMFR0, F64F64, 48, 1) -FIELD(ID_AA64SMFR0, I16I64, 52, 4) -FIELD(ID_AA64SMFR0, SMEVER, 56, 4) -FIELD(ID_AA64SMFR0, FA64, 63, 1) - -FIELD(ID_DFR0, COPDBG, 0, 4) -FIELD(ID_DFR0, COPSDBG, 4, 4) -FIELD(ID_DFR0, MMAPDBG, 8, 4) -FIELD(ID_DFR0, COPTRC, 12, 4) -FIELD(ID_DFR0, MMAPTRC, 16, 4) -FIELD(ID_DFR0, MPROFDBG, 20, 4) -FIELD(ID_DFR0, PERFMON, 24, 4) -FIELD(ID_DFR0, TRACEFILT, 28, 4) - -FIELD(ID_DFR1, MTPMU, 0, 4) -FIELD(ID_DFR1, HPMN0, 4, 4) - -FIELD(DBGDIDR, SE_IMP, 12, 1) -FIELD(DBGDIDR, NSUHD_IMP, 14, 1) -FIELD(DBGDIDR, VERSION, 16, 4) -FIELD(DBGDIDR, CTX_CMPS, 20, 4) -FIELD(DBGDIDR, BRPS, 24, 4) -FIELD(DBGDIDR, WRPS, 28, 4) - -FIELD(DBGDEVID, PCSAMPLE, 0, 4) -FIELD(DBGDEVID, WPADDRMASK, 4, 4) -FIELD(DBGDEVID, BPADDRMASK, 8, 4) -FIELD(DBGDEVID, VECTORCATCH, 12, 4) -FIELD(DBGDEVID, VIRTEXTNS, 16, 4) -FIELD(DBGDEVID, DOUBLELOCK, 20, 4) -FIELD(DBGDEVID, AUXREGS, 24, 4) -FIELD(DBGDEVID, CIDMASK, 28, 4) - -FIELD(DBGDEVID1, PCSROFFSET, 0, 4) - -FIELD(MVFR0, SIMDREG, 0, 4) -FIELD(MVFR0, FPSP, 4, 4) -FIELD(MVFR0, FPDP, 8, 4) -FIELD(MVFR0, FPTRAP, 12, 4) -FIELD(MVFR0, FPDIVIDE, 16, 4) -FIELD(MVFR0, FPSQRT, 20, 4) -FIELD(MVFR0, FPSHVEC, 24, 4) -FIELD(MVFR0, FPROUND, 28, 4) - -FIELD(MVFR1, FPFTZ, 0, 4) -FIELD(MVFR1, FPDNAN, 4, 4) -FIELD(MVFR1, SIMDLS, 8, 4) /* A-profile only */ -FIELD(MVFR1, SIMDINT, 12, 4) /* A-profile only */ -FIELD(MVFR1, SIMDSP, 16, 4) /* A-profile only */ -FIELD(MVFR1, SIMDHP, 20, 4) /* A-profile only */ -FIELD(MVFR1, MVE, 8, 4) /* M-profile only */ -FIELD(MVFR1, FP16, 20, 4) /* M-profile only */ -FIELD(MVFR1, FPHP, 24, 4) -FIELD(MVFR1, SIMDFMAC, 28, 4) - -FIELD(MVFR2, SIMDMISC, 0, 4) -FIELD(MVFR2, FPMISC, 4, 4) - FIELD(GPCCR, PPS, 0, 3) FIELD(GPCCR, IRGN, 8, 2) FIELD(GPCCR, ORGN, 10, 2) --=20 2.43.0 From nobody Sun Sep 28 15:26:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758896263; cv=none; d=zohomail.com; s=zohoarc; b=oHsnHQCsgSH3ehcqUeM1pzOV7UXtrh8b/Eyh/Ck/AVhQmn3aTb+uZi7UpAm5GDkGpnmNF9oNtESOuYT7e7jiGNCUT9U5k4mTWxgSV43MxrUcHeK1Vh8OqZNUdLfFPb9+I5BQf/XQl5XN/noXNZaLSPnuuKnrj2UMFVtRxAdUYFc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758896263; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-410f2007372sm6338315f8f.16.2025.09.26.07.09.30 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Sep 2025 07:09:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758895771; x=1759500571; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=HfRxq0U7zhd1tsQFSFudYaq3Tr4Dt63MO1uZEXfIFSY=; b=JHX+b+fj8n8FjALvOzjFpYpis9ukjkv9yfWsnVH1jih1S6L5Sp10pU7mLU9hoViJ0m XjeY2YRaD9o/8y0EubAyVcrj54D+n9IY6wZg1KT5GbVos3ZAs1H4TJMHw7SwPeKD3gR1 d0uzcgOZknC/eESJZwdesQCxLRSqR9MbiR/GprlNOKAhj+6k1S6YkCX1fXQTyAZrf9sp KOd2zCPvCOv8Kw1xePYZgPZjV6vEdGeiactHS5r8nuZDUyLKyfOOlx6g5ugQ2MTsaPyW iShPlNnpl8bPWoYozsNUbDZ+xHCia/2F0ZaURVRh/k/rrPYFTLP0vFdAGl6/PHP6QwSV sjKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758895771; x=1759500571; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HfRxq0U7zhd1tsQFSFudYaq3Tr4Dt63MO1uZEXfIFSY=; b=EvSf01Ljn/k8uojz0UdeI1PRUFTZYv8sluBbh9BFcjrivZ4OueV+QATBWQDJAJDD8V 4lin33dPp4oz1739jmn8SGyLt8KkHicYpQjAke8vkOsE2Uc+tg/ZvDqwuOg231Bi/d0M N0AJuM2taJ++FUL8XS1IzotLhxIJOSHi/PD4tZFXtOthe0nvZFTGUuE7CGpHJ+B3Rsi9 b1vc+G0C4/DfzRMnnpLsx8bLaVpMqFBLhO2sN21QRRaosZ1zyK2SvZu9MxTQ9/ByEkJh 70h36NUUuAhKQp/TN7vgyOSYhdJFzWHv9teFUL0m8IOUL9oWkzIo6qhvumfYwauAVyJ+ mcCQ== X-Gm-Message-State: AOJu0YwrS8tr7hKiLkaEdtbCrTBcLCPO4HjLLlSEKlz0NG8FclQOMdT4 8+aTjPtt4Fmeneh89WxpRspuSIlanym3V/t2E70F6UYMHLAlIKeyS1AR29YPOSl0eV2RxZjebUS Zt5ZZ X-Gm-Gg: ASbGncu1KuAOrR93ImMiKymcYnpXFTmOEnYU8h7bjh9cPUJPt/c5wbfPxkkl3wCwRu0 y32Rv2yXQWYUn2j1I4IgXJRwKAYF9piAJ58SAOTV57OUX8g0PtR+8mmQgb0GQo99UJ73rcPo8bQ Vp6/u/4aujQAldwO/nxToqn/9huILPn+TT9raBTYzrbN8mlNRTc6ZqZep2y60E8B0CNB5vyhAxD CaMYTK2OyP5jOyMkoAYFmdcKCXTpkoCRYrQyU2k1EK47deRNTOKPs0K/4Al/GUtMwGY5lFL4ymU wfBrcW8sthy/u6ITFlNscMmRSbNBX+cTgCWxdxUNuTOT1nLp3U1QTcmi+hwIomgWcbMlynRY79m nlBkCuTXJwYcJqXc3b17JeOc1OHgXGKFSpg7Q1P4= X-Google-Smtp-Source: AGHT+IFwxfofrZt1N9GKvBzoTJ2s3VeIA3llPtjGzHCbHdKspqNzi5lU4j7iDS94h0RBGOC+Xq5byg== X-Received: by 2002:a5d:5f52:0:b0:3ee:b126:6b6 with SMTP id ffacd0b85a97d-40e4886df41mr6361997f8f.34.1758895771073; Fri, 26 Sep 2025 07:09:31 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 44/44] target/arm: Implement ID_AA64PFR2_EL1 Date: Fri, 26 Sep 2025 15:08:44 +0100 Message-ID: <20250926140844.1493020-45-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250926140844.1493020-1-peter.maydell@linaro.org> References: <20250926140844.1493020-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758896264999116600 Currently we define the ID_AA64PFR2_EL1 encoding as reserved (with the required RAZ behaviour for unassigned system registers in the ID register encoding space). Newer architecture versions start to define fields in this ID register, so define the appropriate constants and implement it as an ID register backed by a field in cpu->isar. Since none of our CPUs set that isar field to non-zero, there is no behavioural change here (other than the name exposed to the user via the gdbstub), but this paves the way for implementing the new features that use fields in this register. The fields here are the ones documented in rev L.b of the Arm ARM. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/cpu-features.h | 5 +++++ target/arm/cpu-sysregs.h.inc | 1 + target/arm/helper.c | 6 ++++-- target/arm/hvf/hvf.c | 1 + target/arm/kvm.c | 1 + target/arm/hvf/sysreg.c.inc | 1 + 6 files changed, 13 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index ad571e2ffee..602f6a88e53 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -277,6 +277,11 @@ FIELD(ID_AA64PFR1, MTEX, 52, 4) FIELD(ID_AA64PFR1, DF2, 56, 4) FIELD(ID_AA64PFR1, PFAR, 60, 4) =20 +FIELD(ID_AA64PFR2, MTEPERM, 0, 4) +FIELD(ID_AA64PFR2, MTESTOREONLY, 4, 4) +FIELD(ID_AA64PFR2, MTEFAR, 8, 4) +FIELD(ID_AA64PFR2, FPMR, 32, 4) + FIELD(ID_AA64MMFR0, PARANGE, 0, 4) FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) FIELD(ID_AA64MMFR0, BIGEND, 8, 4) diff --git a/target/arm/cpu-sysregs.h.inc b/target/arm/cpu-sysregs.h.inc index f48a9daa7c1..2bb2861c623 100644 --- a/target/arm/cpu-sysregs.h.inc +++ b/target/arm/cpu-sysregs.h.inc @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ DEF(ID_AA64PFR0_EL1, 3, 0, 0, 4, 0) DEF(ID_AA64PFR1_EL1, 3, 0, 0, 4, 1) +DEF(ID_AA64PFR2_EL1, 3, 0, 0, 4, 2) DEF(ID_AA64SMFR0_EL1, 3, 0, 0, 4, 5) DEF(ID_AA64DFR0_EL1, 3, 0, 0, 5, 0) DEF(ID_AA64DFR1_EL1, 3, 0, 0, 5, 1) diff --git a/target/arm/helper.c b/target/arm/helper.c index a18d920ac18..aa730addf2f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6109,11 +6109,11 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, .resetvalue =3D GET_IDREG(isar, ID_AA64PFR1)}, - { .name =3D "ID_AA64PFR2_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, + { .name =3D "ID_AA64PFR2_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 2, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, - .resetvalue =3D 0 }, + .resetvalue =3D GET_IDREG(isar, ID_AA64PFR2)}, { .name =3D "ID_AA64PFR3_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 3, .access =3D PL1_R, .type =3D ARM_CP_CONST, @@ -6341,6 +6341,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) R_ID_AA64PFR1_SSBS_MASK | R_ID_AA64PFR1_MTE_MASK | R_ID_AA64PFR1_SME_MASK }, + { .name =3D "ID_AA64PFR2_EL1", + .exported_bits =3D 0 }, { .name =3D "ID_AA64PFR*_EL1_RESERVED", .is_glob =3D true }, { .name =3D "ID_AA64ZFR0_EL1", diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 8b467b36638..0658a99a2d1 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -744,6 +744,7 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFea= tures *ahcf) } regs[] =3D { { HV_SYS_REG_ID_AA64PFR0_EL1, &host_isar.idregs[ID_AA64PFR0_EL1_ID= X] }, { HV_SYS_REG_ID_AA64PFR1_EL1, &host_isar.idregs[ID_AA64PFR1_EL1_ID= X] }, + /* Add ID_AA64PFR2_EL1 here when HVF supports it */ { HV_SYS_REG_ID_AA64DFR0_EL1, &host_isar.idregs[ID_AA64DFR0_EL1_ID= X] }, { HV_SYS_REG_ID_AA64DFR1_EL1, &host_isar.idregs[ID_AA64DFR1_EL1_ID= X] }, { HV_SYS_REG_ID_AA64ISAR0_EL1, &host_isar.idregs[ID_AA64ISAR0_EL1_= IDX] }, diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 5a75ff59271..b8a1c071f57 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -324,6 +324,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFea= tures *ahcf) err =3D 0; } else { err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64PFR1_EL1_IDX); + err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64PFR2_EL1_IDX); err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64SMFR0_EL1_IDX); err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64DFR0_EL1_IDX); err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64DFR1_EL1_IDX); diff --git a/target/arm/hvf/sysreg.c.inc b/target/arm/hvf/sysreg.c.inc index f2276d534e6..067a8603fa7 100644 --- a/target/arm/hvf/sysreg.c.inc +++ b/target/arm/hvf/sysreg.c.inc @@ -92,6 +92,7 @@ DEF_SYSREG(HV_SYS_REG_ID_AA64PFR0_EL1, 3, 0, 0, 4, 0) #endif =20 DEF_SYSREG(HV_SYS_REG_ID_AA64PFR1_EL1, 3, 0, 0, 4, 1) +/* Add ID_AA64PFR2_EL1 here when HVF supports it */ DEF_SYSREG(HV_SYS_REG_ID_AA64DFR0_EL1, 3, 0, 0, 5, 0) DEF_SYSREG(HV_SYS_REG_ID_AA64DFR1_EL1, 3, 0, 0, 5, 1) DEF_SYSREG(HV_SYS_REG_ID_AA64ISAR0_EL1, 3, 0, 0, 6, 0) --=20 2.43.0