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Fri, 26 Sep 2025 06:17:54 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: Pierrick Bouvier , Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs) Subject: [PULL 07/24] target/riscv/common-semi-target: remove sizeof(target_ulong) Date: Fri, 26 Sep 2025 14:17:26 +0100 Message-ID: <20250926131744.432185-8-alex.bennee@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20250926131744.432185-1-alex.bennee@linaro.org> References: <20250926131744.432185-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758892772679116600 From: Pierrick Bouvier Only riscv64 extends SYS_EXIT, similar to aarch64. Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Message-ID: <20250822150058.18692-6-pierrick.bouvier@linaro.org> Signed-off-by: Alex Benn=C3=A9e Message-ID: <20250922093711.2768983-9-alex.bennee@linaro.org> diff --git a/target/riscv/common-semi-target.h b/target/riscv/common-semi-t= arget.h index ba40e794dcc..7e6ea8da02c 100644 --- a/target/riscv/common-semi-target.h +++ b/target/riscv/common-semi-target.h @@ -25,14 +25,14 @@ static inline void common_semi_set_ret(CPUState *cs, ta= rget_ulong ret) env->gpr[xA0] =3D ret; } =20 -static inline bool common_semi_sys_exit_is_extended(CPUState *cs) +static inline bool is_64bit_semihosting(CPUArchState *env) { - return sizeof(target_ulong) =3D=3D 8; + return riscv_cpu_mxl(env) !=3D MXL_RV32; } =20 -static inline bool is_64bit_semihosting(CPUArchState *env) +static inline bool common_semi_sys_exit_is_extended(CPUState *cs) { - return riscv_cpu_mxl(env) !=3D MXL_RV32; + return is_64bit_semihosting(cpu_env(cs)); } =20 static inline target_ulong common_semi_stack_bottom(CPUState *cs) --=20 2.47.3