From nobody Sun Sep 28 15:58:45 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 175887582501422.943673033178584; Fri, 26 Sep 2025 01:37:05 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v23eR-0007pw-Gm; Fri, 26 Sep 2025 04:17:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v23eM-0007mb-Uh; Fri, 26 Sep 2025 04:17:55 -0400 Received: from isrv.corpit.ru ([212.248.84.144]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v23eD-00021D-M3; Fri, 26 Sep 2025 04:17:53 -0400 Received: from tsrv.corpit.ru (tsrv.tls.msk.ru [192.168.177.2]) by isrv.corpit.ru (Postfix) with ESMTP id CB0F0157D79; Fri, 26 Sep 2025 11:10:34 +0300 (MSK) Received: from think4mjt.origo (mjtthink.wg.tls.msk.ru [192.168.177.146]) by tsrv.corpit.ru (Postfix) with ESMTP id DDD35290C5D; Fri, 26 Sep 2025 11:10:35 +0300 (MSK) From: Michael Tokarev To: qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, Richard Henderson , Mark Cave-Ayland , Michael Tokarev Subject: [Stable-10.1.1 49/60] target/sparc: Loosen decode of RDY for v7 Date: Fri, 26 Sep 2025 11:10:17 +0300 Message-ID: <20250926081031.2214971-49-mjt@tls.msk.ru> X-Mailer: git-send-email 2.47.3 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=212.248.84.144; envelope-from=mjt@tls.msk.ru; helo=isrv.corpit.ru X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1758875826153116600 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Bits [18:0] are not decoded with v7, and for v8 unused values of rs1 simply produce undefined results. Fixes: af25071c1d ("target/sparc: Move RDASR, STBAR, MEMBAR to decodetree") Signed-off-by: Richard Henderson Reviewed-by: Mark Cave-Ayland Tested-by: Mark Cave-Ayland (cherry picked from commit 49d669ccf33a772e3baf3fe4ebb996dc015f46c1) Signed-off-by: Michael Tokarev diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 1b1b85e9c2..74848996ae 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -91,6 +91,7 @@ CALL 01 i:s30 STBAR_v9 10 00000 101000 01111 0 0000000000000 MEMBAR 10 00000 101000 01111 1 000000 cmask:3 mmask:4 =20 + RDY_v9 10 rd:5 101000 00000 0 0000000000000 RDCCR 10 rd:5 101000 00010 0 0000000000000 RDASI 10 rd:5 101000 00011 0 0000000000000 RDTICK 10 rd:5 101000 00100 0 0000000000000 @@ -118,8 +119,15 @@ CALL 01 i:s30 # This confirms that bit 13 is ignored, as 0x8143c000 is STBAR. STBAR_v8 10 ----- 101000 01111 - ------------- =20 - # Before v8, all rs1 accepted; otherwise rs1=3D=3D0. - RDY 10 rd:5 101000 rs1:5 0 0000000000000 + # For v7, bits [18:0] are ignored. + # For v8, bits [18:14], aka rs1, are repurposed and rs1 =3D 0 is RDY, + # and other values are RDASR. However, the v8 manual explicitly + # says that rs1 in 1..14 yield undefined results and do not cause + # an illegal instruction trap, and rs1 in 16..31 are available for + # implementation specific usage. + # Implement not causing an illegal instruction trap for v8 by + # continuing to interpret unused values per v7, i.e. as RDY. + RDY_v7 10 rd:5 101000 ----- - ------------- } =20 { diff --git a/target/sparc/translate.c b/target/sparc/translate.c index ece393fffc..cfdd9c1ce4 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -2863,18 +2863,8 @@ static TCGv do_rdy(DisasContext *dc, TCGv dst) return cpu_y; } =20 -static bool trans_RDY(DisasContext *dc, arg_RDY *a) -{ - /* - * TODO: Need a feature bit for sparcv8. In the meantime, treat all - * 32-bit cpus like sparcv7, which ignores the rs1 field. - * This matches after all other ASR, so Leon3 Asr17 is handled first. - */ - if (avail_64(dc) && a->rs1 !=3D 0) { - return false; - } - return do_rd_special(dc, true, a->rd, do_rdy); -} +TRANS(RDY_v7, 32, do_rd_special, true, a->rd, do_rdy) +TRANS(RDY_v9, 64, do_rd_special, true, a->rd, do_rdy) =20 static TCGv do_rd_leon3_config(DisasContext *dc, TCGv dst) { --=20 2.47.3