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Iglesias" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , "Frederic Konrad" , Sai Pavan Boddu Subject: [PATCH v6 39/47] target/arm/tcg/cpu64: add the cortex-a78ae CPU Date: Fri, 26 Sep 2025 09:07:57 +0200 Message-ID: <20250926070806.292065-40-luc.michel@amd.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250926070806.292065-1-luc.michel@amd.com> References: <20250926070806.292065-1-luc.michel@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF00003446:EE_|MN2PR12MB4205:EE_ X-MS-Office365-Filtering-Correlation-Id: ca4b9b92-44a1-4eb8-009b-08ddfccba444 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|376014|82310400026|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?J2XgKLjx9upVrf9QGs0xHSNa0RWQDOkLV8vTPg4g+ZbK1kw5cl941hsp+mux?= =?us-ascii?Q?FdCXP0Y6YgcRP7qvagxnra7Jw7PEtRdjv4LneaUAOqNjhACReECB5NfUs7+E?= =?us-ascii?Q?fllNGHZ/BnE7LYtZCFbnrBHZbelhJPjqSWLV5OkGcku2Y7rJfzB2pLgrUGbv?= =?us-ascii?Q?vaHk1jTjy+slhHFDo/hB2qJEwfZhzDjxC6amJfbFSBMx7hovGFnSugeY4IRe?= =?us-ascii?Q?dwPA4oeDurFrXelPhL/0xvj1pZtU0nHR0W6zgwacpi1t+WutkPAbAJuU/O9e?= =?us-ascii?Q?TQwpJkoK1nq0N4695WmYDXcELYgJBTzDKryc4lGvlJVvn5n0jvolWH+XSyF7?= =?us-ascii?Q?ZFrUPyoz4dD1Tn/XC4Vm1Pj28VLljzLJN5ZCVJUMJVVXhPnFKJS0q8IRt1om?= =?us-ascii?Q?5JBc870Z70aQfOTapoobk3V7hdhBVEzJaEcdGx8eEz4pmVkL6rz1CO9SWzXN?= =?us-ascii?Q?4RVBjWODvNCM7g0mDMKgio0OOswA79dr8gZ83H+YHGa4ViA4eb3pMckUmRdb?= =?us-ascii?Q?1S8CEqlqFuT9L+KBT6O+ll/eX+0+BCuLyqwCgpQfXxtGa7CHOYSQ+C4bVOU7?= =?us-ascii?Q?S/a6eZAUjC3y62wkCZMPt4y1kKvvrsYJln5UPsPdPh0qeW+uI1L71k6B6kwZ?= =?us-ascii?Q?VwPpYzLYakrRRQy8c71rBwm0NkQLUNgw5WfzhEEB0ygdPoio8kKlfICDG9Sf?= =?us-ascii?Q?y9/ne58tjY1E59h48NQRXdx4XMzz2tXm0u7tr9BJkW2z+kQJIHF+HMjWHFrn?= =?us-ascii?Q?W70jXmjrLOGGLvB3K9wfwPMFT9ZfTnea47nHvMBtRL919DKUbxrSb/UABGyO?= =?us-ascii?Q?ElGLRQ5RT+Ip6Kb0fr+A3lRI2c5rj+WIhsEIURpATlYeOVUux+oAtrcXR+6R?= =?us-ascii?Q?FUKOnk2UtcBgW27UBSSjXjEF7an6qJS7L2IswUY6ZXO/cECzmuMBqQQri1fa?= =?us-ascii?Q?G7KTG4hajuE1JlFeb1TjfM+Y3JGpD+mGxwhtLUsw8++Qdkl3Y/aiiNeuIeO7?= =?us-ascii?Q?Yj4nWkNzY2MnVZo+BwSQ8nXi9b4HCoWjp+cCpcyb5UmYp8lqTm1tXazegwrL?= =?us-ascii?Q?PNifdE/Q/vA+ZsMbb+jofLaK5cAy0WwFOThh4Wzpfl/a0lYKajGOkjEs4chH?= =?us-ascii?Q?JEVFbhvjyj1U4LvMaxViaNa7IFT2YLKqOC6ATTTnZZVLr2Lx5YRupI5Urrcu?= =?us-ascii?Q?6WVnJKxeaE3uly9E5yhv+EIjYAz6ctbHX4QfpANtJK4tFWFKol+usy/6yvn4?= =?us-ascii?Q?zPyC0DEprSAjPOHSE+Y31SM8Or6MYOTIDd+86OL+peR23O63DoGJOWt4WWQi?= =?us-ascii?Q?vU1BLwqSoeLcYHut7OSf/Txk5ug/th4lsWR4C7+XED+Sg1gTV/GbzjZjZaiJ?= =?us-ascii?Q?eY2yKzSRlqCWfNkc22Db4RBBHDRjs27vYPqHhjJ61Uw3f4Ef4fob52WoTtSt?= =?us-ascii?Q?iBIZ5Stj2LPfq8Tk31xearINhXiQtbdRKChpozwd2rJgGDlwaHm4XNOjYx5r?= =?us-ascii?Q?y7kbtIVqyunmiY9L4pY4sxgQHVT+cOxOH9pvHIPc4ajSXLtJPKIkn0WgFR6D?= =?us-ascii?Q?eJ9yeP16TNBvXiygVds=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:satlexmb08.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(1800799024)(376014)(82310400026)(36860700013); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Sep 2025 07:09:32.0154 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ca4b9b92-44a1-4eb8-009b-08ddfccba444 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF00003446.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4205 Received-SPF: permerror client-ip=2a01:111:f403:c111::9; envelope-from=Luc.Michel@amd.com; helo=DM5PR21CU001.outbound.protection.outlook.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1758870935508116600 Content-Type: text/plain; charset="utf-8" Add support for the ARM Cortex-A78AE CPU. Signed-off-by: Luc Michel Reviewed-by: Edgar E. Iglesias Reviewed-by: Peter Maydell --- target/arm/tcg/cpu64.c | 78 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 78 insertions(+) diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index abef6a246e8..90b6c0ebb0e 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -404,10 +404,83 @@ static void aarch64_a76_initfn(Object *obj) =20 /* From D5.1 AArch64 PMU register summary */ cpu->isar.reset_pmcr_el0 =3D 0x410b3000; } =20 +static void aarch64_a78ae_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; + + cpu->dtb_compatible =3D "arm,cortex-a78ae"; + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_AARCH64); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); + + /* Ordered by 3.2.4 AArch64 registers by functional group */ + SET_IDREG(isar, CLIDR, 0x82000023); + cpu->ctr =3D 0x9444c004; + cpu->dcz_blocksize =3D 4; + SET_IDREG(isar, ID_AA64DFR0, 0x0000000110305408ull); + SET_IDREG(isar, ID_AA64ISAR0, 0x0010100010211120ull); + SET_IDREG(isar, ID_AA64ISAR1, 0x0000000001200031ull); + SET_IDREG(isar, ID_AA64MMFR0, 0x0000000000101125ull); + SET_IDREG(isar, ID_AA64MMFR1, 0x0000000010212122ull); + SET_IDREG(isar, ID_AA64MMFR2, 0x0000000100001011ull); + SET_IDREG(isar, ID_AA64PFR0, 0x1100000010111112ull); /* GIC filled in = later */ + SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000010ull); + SET_IDREG(isar, ID_AFR0, 0x00000000); + SET_IDREG(isar, ID_DFR0, 0x04010088); + SET_IDREG(isar, ID_ISAR0, 0x02101110); + SET_IDREG(isar, ID_ISAR1, 0x13112111); + SET_IDREG(isar, ID_ISAR2, 0x21232042); + SET_IDREG(isar, ID_ISAR3, 0x01112131); + SET_IDREG(isar, ID_ISAR4, 0x00010142); + SET_IDREG(isar, ID_ISAR5, 0x01011121); + SET_IDREG(isar, ID_ISAR6, 0x00000010); + SET_IDREG(isar, ID_MMFR0, 0x10201105); + SET_IDREG(isar, ID_MMFR1, 0x40000000); + SET_IDREG(isar, ID_MMFR2, 0x01260000); + SET_IDREG(isar, ID_MMFR3, 0x02122211); + SET_IDREG(isar, ID_MMFR4, 0x00021110); + SET_IDREG(isar, ID_PFR0, 0x10010131); + SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */ + SET_IDREG(isar, ID_PFR2, 0x00000011); + cpu->midr =3D 0x410fd423; /* r0p3 */ + cpu->revidr =3D 0; + + /* From 3.2.33 CCSIDR_EL1 */ + /* 64KB L1 dcache */ + cpu->ccsidr[0] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, = 7); + /* 64KB L1 icache */ + cpu->ccsidr[1] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, = 2); + /* 512KB L2 cache */ + cpu->ccsidr[2] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 8, 64, 512 * KiB,= 7); + + /* From 3.2.118 SCTLR_EL3 */ + cpu->reset_sctlr =3D 0x30c50838; + + /* From 3.4.23 ICH_VTR_EL2 */ + cpu->gic_num_lrs =3D 4; + cpu->gic_vpribits =3D 5; + cpu->gic_vprebits =3D 5; + /* From 3.4.8 ICC_CTLR_EL3 */ + cpu->gic_pribits =3D 5; + + /* From 3.5.1 AdvSIMD AArch64 register summary */ + cpu->isar.mvfr0 =3D 0x10110222; + cpu->isar.mvfr1 =3D 0x13211111; + cpu->isar.mvfr2 =3D 0x00000043; + + /* From 5.5.1 AArch64 PMU register summary */ + cpu->isar.reset_pmcr_el0 =3D 0x41223000; +} + static void aarch64_a64fx_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); ARMISARegisters *isar =3D &cpu->isar; =20 @@ -1319,10 +1392,15 @@ void aarch64_max_tcg_initfn(Object *obj) static const ARMCPUInfo aarch64_cpus[] =3D { { .name =3D "cortex-a35", .initfn =3D aarch64_a35_initfn }, { .name =3D "cortex-a55", .initfn =3D aarch64_a55_initfn }, { .name =3D "cortex-a72", .initfn =3D aarch64_a72_initfn }, { .name =3D "cortex-a76", .initfn =3D aarch64_a76_initfn }, + /* + * The Cortex-A78AE differs slightly from the plain Cortex-A78. We don= 't + * currently model the latter. + */ + { .name =3D "cortex-a78ae", .initfn =3D aarch64_a78ae_initfn }, { .name =3D "cortex-a710", .initfn =3D aarch64_a710_initfn }, { .name =3D "a64fx", .initfn =3D aarch64_a64fx_initfn }, { .name =3D "neoverse-n1", .initfn =3D aarch64_neoverse_n1_init= fn }, { .name =3D "neoverse-v1", .initfn =3D aarch64_neoverse_v1_init= fn }, { .name =3D "neoverse-n2", .initfn =3D aarch64_neoverse_n2_init= fn }, --=20 2.51.0