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Iglesias" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , "Frederic Konrad" , Sai Pavan Boddu Subject: [PATCH v6 24/47] hw/arm/xlnx-versal: add support for multiple GICs Date: Fri, 26 Sep 2025 09:07:42 +0200 Message-ID: <20250926070806.292065-25-luc.michel@amd.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250926070806.292065-1-luc.michel@amd.com> References: <20250926070806.292065-1-luc.michel@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: None (SATLEXMB04.amd.com: luc.michel@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002BA51:EE_|CY8PR12MB7340:EE_ X-MS-Office365-Filtering-Correlation-Id: e944ceba-6b00-4907-4ca5-08ddfccb9879 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700013|376014|1800799024|82310400026|30052699003; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?7FWX0e+L7yRictyW1VfrH3JTvfo6HrIFkQAUqZ6TRLEhlVObd5Cou90w9oxB?= =?us-ascii?Q?VDL6t0i/NU62SJr0vWVv8ga+xWyDHHIfVyt17qA/wmjqyhe/RRIj11aIgucC?= =?us-ascii?Q?dNmMNWKvkrQRiIEv47q/PLwnBxl2j7IemJjgGJH8GL6lZEia1sEzhq5lI8iO?= =?us-ascii?Q?uxWgmDuIhFCu5Gr30LNqpygAKisBf6rJ8OoC9fTltFrxo6cN5QG6LFY8mGUM?= =?us-ascii?Q?LuxL4MsabXfZRLqVgcfGAiwC2wQVNcyJu6wwGtddYkNst8SOYzSIO3h63h7h?= =?us-ascii?Q?P8ZedKw1U2mJgcVI3J1tv0cKdhI+YZJAK8V4BFqQ/of1wz4LIFYa0wSQ83bA?= =?us-ascii?Q?j5iM3gdW/VRJrlFP53WTXsaiJSyZbOfgkMRm2VZHsYBkIWxId4G84pyZdKV4?= =?us-ascii?Q?/BHSwmeXDO8qWNfhxZ/LEJc0y8se8QaILfuu8VoS83NhBtstzg5TNa2co2kc?= =?us-ascii?Q?A42f3R371vNU3N9CcbWqpL4cUc7pG2TfmoerNBv6jO/NnQd1j4VYA3i2aJP8?= =?us-ascii?Q?iS1ioHaTVd2aHulcTHTNkSlYjLinG+hMgWnRJcSCY+GQJSocY5P0zy9S3NUX?= =?us-ascii?Q?m/zFVJmC458jy1ct5SWKO2kbQTJk3EjpUuY5dc+OBK75Ivjsoa9WxkcVRuAX?= =?us-ascii?Q?+XjHWiKNr+ZeRCJHFvf+abpy/nB/6wEJ+22e/NmZjizpXLGiRRExQsdw44jh?= =?us-ascii?Q?gcwHcvC59Q/qQZZY9/fZKCkCSYBidpsg/1EorEqM5Tl0CB57zHDYGwGhf/Xl?= =?us-ascii?Q?8W4O3anryMqGkDjRgmrwEA1D6T+7i6Zsy8KSaik2tiiOVPG2CEpUfcaWnTYz?= =?us-ascii?Q?4fP7z8m0AfMHW9gvkbz1Rl8IaTFsa1CF4HWgjQVBdhNr078gx9pbwzsopdCJ?= =?us-ascii?Q?aDeiLRRp085NfFvl/jfWNz+2Y4CtkcCB3WHw0CdjzjAGa0vICFhq9ydmx1P/?= =?us-ascii?Q?wXxPIbq4c0sFLQJ137yO8/oVME+wVbAuDVpZMOaI9//XewYcSjN8Pzy/yPpy?= =?us-ascii?Q?isgEzoaJLTsT/lDmw0c//hG1sCtpgW0ewnO7v9Yd094++dBvHxwSsP71kxQQ?= =?us-ascii?Q?SBVm07Ui7sRqA95l4Lm9I6fa9xXAg6Jkp3VdadMd4yV8Ix2XSEkBiNkmuCo3?= =?us-ascii?Q?c+5e11vBasOevixYeggU+NBDLvFcEe8Rh9bMkNU+8DkVDPYuVSwBuLO/yERR?= =?us-ascii?Q?fMtp5GgbNuHyjku8pNr+A4Dtibl9g5P9SaiuPUyQhz0KXkFuirwua3gWQfHn?= =?us-ascii?Q?1fKkYAShq6OOwvaxOF9/C7EeWFQPxKHNga9Jx26eeJ2qTijvMBzY0VZaEqUI?= =?us-ascii?Q?/6BOlt476dT+aTLr8iCkvXgT4FiT5GtXb4RgpyFyxomVsejQc2+rD2RoZK91?= =?us-ascii?Q?89LpfkC4VxZ2Lis8K64nbK/i82fp56kFf5JQ/dx74tEFa6/nbP9rj/PPnhsF?= =?us-ascii?Q?fqpgo5Ef7nRZfsFqOWSnVm0Z0XvEuKykhT6g68ZrCLEZ0StyCNVXY3wBCLtI?= =?us-ascii?Q?C4zCEZ9PHWeqOHtCMl9JgKhkIMkrrhFI/aATJCPZGIn6fq1FgBp8/ct70d07?= =?us-ascii?Q?gcpK/4XWjn/Y4L09W5k=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:satlexmb07.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(36860700013)(376014)(1800799024)(82310400026)(30052699003); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Sep 2025 07:09:12.2393 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e944ceba-6b00-4907-4ca5-08ddfccb9879 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002BA51.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7340 Received-SPF: permerror client-ip=2a01:111:f403:c001::2; envelope-from=Luc.Michel@amd.com; helo=SJ2PR03CU001.outbound.protection.outlook.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, SPF_HELO_PASS=-0.001, T_SPF_TEMPERROR=0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1758870854776116600 Content-Type: text/plain; charset="utf-8" The Versal SoC contains two GICs: one GICv3 in the APU and one GICv2 in the RPU (currently not instantiated). To prepare for the GICv2 instantiation, add support for multiple GICs when connecting interrupts. When a GIC is created, the first-cpu-index property is set on it, and a pointer to the GIC is stored in the intc array. When connecting an IRQ, a TYPE_SPLIT_IRQ device is created with its num-lines property set to the number of GICs in the SoC. The split device is used to fan out the IRQ to all the GICs. Signed-off-by: Luc Michel Reviewed-by: Francisco Iglesias Reviewed-by: Edgar E. Iglesias --- include/hw/arm/xlnx-versal.h | 1 + hw/arm/xlnx-versal.c | 56 +++++++++++++++++++++++++++++++++--- 2 files changed, 53 insertions(+), 4 deletions(-) diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h index 9d9ccfb0014..984f9f2ccdd 100644 --- a/include/hw/arm/xlnx-versal.h +++ b/include/hw/arm/xlnx-versal.h @@ -40,10 +40,11 @@ OBJECT_DECLARE_TYPE(Versal, VersalClass, XLNX_VERSAL_BA= SE) struct Versal { /*< private >*/ SysBusDevice parent_obj; =20 /*< public >*/ + GArray *intc; MemoryRegion mr_ps; =20 struct { /* 4 ranges to access DDR. */ MemoryRegion mr_ddr_ranges[4]; diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c index e03411bc212..9256eceffc7 100644 --- a/hw/arm/xlnx-versal.c +++ b/hw/arm/xlnx-versal.c @@ -43,10 +43,11 @@ #include "hw/misc/xlnx-versal-cframe-reg.h" #include "hw/or-irq.h" #include "hw/misc/xlnx-versal-crl.h" #include "hw/intc/arm_gicv3_common.h" #include "hw/intc/arm_gicv3_its_common.h" +#include "hw/core/split-irq.h" =20 #define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72") #define XLNX_VERSAL_RCPU_TYPE ARM_CPU_TYPE_NAME("cortex-r5f") #define GEM_REVISION 0x40070106 =20 @@ -315,10 +316,47 @@ static inline Object *versal_get_child_idx(Versal *s,= const char *child, g_autofree char *n =3D g_strdup_printf("%s[%zu]", child, idx); =20 return versal_get_child(s, n); } =20 +/* + * The SoC embeds multiple GICs. They all receives the same IRQ lines at t= he + * same index. This function creates a TYPE_SPLIT_IRQ device to fan out the + * given IRQ input to all the GICs. + * + * The TYPE_SPLIT_IRQ devices lie in the /soc/irq-splits QOM container + */ +static qemu_irq versal_get_gic_irq(Versal *s, int irq_idx) +{ + DeviceState *split; + Object *container =3D versal_get_child(s, "irq-splits"); + int idx =3D FIELD_EX32(irq_idx, VERSAL_IRQ, IRQ); + g_autofree char *name =3D g_strdup_printf("irq[%d]", idx); + + split =3D DEVICE(object_resolve_path_at(container, name)); + + if (split =3D=3D NULL) { + size_t i; + + split =3D qdev_new(TYPE_SPLIT_IRQ); + qdev_prop_set_uint16(split, "num-lines", s->intc->len); + object_property_add_child(container, name, OBJECT(split)); + qdev_realize_and_unref(split, NULL, &error_abort); + + for (i =3D 0; i < s->intc->len; i++) { + DeviceState *gic; + + gic =3D g_array_index(s->intc, DeviceState *, i); + qdev_connect_gpio_out(split, i, qdev_get_gpio_in(gic, idx)); + } + } else { + g_assert(FIELD_EX32(irq_idx, VERSAL_IRQ, ORED)); + } + + return qdev_get_gpio_in(split, 0); +} + /* * When the R_VERSAL_IRQ_ORED flag is set on an IRQ descriptor, this funct= ion is * used to return the corresponding or gate input IRQ. The or gate is crea= ted if * not already existant. * @@ -351,16 +389,14 @@ static qemu_irq versal_get_irq_or_gate_in(Versal *s, = int irq_idx, =20 static qemu_irq versal_get_irq(Versal *s, int irq_idx) { qemu_irq irq; bool ored; - DeviceState *gic; =20 ored =3D FIELD_EX32(irq_idx, VERSAL_IRQ, ORED); =20 - gic =3D DEVICE(versal_get_child_idx(s, "apu-gic", 0)); - irq =3D qdev_get_gpio_in(gic, FIELD_EX32(irq_idx, VERSAL_IRQ, IRQ)); + irq =3D versal_get_gic_irq(s, irq_idx); =20 if (ored) { irq =3D versal_get_irq_or_gate_in(s, irq_idx, irq); } =20 @@ -499,10 +535,11 @@ static void versal_create_gic_its(Versal *s, } =20 static DeviceState *versal_create_gic(Versal *s, const VersalCpuClusterMap *map, MemoryRegion *mr, + int first_cpu_idx, size_t num_cpu) { DeviceState *dev; SysBusDevice *sbd; QList *redist_region_count; @@ -523,10 +560,11 @@ static DeviceState *versal_create_gic(Versal *s, qdev_prop_set_array(dev, "redist-region-count", redist_region_count); =20 qdev_prop_set_bit(dev, "has-security-extensions", true); qdev_prop_set_bit(dev, "has-lpi", map->gic.has_its); object_property_set_link(OBJECT(dev), "sysmem", OBJECT(mr), &error_abo= rt); + qdev_prop_set_uint32(dev, "first-cpu-index", first_cpu_idx); =20 sysbus_realize_and_unref(sbd, &error_fatal); =20 memory_region_add_subregion(mr, map->gic.dist, sysbus_mmio_get_region(sbd, 0)); @@ -549,10 +587,12 @@ static DeviceState *versal_create_gic(Versal *s, qemu_fdt_setprop(s->cfg.fdt, node, "interrupt-controller", NULL, 0= ); } =20 versal_create_gic_its(s, map, dev, mr, node); =20 + g_array_append_val(s->intc, dev); + return dev; } =20 static void connect_gic_to_cpu(const VersalCpuClusterMap *map, DeviceState *gic, DeviceState *cpu, size_t = idx, @@ -606,13 +646,15 @@ static inline void versal_create_and_connect_gic(Vers= al *s, MemoryRegion *mr, DeviceState **cpus, size_t num_cpu) { DeviceState *gic; + int first_cpu_idx; size_t i; =20 - gic =3D versal_create_gic(s, map, mr, num_cpu); + first_cpu_idx =3D CPU(cpus[0])->cpu_index; + gic =3D versal_create_gic(s, map, mr, first_cpu_idx, num_cpu); =20 for (i =3D 0; i < num_cpu; i++) { connect_gic_to_cpu(map, gic, cpus[i], i, num_cpu); } } @@ -1537,10 +1579,14 @@ static void versal_realize(DeviceState *dev, Error = **errp) =20 s->phandle.clk_25mhz =3D fdt_add_clk_node(s, "/clk25", 25 * 1000 * 100= 0); s->phandle.clk_125mhz =3D fdt_add_clk_node(s, "/clk125", 125 * 1000 * = 1000); s->phandle.gic =3D qemu_fdt_alloc_phandle(s->cfg.fdt); =20 + container =3D object_new(TYPE_CONTAINER); + object_property_add_child(OBJECT(s), "irq-splits", container); + object_unref(container); + container =3D object_new(TYPE_CONTAINER); object_property_add_child(OBJECT(s), "irq-or-gates", container); object_unref(container); =20 qemu_fdt_setprop_cell(s->cfg.fdt, "/", "interrupt-parent", s->phandle.= gic); @@ -1718,10 +1764,11 @@ static void versal_base_init(Object *obj) =20 memory_region_init(&s->lpd.rpu.mr, obj, "mr-rpu", UINT64_MAX); memory_region_init(&s->mr_ps, obj, "mr-ps-switch", UINT64_MAX); memory_region_init_alias(&s->lpd.rpu.mr_ps_alias, OBJECT(s), "mr-rpu-ps-alias", &s->mr_ps, 0, UINT64_MAX); + s->intc =3D g_array_new(false, false, sizeof(DeviceState *)); =20 num_can =3D versal_get_map(s)->num_canfd; s->cfg.canbus =3D g_new0(CanBusState *, num_can); =20 for (i =3D 0; i < num_can; i++) { @@ -1735,10 +1782,11 @@ static void versal_base_init(Object *obj) =20 static void versal_base_finalize(Object *obj) { Versal *s =3D XLNX_VERSAL_BASE(obj); =20 + g_array_free(s->intc, true); g_free(s->cfg.canbus); } =20 static const Property versal_properties[] =3D { DEFINE_PROP_LINK("ddr", Versal, cfg.mr_ddr, TYPE_MEMORY_REGION, --=20 2.51.0