From nobody Sun Sep 28 16:32:16 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1758857180734176.2202620454418; Thu, 25 Sep 2025 20:26:20 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v1z4W-0002jo-Cc; Thu, 25 Sep 2025 23:24:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v1z4T-0002jP-Cw; Thu, 25 Sep 2025 23:24:33 -0400 Received: from sgoci-sdnproxy-4.icoremail.net ([129.150.39.64]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v1z4C-0005Tl-T9; Thu, 25 Sep 2025 23:24:33 -0400 Received: from prodtpl.icoremail.net (unknown [10.12.1.20]) by hzbj-icmmx-6 (Coremail) with SMTP id AQAAfwAnvWBNB9Zo9lt8Bw--.5833S2; Fri, 26 Sep 2025 11:23:57 +0800 (CST) Received: from phytium.com.cn (unknown [218.76.62.144]) by mail (Coremail) with SMTP id AQAAfwAHa+hBB9Zoe_wgAA--.9731S3; Fri, 26 Sep 2025 11:23:45 +0800 (CST) From: Tao Tang To: Eric Auger , Peter Maydell Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, Chen Baozi , Pierrick Bouvier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jean-Philippe Brucker , Mostafa Saleh , Tao Tang Subject: [PATCH v2 13/14] hw/arm/smmuv3: Add property to enable Secure SMMU support Date: Fri, 26 Sep 2025 11:23:39 +0800 Message-Id: <20250926032339.1089647-1-tangtao1634@phytium.com.cn> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250925162618.191242-1-tangtao1634@phytium.com.cn> References: <20250925162618.191242-1-tangtao1634@phytium.com.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAfwAHa+hBB9Zoe_wgAA--.9731S3 X-CM-SenderInfo: pwdqw3tdrrljuu6sx5pwlxzhxfrphubq/1tbiAQAFBWjVmkcBvQAAsd Authentication-Results: hzbj-icmmx-6; spf=neutral smtp.mail=tangtao163 4@phytium.com.cn; X-Coremail-Antispam: 1Uk129KBjvJXoW7KrWktFyDKr15WFyDGFyDKFg_yoW5JFy5pF s3Ar1rKr45u3WfJay7Za18Zay2v3yvq3ZxurW8C3Wru3WDAryDXr4vkr48Ga98Xw1Yya1x WF48uF48CF42vrJanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUj1kv1TuYvTs0mT0YCTnIWj DUYxn0WfASr-VFAU7a7-sFnT9fnUUIcSsGvfJ3UbIYCTnIWIevJa73UjIFyTuYvj4RJUUU UUUUU Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=129.150.39.64; envelope-from=tangtao1634@phytium.com.cn; helo=sgoci-sdnproxy-4.icoremail.net X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1758857182413116600 Content-Type: text/plain; charset="utf-8" My apologies, resending patches 13-14/14 to fix a threading mistake from my previous attempt. This commit completes the initial implementation of the Secure SMMUv3 model by making the feature user-configurable. A new boolean property, "secure-impl", is introduced to the device. This property defaults to false, ensuring backward compatibility for existing machine types that do not expect the secure programming interface. When "secure-impl" is set to true, the smmuv3_init_regs function now initializes the secure register bank (bank[SMMU_SEC_IDX_S]). Crucially, the S_IDR1.SECURE_IMPL bit is set according to this property, correctly advertising the presence of the secure functionality to the guest. This patch ties together all the previous refactoring work. With this property enabled, the banked registers, security-aware queues, and other secure features become active, allowing a guest to probe and configure the Secure SMMU. Signed-off-by: Tao Tang --- hw/arm/smmuv3.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index c92cc0f06a..80fbc25cf5 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -351,6 +351,16 @@ static void smmuv3_init_regs(SMMUv3State *s) s->statusr =3D 0; s->bank[SMMU_SEC_IDX_NS].gbpa =3D SMMU_GBPA_RESET_VAL; + /* Initialize Secure bank (SMMU_SEC_IDX_S) */ + memset(s->bank[SMMU_SEC_IDX_S].idr, 0, sizeof(s->bank[SMMU_SEC_IDX_S].= idr)); + s->bank[SMMU_SEC_IDX_S].idr[1] =3D FIELD_DP32(s->bank[SMMU_SEC_IDX_S].= idr[1], + S_IDR1, SECURE_IMPL, + s->secure_impl); + s->bank[SMMU_SEC_IDX_S].idr[1] =3D FIELD_DP32( + s->bank[SMMU_SEC_IDX_S].idr[1], IDR1, SIDSIZE, SMMU_IDR1_SIDSIZE); + s->bank[SMMU_SEC_IDX_S].gbpa =3D SMMU_GBPA_RESET_VAL; + s->bank[SMMU_SEC_IDX_S].cmdq.entry_size =3D sizeof(struct Cmd); + s->bank[SMMU_SEC_IDX_S].eventq.entry_size =3D sizeof(struct Evt); } static int smmu_get_ste(SMMUv3State *s, dma_addr_t addr, STE *buf, @@ -2505,6 +2515,12 @@ static const Property smmuv3_properties[] =3D { * Defaults to stage 1 */ DEFINE_PROP_STRING("stage", SMMUv3State, stage), + /* + * SECURE_IMPL field in S_IDR1 register. + * Indicates whether secure state is implemented. + * Defaults to false (0) + */ + DEFINE_PROP_BOOL("secure-impl", SMMUv3State, secure_impl, false), }; static void smmuv3_instance_init(Object *obj) -- 2.34.1