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([71.212.157.132]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-27ed6ac37efsm35829425ad.137.2025.09.25.17.11.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Sep 2025 17:11:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758845498; x=1759450298; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=eYnftHW1Ls4w3e04vsyEzSpq9klvXAp2CYI/RMc0+3o=; b=iQ+9XslVBDuNheoEYTDfDyAlIPa9wNDzV2hCQUbK7VKPr8/UuT1LTYk1HMDO2DuHOf /e2KtCmyAA1zdMDr8bM9MhJWUw4g6yNLTZrSAfOxu7aGHchsp9xAHuxH+TbRY5+1kKcw O5rUXyjdA1DitcLy+023rwSX1cvdLWdIMrl3ECd9rNP+Ym65TEbvb2uX3MmWypr1xeEA 8C+4Qtt8OxHgIOzYK+kfe6wSk6fEXOHq6hVCuV/Q6N3Hz7wvGgjZE0IfJjjVbplcGdHO LoX7rbZubF3lEA7NbX7Xu8VLE4eJeg7wyaKohUt+/zQjOs2rssJa1q4IdvEjAO1JAztm 4ePg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758845498; x=1759450298; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eYnftHW1Ls4w3e04vsyEzSpq9klvXAp2CYI/RMc0+3o=; b=XfbFAgzIdpkwECvKomillXYx/7c7XLg3ORzmcO2coJ0U5Vph3521tZW22dvEmeKSsN AyoRoC5WEzFMB65WbgvgWkJ/hIVo2Ig5EK/q4GXJmf4SV1UhwSGeEMMLHdj2jtrBjABS WecYCE4112F9AhsgvkITgTgUdaFyEeeo9P8AQsTqnD2ApIKBorF2KEI5SIgPE45wo4IM wCEgiV+maviH5XEpoJhDElV8dJYR4h7Bhk3hkYQwesJHXvyQ2cP7A5CLo7ScIk83+cdH gWcEf6ZqSuDYB4jQ/vlGIL7sDIgxxh28USJy8dJ4XrOXGJQQ4/Gge1Nn6D/RrqMfQyvi 1qyw== X-Gm-Message-State: AOJu0YzBxxHB5YAamzh96Y8UUdPalh3SgZQfUE2R/s93ln/IL5mGnjBO YHf3KiWj2z63f62G6Cm8SQZScOzNx/LrVqj5PZck8rNkLf3ed6DihalPYdsmcR382BAIHWtA4y3 5qVMX X-Gm-Gg: ASbGncuugs3urUAWRudNZSCCvi6L5Ivo1hGwco168CILQeIttEEFryNVQ0IA5AA7sV4 E4CaG70B1sW6qK41rJ29FFekqtBcyfEfY4zvKsOfcu7y2Q2u3dh7iZh/wLO0ytCaQMo8UZNJgK0 sqtqZpBtEFgrp/OorObLl/rqaJZRAdwR42WcqxfGSbecFHJQBH//56H/WyIFFYek8nt0WCy4I5U fCOLXi0eEUaF+guikK+OgzYCLafVUdHBZ20Ze3yl+YhHXmlPH/0g3rfzZctEwIgJdKv6Nxy4vB2 uG1tC2hJPwYFikIOZ79ltDV/I4N9OOfndIG9kRTM5aAK6j1AohH9kk4WVVzDjGMVz/3b2oX54xj K7nhtlVfTamSooIdgZdoDi85C8gsY X-Google-Smtp-Source: AGHT+IFiQNvVqZN5bODojKemhRXAqXBpbHIhTR+XD/3j+as/g9di5GTd0zV7xwRR0s7QG/JhLyxh8g== X-Received: by 2002:a17:902:da47:b0:250:643e:c947 with SMTP id d9443c01a7336-27ed4a91a3emr51408355ad.28.1758845498532; Thu, 25 Sep 2025 17:11:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 04/10] target/arm: Add cur_space to S1Translate Date: Thu, 25 Sep 2025 17:11:28 -0700 Message-ID: <20250926001134.295547-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250926001134.295547-1-richard.henderson@linaro.org> References: <20250926001134.295547-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, T_SPF_HELO_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758845613893116600 Content-Type: text/plain; charset="utf-8" We've been updating in_space and then using hacks to access the original space. Instead, update cur_space and leave in_space unchanged. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 37 +++++++++++++++++++------------------ 1 file changed, 19 insertions(+), 18 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 6344971fa6..1cafe8f4f7 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -36,8 +36,6 @@ typedef struct S1Translate { /* * in_space: the security space for this walk. This plus * the in_mmu_idx specify the architectural translation regime. - * If a Secure ptw is "downgraded" to NonSecure by an NSTable bit, - * this field is updated accordingly. * * Note that the security space for the in_ptw_idx may be different * from that for the in_mmu_idx. We do not need to explicitly track @@ -52,6 +50,11 @@ typedef struct S1Translate { * value being Stage2 vs Stage2_S distinguishes those. */ ARMSecuritySpace in_space; + /* + * Like in_space, except this may be "downgraded" to NonSecure + * by an NSTable bit. + */ + ARMSecuritySpace cur_space; /* * in_debug: is this a QEMU debug access (gdbstub, etc)? Debug * accesses will not update the guest page table access flags @@ -587,7 +590,8 @@ static bool S1_ptw_translate(CPUARMState *env, S1Transl= ate *ptw, * From gdbstub, do not use softmmu so that we don't modify the * state of the cpu at all, including softmmu tlb contents. */ - ARMSecuritySpace s2_space =3D S2_security_space(ptw->in_space, s2_= mmu_idx); + ARMSecuritySpace s2_space + =3D S2_security_space(ptw->cur_space, s2_mmu_idx); S1Translate s2ptw =3D { .in_mmu_idx =3D s2_mmu_idx, .in_ptw_idx =3D ptw_idx_for_stage_2(env, s2_mmu_idx), @@ -630,7 +634,7 @@ static bool S1_ptw_translate(CPUARMState *env, S1Transl= ate *ptw, } =20 if (regime_is_stage2(s2_mmu_idx)) { - uint64_t hcr =3D arm_hcr_el2_eff_secstate(env, ptw->in_space); + uint64_t hcr =3D arm_hcr_el2_eff_secstate(env, ptw->cur_space); =20 if ((hcr & HCR_PTW) && S2_attrs_are_device(hcr, pte_attrs)) { /* @@ -641,7 +645,7 @@ static bool S1_ptw_translate(CPUARMState *env, S1Transl= ate *ptw, fi->s2addr =3D addr; fi->stage2 =3D true; fi->s1ptw =3D true; - fi->s1ns =3D fault_s1ns(ptw->in_space, s2_mmu_idx); + fi->s1ns =3D fault_s1ns(ptw->cur_space, s2_mmu_idx); return false; } } @@ -657,7 +661,7 @@ static bool S1_ptw_translate(CPUARMState *env, S1Transl= ate *ptw, fi->s2addr =3D addr; fi->stage2 =3D regime_is_stage2(s2_mmu_idx); fi->s1ptw =3D fi->stage2; - fi->s1ns =3D fault_s1ns(ptw->in_space, s2_mmu_idx); + fi->s1ns =3D fault_s1ns(ptw->cur_space, s2_mmu_idx); return false; } =20 @@ -844,7 +848,7 @@ static uint64_t arm_casq_ptw(CPUARMState *env, uint64_t= old_val, fi->s2addr =3D ptw->out_virt; fi->stage2 =3D true; fi->s1ptw =3D true; - fi->s1ns =3D fault_s1ns(ptw->in_space, ptw->in_ptw_idx); + fi->s1ns =3D fault_s1ns(ptw->cur_space, ptw->in_ptw_idx); return 0; } =20 @@ -1224,7 +1228,7 @@ static bool get_phys_addr_v6(CPUARMState *env, S1Tran= slate *ptw, g_assert_not_reached(); } } - out_space =3D ptw->in_space; + out_space =3D ptw->cur_space; if (ns) { /* * The NS bit will (as required by the architecture) have no effec= t if @@ -1254,7 +1258,7 @@ static bool get_phys_addr_v6(CPUARMState *env, S1Tran= slate *ptw, } =20 result->f.prot =3D get_S1prot(env, mmu_idx, false, user_rw, prot_r= w, - xn, pxn, result->f.attrs.space, out_sp= ace); + xn, pxn, ptw->in_space, out_space); if (ptw->in_prot_check & ~result->f.prot) { /* Access permission fault. */ fi->type =3D ARMFault_Permission; @@ -1857,7 +1861,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Tr= anslate *ptw, * NonSecure. With RME, the EL3 translation regime does not change * from Root to NonSecure. */ - if (ptw->in_space =3D=3D ARMSS_Secure + if (ptw->cur_space =3D=3D ARMSS_Secure && !regime_is_stage2(mmu_idx) && extract32(tableattrs, 4, 1)) { /* @@ -1867,7 +1871,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Tr= anslate *ptw, QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_S + 1 !=3D ARMMMUIdx_Phys_NS); QEMU_BUILD_BUG_ON(ARMMMUIdx_Stage2_S + 1 !=3D ARMMMUIdx_Stage2); ptw->in_ptw_idx +=3D 1; - ptw->in_space =3D ARMSS_NonSecure; + ptw->cur_space =3D ARMSS_NonSecure; } =20 if (!S1_ptw_translate(env, ptw, descaddr, fi)) { @@ -1991,7 +1995,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Tr= anslate *ptw, } =20 ap =3D extract32(attrs, 6, 2); - out_space =3D ptw->in_space; + out_space =3D ptw->cur_space; if (regime_is_stage2(mmu_idx)) { /* * R_GYNXY: For stage2 in Realm security state, bit 55 is NS. @@ -2089,12 +2093,8 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1T= ranslate *ptw, =20 user_rw =3D simple_ap_to_rw_prot_is_user(ap, true); prot_rw =3D simple_ap_to_rw_prot_is_user(ap, false); - /* - * Note that we modified ptw->in_space earlier for NSTable, but - * result->f.attrs retains a copy of the original security space. - */ result->f.prot =3D get_S1prot(env, mmu_idx, aarch64, user_rw, prot= _rw, - xn, pxn, result->f.attrs.space, out_sp= ace); + xn, pxn, ptw->in_space, out_space); =20 /* Index into MAIR registers for cache attributes */ attrindx =3D extract32(attrs, 2, 3); @@ -2192,7 +2192,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Tr= anslate *ptw, fi->level =3D level; fi->stage2 =3D regime_is_stage2(mmu_idx); } - fi->s1ns =3D fault_s1ns(ptw->in_space, mmu_idx); + fi->s1ns =3D fault_s1ns(ptw->cur_space, mmu_idx); return true; } =20 @@ -3413,6 +3413,7 @@ static bool get_phys_addr_nogpc(CPUARMState *env, S1T= ranslate *ptw, * cannot upgrade a NonSecure translation regime's attributes * to Secure or Realm. */ + ptw->cur_space =3D ptw->in_space; result->f.attrs.space =3D ptw->in_space; result->f.attrs.secure =3D arm_space_is_secure(ptw->in_space); =20 --=20 2.43.0