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(unknown [9.10.239.198]) by smtpav02.dal12v.mail.ibm.com (Postfix) with ESMTP; Thu, 25 Sep 2025 20:18:50 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=9FCc7wBAmkc7vYS4b Ig+hKEEzQV3GlWgvAfLxEe9huQ=; b=VazvD9eJLzrUi9vHuvQYimZPWZ5SGkvLL wBZKj8umUOD87mdk8KIeA4w54BfHI6PAWKrHMgYYBLtaQ/HrzoRkaceRiCAsQu2v L/oVgTHcl2MvkU6ZwB0qct3w9u4JCQlwsRwnwdfds+pdsDtW+0JgzOy0OPAQNg0M OBa+QClTrFkfsYWykWizxp1o+3biwTbWlWzbm4RfFsqv8v21/NC5KZcxubbEH1mj 6lg8EYf0ZuO9rbV8CqyvD5U1Gj6WzZahKLAKloklnxUQqJW4EgjWDr5AH8DpMs7s g65AmsAV88MfbSGelXM9RFKq9x/2cOXUWdOF20XgEr18GgHSsCMzg== From: Glenn Miles To: qemu-devel@nongnu.org Cc: Glenn Miles , qemu-ppc@nongnu.org, clg@redhat.com, npiggin@gmail.com, harshpb@linux.ibm.com, thuth@redhat.com, rathc@linux.ibm.com, richard.henderson@linaro.org Subject: [PATCH v6 4/9] target/ppc: Add IBM PPE42 exception model Date: Thu, 25 Sep 2025 15:17:42 -0500 Message-ID: <20250925201758.652077-5-milesg@linux.ibm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250925201758.652077-1-milesg@linux.ibm.com> References: <20250925201758.652077-1-milesg@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Authority-Analysis: v=2.4 cv=MfBhep/f c=1 sm=1 tr=0 ts=68d5a3ac cx=c_pps a=bLidbwmWQ0KltjZqbj+ezA==:117 a=bLidbwmWQ0KltjZqbj+ezA==:17 a=yJojWOMRYYMA:10 a=VnNF1IyMAAAA:8 a=h1b_CP1ddBs6gX6iP-IA:9 a=cPQSjfK2_nFv0Q5t_7PE:22 X-Proofpoint-GUID: 8KUYQutOsuCDFLYzxSb9V8EVd07AiIhu X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTI1MDE3NCBTYWx0ZWRfXwj1uiYjt29SQ RyTr+ke28SLKljAW64anhZR74Dz2c64toD6mi5iE4+9NLYNyn2/zMnrXg0G42aYO6cC6JUhyCSt IC5KbwVymtYfl9vhRs0F/PzepV8TtybqtSNPcSYnh43ophQOS6GM35md7CHi+nZv9ks1DPGc5df VDTF5V2OETivshdcv/xunvn8mZcJ0ppCfSnPZdfRpkH60RgdV5K8bFAi+XzBVk/vGVX+W2r8ieO BjhTT2HT78nuXBYQeQgvzlD7uSY/3CDHn9AmK1ibJi8YZMvMTa5alYl1badct/emYm1I7dKZH3m KQ8ZcA+vfKZw6aFExb1GqdWOsc9KOflVz2N6KJCVuO/kQaEX5st1wbFXuHRZLJwOHLHVKfe/19G 6FWhlFf2SkZZtUbypTt5yE/1iWuC+w== X-Proofpoint-ORIG-GUID: TaZ1yPr3nH-rIcE2QcgY4rrUKO31ZSGk X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-25_01,2025-09-25_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 malwarescore=0 impostorscore=0 phishscore=0 bulkscore=0 adultscore=0 lowpriorityscore=0 spamscore=0 suspectscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2509150000 definitions=main-2509250174 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=milesg@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1758831646246116600 Content-Type: text/plain; charset="utf-8" Add support for the IBM PPE42 exception model including new exception vectors, exception priorities and setting of PPE42 SPRs for determining the cause of an exception. Signed-off-by: Glenn Miles Reviewed-by: Chinmay Rath --- target/ppc/cpu_init.c | 39 ++++++++- target/ppc/excp_helper.c | 163 +++++++++++++++++++++++++++++++++++ target/ppc/tcg-excp_helper.c | 12 +++ 3 files changed, 213 insertions(+), 1 deletion(-) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index c78b255085..9e4ea8fd13 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -1720,6 +1720,30 @@ static void init_excp_4xx(CPUPPCState *env) #endif } =20 +static void init_excp_ppe42(CPUPPCState *env) +{ +#if !defined(CONFIG_USER_ONLY) + /* Machine Check vector changed after version 0 */ + if (((env->spr[SPR_PVR] & 0xf00000ul) >> 20) =3D=3D 0) { + env->excp_vectors[POWERPC_EXCP_MCHECK] =3D 0x00000000; + } else { + env->excp_vectors[POWERPC_EXCP_MCHECK] =3D 0x00000020; + } + env->excp_vectors[POWERPC_EXCP_RESET] =3D 0x00000040; + env->excp_vectors[POWERPC_EXCP_DSI] =3D 0x00000060; + env->excp_vectors[POWERPC_EXCP_ISI] =3D 0x00000080; + env->excp_vectors[POWERPC_EXCP_EXTERNAL] =3D 0x000000A0; + env->excp_vectors[POWERPC_EXCP_ALIGN] =3D 0x000000C0; + env->excp_vectors[POWERPC_EXCP_PROGRAM] =3D 0x000000E0; + env->excp_vectors[POWERPC_EXCP_DECR] =3D 0x00000100; + env->excp_vectors[POWERPC_EXCP_FIT] =3D 0x00000120; + env->excp_vectors[POWERPC_EXCP_WDT] =3D 0x00000140; + env->ivpr_mask =3D 0xFFFFFE00UL; + /* Hardware reset vector */ + env->hreset_vector =3D 0x00000040UL; +#endif +} + static void init_excp_MPC5xx(CPUPPCState *env) { #if !defined(CONFIG_USER_ONLY) @@ -2245,6 +2269,7 @@ static void init_proc_ppe42(CPUPPCState *env) { register_ppe42_sprs(env); =20 + init_excp_ppe42(env); env->dcache_line_size =3D 32; env->icache_line_size =3D 32; /* Allocate hardware IRQ controller */ @@ -2278,7 +2303,7 @@ static void ppe42_class_common_init(PowerPCCPUClass *= pcc) (1ull << MSR_IPE) | R_MSR_SIBRCA_MASK; pcc->mmu_model =3D POWERPC_MMU_REAL; - pcc->excp_model =3D POWERPC_EXCP_40x; + pcc->excp_model =3D POWERPC_EXCP_PPE42; pcc->bus_model =3D PPC_FLAGS_INPUT_PPE42; pcc->bfd_mach =3D bfd_mach_ppc_403; pcc->flags =3D POWERPC_FLAG_PPE42 | POWERPC_FLAG_BUS_CLK; @@ -7856,6 +7881,18 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, int f= lags) * they can be read with "p $ivor0", "p $ivor1", etc. */ break; + case POWERPC_EXCP_PPE42: + qemu_fprintf(f, "SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx "\n", + env->spr[SPR_SRR0], env->spr[SPR_SRR1]); + + qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx + " ISR " TARGET_FMT_lx " EDR " TARGET_FMT_lx "\n", + env->spr[SPR_PPE42_TCR], env->spr[SPR_PPE42_TSR], + env->spr[SPR_PPE42_ISR], env->spr[SPR_PPE42_EDR]); + + qemu_fprintf(f, " PIR " TARGET_FMT_lx " IVPR " TARGET_FMT_lx "\= n", + env->spr[SPR_PPE42_PIR], env->spr[SPR_PPE42_IVPR]); + break; case POWERPC_EXCP_40x: qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n= ", diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 1efdc4066e..d8bca19fff 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -949,6 +949,125 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int ex= cp) powerpc_set_excp_state(cpu, vector, new_msr); } =20 +static void powerpc_excp_ppe42(PowerPCCPU *cpu, int excp) +{ + CPUPPCState *env =3D &cpu->env; + target_ulong msr, new_msr, vector; + target_ulong mcs =3D PPE42_ISR_MCS_INSTRUCTION; + bool promote_unmaskable; + + msr =3D env->msr; + + /* + * New interrupt handler msr preserves SIBRC and ME unless explicitly + * overridden by the exception. All other MSR bits are zeroed out. + */ + new_msr =3D env->msr & (((target_ulong)1 << MSR_ME) | R_MSR_SIBRC_MASK= ); + + /* HV emu assistance interrupt only exists on server arch 2.05 or late= r */ + if (excp =3D=3D POWERPC_EXCP_HV_EMU) { + excp =3D POWERPC_EXCP_PROGRAM; + } + + /* + * Unmaskable interrupts (Program, ISI, Alignment and DSI) are promote= d to + * machine check if MSR_UIE is 0. + */ + promote_unmaskable =3D !(msr & ((target_ulong)1 << MSR_UIE)); + + + switch (excp) { + case POWERPC_EXCP_MCHECK: /* Machine check exception = */ + break; + case POWERPC_EXCP_DSI: /* Data storage exception = */ + trace_ppc_excp_dsi(env->spr[SPR_PPE42_ISR], env->spr[SPR_PPE42_EDR= ]); + if (promote_unmaskable) { + excp =3D POWERPC_EXCP_MCHECK; + mcs =3D PPE42_ISR_MCS_DSI; + } + break; + case POWERPC_EXCP_ISI: /* Instruction storage exception = */ + trace_ppc_excp_isi(msr, env->nip); + if (promote_unmaskable) { + excp =3D POWERPC_EXCP_MCHECK; + mcs =3D PPE42_ISR_MCS_ISI; + } + break; + case POWERPC_EXCP_EXTERNAL: /* External input = */ + break; + case POWERPC_EXCP_ALIGN: /* Alignment exception = */ + if (promote_unmaskable) { + excp =3D POWERPC_EXCP_MCHECK; + mcs =3D PPE42_ISR_MCS_ALIGNMENT; + } + break; + case POWERPC_EXCP_PROGRAM: /* Program exception = */ + if (promote_unmaskable) { + excp =3D POWERPC_EXCP_MCHECK; + mcs =3D PPE42_ISR_MCS_PROGRAM; + } + switch (env->error_code & ~0xF) { + case POWERPC_EXCP_INVAL: + trace_ppc_excp_inval(env->nip); + env->spr[SPR_PPE42_ISR] &=3D ~((target_ulong)1 << PPE42_ISR_PT= R); + break; + case POWERPC_EXCP_TRAP: + env->spr[SPR_PPE42_ISR] |=3D ((target_ulong)1 << PPE42_ISR_PTR= ); + break; + default: + /* Should never occur */ + cpu_abort(env_cpu(env), "Invalid program exception %d. Abortin= g\n", + env->error_code); + break; + } +#ifdef CONFIG_TCG + env->spr[SPR_PPE42_EDR] =3D ppc_ldl_code(env, env->nip); +#endif + break; + case POWERPC_EXCP_DECR: /* Decrementer exception = */ + break; + case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt = */ + trace_ppc_excp_print("FIT"); + break; + case POWERPC_EXCP_WDT: /* Watchdog timer interrupt = */ + trace_ppc_excp_print("WDT"); + break; + case POWERPC_EXCP_RESET: /* System reset exception = */ + /* reset exceptions don't have ME set */ + new_msr &=3D ~((target_ulong)1 << MSR_ME); + break; + default: + cpu_abort(env_cpu(env), "Invalid PPE42 exception %d. Aborting\n", + excp); + break; + } + + env->spr[SPR_SRR0] =3D env->nip; + env->spr[SPR_SRR1] =3D msr; + + vector =3D env->excp_vectors[excp]; + if (vector =3D=3D (target_ulong)-1ULL) { + cpu_abort(env_cpu(env), + "Raised an exception without defined vector %d\n", excp); + } + vector |=3D env->spr[SPR_PPE42_IVPR]; + + if (excp =3D=3D POWERPC_EXCP_MCHECK) { + /* Also set the Machine Check Status (MCS) */ + env->spr[SPR_PPE42_ISR] &=3D ~R_PPE42_ISR_MCS_MASK; + env->spr[SPR_PPE42_ISR] |=3D (mcs & R_PPE42_ISR_MCS_MASK); + env->spr[SPR_PPE42_ISR] &=3D ~((target_ulong)1 << PPE42_ISR_MFE); + + /* Machine checks halt execution if MSR_ME is 0 */ + powerpc_mcheck_checkstop(env); + + /* machine check exceptions don't have ME set */ + new_msr &=3D ~((target_ulong)1 << MSR_ME); + } + + powerpc_set_excp_state(cpu, vector, new_msr); +} + static void powerpc_excp_booke(PowerPCCPU *cpu, int excp) { CPUPPCState *env =3D &cpu->env; @@ -1589,6 +1708,9 @@ void powerpc_excp(PowerPCCPU *cpu, int excp) case POWERPC_EXCP_POWER11: powerpc_excp_books(cpu, excp); break; + case POWERPC_EXCP_PPE42: + powerpc_excp_ppe42(cpu, excp); + break; default: g_assert_not_reached(); } @@ -1945,6 +2067,43 @@ static int p9_next_unmasked_interrupt(CPUPPCState *e= nv, } #endif /* TARGET_PPC64 */ =20 +static int ppe42_next_unmasked_interrupt(CPUPPCState *env) +{ + bool async_deliver; + + /* External reset */ + if (env->pending_interrupts & PPC_INTERRUPT_RESET) { + return PPC_INTERRUPT_RESET; + } + /* Machine check exception */ + if (env->pending_interrupts & PPC_INTERRUPT_MCK) { + return PPC_INTERRUPT_MCK; + } + + async_deliver =3D FIELD_EX64(env->msr, MSR, EE); + + if (async_deliver !=3D 0) { + /* Watchdog timer */ + if (env->pending_interrupts & PPC_INTERRUPT_WDT) { + return PPC_INTERRUPT_WDT; + } + /* External Interrupt */ + if (env->pending_interrupts & PPC_INTERRUPT_EXT) { + return PPC_INTERRUPT_EXT; + } + /* Fixed interval timer */ + if (env->pending_interrupts & PPC_INTERRUPT_FIT) { + return PPC_INTERRUPT_FIT; + } + /* Decrementer exception */ + if (env->pending_interrupts & PPC_INTERRUPT_DECR) { + return PPC_INTERRUPT_DECR; + } + } + + return 0; +} + static int ppc_next_unmasked_interrupt(CPUPPCState *env) { uint32_t pending_interrupts =3D env->pending_interrupts; @@ -1970,6 +2129,10 @@ static int ppc_next_unmasked_interrupt(CPUPPCState *= env) } #endif =20 + if (env->excp_model =3D=3D POWERPC_EXCP_PPE42) { + return ppe42_next_unmasked_interrupt(env); + } + /* External reset */ if (pending_interrupts & PPC_INTERRUPT_RESET) { return PPC_INTERRUPT_RESET; diff --git a/target/ppc/tcg-excp_helper.c b/target/ppc/tcg-excp_helper.c index f835be5156..edecfb8572 100644 --- a/target/ppc/tcg-excp_helper.c +++ b/target/ppc/tcg-excp_helper.c @@ -229,6 +229,18 @@ void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr v= addr, case POWERPC_MMU_BOOKE206: env->spr[SPR_BOOKE_DEAR] =3D vaddr; break; + case POWERPC_MMU_REAL: + if (env->flags & POWERPC_FLAG_PPE42) { + env->spr[SPR_PPE42_EDR] =3D vaddr; + if (access_type =3D=3D MMU_DATA_STORE) { + env->spr[SPR_PPE42_ISR] |=3D PPE42_ISR_ST; + } else { + env->spr[SPR_PPE42_ISR] &=3D ~PPE42_ISR_ST; + } + } else { + env->spr[SPR_DAR] =3D vaddr; + } + break; default: env->spr[SPR_DAR] =3D vaddr; break; --=20 2.43.0