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(unknown [9.10.239.198]) by smtpav02.dal12v.mail.ibm.com (Postfix) with ESMTP; Thu, 25 Sep 2025 20:18:45 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=xZD0+yS0L5qcJJtfr NXA9CFmxbJ6dxB79aBk4VpH3wY=; b=PGv5V9iBf6VIrhwYd4l9sjJ5ukUgAyx+P nzHgUlAEmadT+e83XYIAzuMkGOb3o1dDbTnv1UhapusMoCdmU3DRU7lhUNbyX6zr n+wGamiTKwUqoYKWHuzJ/L0FzNM3TkZN26F9MWbhQ+OJbPIG2+jYYr09fmO4dQUt 0Lnbrs4FYfEkIVB3Ss0b4dIPGpVo91QpxwbnrPzbYISqfXA4oEKEBp/Fz5oVFhkC VIg0mgsHlBn8wgYy/QgPPQUNJ+03p9+f0MBD/Ht1sTDHnzBwLBBPaytv03t2LoqZ jKr0OdoWHehGhcWB4Lnq8UKtdbrmrOT7b/1sYQi8oLawn4F1q3F0w== From: Glenn Miles To: qemu-devel@nongnu.org Cc: Glenn Miles , qemu-ppc@nongnu.org, clg@redhat.com, npiggin@gmail.com, harshpb@linux.ibm.com, thuth@redhat.com, rathc@linux.ibm.com, richard.henderson@linaro.org Subject: [PATCH v6 2/9] target/ppc: Add IBM PPE42 family of processors Date: Thu, 25 Sep 2025 15:17:40 -0500 Message-ID: <20250925201758.652077-3-milesg@linux.ibm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250925201758.652077-1-milesg@linux.ibm.com> References: <20250925201758.652077-1-milesg@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Authority-Analysis: v=2.4 cv=BbvVE7t2 c=1 sm=1 tr=0 ts=68d5a3a9 cx=c_pps a=5BHTudwdYE3Te8bg5FgnPg==:117 a=5BHTudwdYE3Te8bg5FgnPg==:17 a=yJojWOMRYYMA:10 a=jRLB2SoPAAAA:8 a=VnNF1IyMAAAA:8 a=CMSrYuGzgbGWQ58TYJUA:9 a=yloqiLrygL2q3s9aD-8D:22 a=cPQSjfK2_nFv0Q5t_7PE:22 X-Proofpoint-ORIG-GUID: tMsZHmCPo7ZRDpIbY-0Q5rUnBANUdxVr X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTI1MDE3NCBTYWx0ZWRfX6qQHJlNwBS09 tjold+3hjjUIsF4tICi9pOwpEQQ+NvIlMJnK2n7kpuN5VaI9uaiVzOIpVEIdPRkKueySHMZp7Vy jBpPJsqbeVEq8JlsX8Jv70T3ddxb32l2cXOQpswPinFis7qaFZFp8VKiQEtTxt53o3sGJJMvdkE 6rKqJ9zqZAlgyaRL2b95z4FqGWJYGDGRj3+4Phoq4D9qWqyQs0+CqvvYKLa96ABR3dfgXgo4JoM pkFu7MbMikDOeQH60O9RKg3CN/UOe0RCU6qX0NTpHXiv6Fx7Pr+t6S/Qg8YGP4Jh/7jFcjfS+pY uyz5vgQbC8wYiAS3Im9fgNovMab+o5UmRc0tGS+oSMvT0WK5wJABOiYn9GX5QIREmshZ1gvOkzd K8T1wMEb85Ou41IWqMa8wk+iZAX7fA== X-Proofpoint-GUID: NZqBV7_paCJS-GyIjtPgUI4X9Gp58Wbr X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-25_01,2025-09-25_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 malwarescore=0 spamscore=0 clxscore=1015 bulkscore=0 adultscore=0 lowpriorityscore=0 priorityscore=1501 impostorscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2509150000 definitions=main-2509250174 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=milesg@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1758831670222116600 Content-Type: text/plain; charset="utf-8" Adds the IBM PPE42 family of 32-bit processors supporting the PPE42, PPE42X and PPE42XM processor versions. These processors are used as embedded processors in the IBM Power9, Power10 and Power12 processors for various tasks. It is basically a stripped down version of the IBM PowerPC 405 processor, with some added instructions for handling 64-bit loads and stores. For more information on the PPE 42 processor please visit: https://wiki.raptorcs.com/w/images/a/a3/PPE_42X_Core_Users_Manual.pdf Supports PPE42 SPR's (Including the MSR). Does not yet support exceptions, new PPE42 instructions and does not prevent access to some invalid instructions and registers (currently allows access to invalid GPR's and CR fields). Signed-off-by: Glenn Miles Reviewed-by: Chinmay Rath --- Changes from v5: - Added missing POWERPC_FLAG_PPE42 check (Chinmay) target/ppc/cpu-models.c | 7 ++ target/ppc/cpu_init.c | 207 ++++++++++++++++++++++++++++++++------- target/ppc/helper_regs.c | 41 +++++--- target/ppc/translate.c | 6 +- 4 files changed, 205 insertions(+), 56 deletions(-) diff --git a/target/ppc/cpu-models.c b/target/ppc/cpu-models.c index ea86ea202a..09f73e23a8 100644 --- a/target/ppc/cpu-models.c +++ b/target/ppc/cpu-models.c @@ -116,6 +116,13 @@ NULL) POWERPC_DEF("x2vp20", CPU_POWERPC_X2VP20, 405, NULL) + /* PPE42 Embedded Controllers = */ + POWERPC_DEF("PPE42", CPU_POWERPC_PPE42, ppe42, + "Generic PPE 42") + POWERPC_DEF("PPE42X", CPU_POWERPC_PPE42X, ppe42= x, + "Generic PPE 42X") + POWERPC_DEF("PPE42XM", CPU_POWERPC_PPE42XM, ppe42= xm, + "Generic PPE 42XM") /* PowerPC 440 family = */ #if defined(TODO_USER_ONLY) POWERPC_DEF("440", CPU_POWERPC_440, 440GP, diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index db841f1260..c78b255085 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -1653,6 +1653,47 @@ static void register_8xx_sprs(CPUPPCState *env) * ... and more (thermal management, performance counters, ...) */ =20 +static void register_ppe42_sprs(CPUPPCState *env) +{ + spr_register(env, SPR_PPE42_EDR, "EDR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_PPE42_ISR, "ISR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_PPE42_IVPR, "IVPR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, SPR_NOACCESS, + 0xfff80000); + spr_register(env, SPR_PPE42_PIR, "PIR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_pir, + 0x00000000); + spr_register(env, SPR_PPE42_DBCR, "DBCR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_40x_dbcr0, + 0x00000000); + spr_register(env, SPR_PPE42_DACR, "DACR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Timer */ + spr_register(env, SPR_DECR, "DECR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_decr, &spr_write_decr, + 0x00000000); + spr_register(env, SPR_PPE42_TSR, "TSR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_booke_tsr, + 0x00000000); + spr_register(env, SPR_BOOKE_TCR, "TCR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_booke_tcr, + 0x00000000); +} + /*************************************************************************= ****/ /* Exception vectors models = */ static void init_excp_4xx(CPUPPCState *env) @@ -2200,6 +2241,79 @@ POWERPC_FAMILY(405)(ObjectClass *oc, const void *dat= a) POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; } =20 +static void init_proc_ppe42(CPUPPCState *env) +{ + register_ppe42_sprs(env); + + env->dcache_line_size =3D 32; + env->icache_line_size =3D 32; + /* Allocate hardware IRQ controller */ + ppc40x_irq_init(env_archcpu(env)); + + SET_FIT_PERIOD(8, 12, 16, 20); + SET_WDT_PERIOD(16, 20, 24, 28); +} + +static void ppe42_class_common_init(PowerPCCPUClass *pcc) +{ + pcc->init_proc =3D init_proc_ppe42; + pcc->check_pow =3D check_pow_nocheck; + pcc->check_attn =3D check_attn_none; + pcc->insns_flags =3D PPC_INSNS_BASE | + PPC_WRTEE | + PPC_CACHE | + PPC_CACHE_DCBZ | + PPC_MEM_SYNC; + pcc->msr_mask =3D R_MSR_SEM_MASK | + (1ull << MSR_IS0) | + R_MSR_SIBRC_MASK | + (1ull << MSR_LP) | + (1ull << MSR_WE) | + (1ull << MSR_IS1) | + (1ull << MSR_UIE) | + (1ull << MSR_EE) | + (1ull << MSR_ME) | + (1ull << MSR_IS2) | + (1ull << MSR_IS3) | + (1ull << MSR_IPE) | + R_MSR_SIBRCA_MASK; + pcc->mmu_model =3D POWERPC_MMU_REAL; + pcc->excp_model =3D POWERPC_EXCP_40x; + pcc->bus_model =3D PPC_FLAGS_INPUT_PPE42; + pcc->bfd_mach =3D bfd_mach_ppc_403; + pcc->flags =3D POWERPC_FLAG_PPE42 | POWERPC_FLAG_BUS_CLK; +} + +POWERPC_FAMILY(ppe42)(ObjectClass *oc, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + PowerPCCPUClass *pcc =3D POWERPC_CPU_CLASS(oc); + + dc->desc =3D "PPE 42"; + pcc->insns_flags2 =3D PPC2_PPE42; + ppe42_class_common_init(pcc); +} + +POWERPC_FAMILY(ppe42x)(ObjectClass *oc, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + PowerPCCPUClass *pcc =3D POWERPC_CPU_CLASS(oc); + + dc->desc =3D "PPE 42X"; + pcc->insns_flags2 =3D PPC2_PPE42 | PPC2_PPE42X; + ppe42_class_common_init(pcc); +} + +POWERPC_FAMILY(ppe42xm)(ObjectClass *oc, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + PowerPCCPUClass *pcc =3D POWERPC_CPU_CLASS(oc); + + dc->desc =3D "PPE 42XM"; + pcc->insns_flags2 =3D PPC2_PPE42 | PPC2_PPE42X | PPC2_PPE42XM; + ppe42_class_common_init(pcc); +} + static void init_proc_440EP(CPUPPCState *env) { register_BookE_sprs(env, 0x000000000000FFFFULL); @@ -6802,53 +6916,64 @@ static void init_ppc_proc(PowerPCCPU *cpu) =20 /* MSR bits & flags consistency checks */ if (env->msr_mask & (1 << 25)) { - switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) { + switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE | + POWERPC_FLAG_PPE42)) { case POWERPC_FLAG_SPE: case POWERPC_FLAG_VRE: + case POWERPC_FLAG_PPE42: break; default: fprintf(stderr, "PowerPC MSR definition inconsistency\n" - "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n"= ); + "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n" + "or POWERPC_FLAG_PPE42\n"); exit(1); } - } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) { + } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE | + POWERPC_FLAG_PPE42)) { fprintf(stderr, "PowerPC MSR definition inconsistency\n" - "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n= "); + "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n" + "nor POWERPC_FLAG_PPE42\n"); exit(1); } if (env->msr_mask & (1 << 17)) { - switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) { + switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE | + POWERPC_FLAG_PPE42)) { case POWERPC_FLAG_TGPR: case POWERPC_FLAG_CE: + case POWERPC_FLAG_PPE42: break; default: fprintf(stderr, "PowerPC MSR definition inconsistency\n" - "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n"= ); + "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n" + "or POWERPC_FLAG_PPE42\n"); exit(1); } - } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) { + } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE | + POWERPC_FLAG_PPE42)) { fprintf(stderr, "PowerPC MSR definition inconsistency\n" - "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n= "); + "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n" + "nor POWERPC_FLAG_PPE42\n"); exit(1); } if (env->msr_mask & (1 << 10)) { switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE | - POWERPC_FLAG_UBLE)) { + POWERPC_FLAG_UBLE | POWERPC_FLAG_PPE42)) { case POWERPC_FLAG_SE: case POWERPC_FLAG_DWE: case POWERPC_FLAG_UBLE: + case POWERPC_FLAG_PPE42: break; default: fprintf(stderr, "PowerPC MSR definition inconsistency\n" "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or " - "POWERPC_FLAG_UBLE\n"); + "POWERPC_FLAG_UBLE or POWERPC_FLAG_PPE42\n"); exit(1); } } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE | - POWERPC_FLAG_UBLE)) { + POWERPC_FLAG_UBLE | POWERPC_FLAG_PPE42)) { fprintf(stderr, "PowerPC MSR definition inconsistency\n" "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE no= r " - "POWERPC_FLAG_UBLE\n"); + "POWERPC_FLAG_UBLE nor POWERPC_FLAG_PPE42\n"); exit(1); } if (env->msr_mask & (1 << 9)) { @@ -6867,18 +6992,23 @@ static void init_ppc_proc(PowerPCCPU *cpu) exit(1); } if (env->msr_mask & (1 << 2)) { - switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) { + switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM | + POWERPC_FLAG_PPE42)) { case POWERPC_FLAG_PX: case POWERPC_FLAG_PMM: + case POWERPC_FLAG_PPE42: break; default: fprintf(stderr, "PowerPC MSR definition inconsistency\n" - "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n"); + "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n" + "or POWERPC_FLAG_PPE42\n"); exit(1); } - } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) { + } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM | + POWERPC_FLAG_PPE42)) { fprintf(stderr, "PowerPC MSR definition inconsistency\n" - "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n"= ); + "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n" + "nor POWERPC_FLAG_PPE42\n"); exit(1); } if ((env->flags & POWERPC_FLAG_BUS_CLK) =3D=3D 0) { @@ -7243,39 +7373,40 @@ static void ppc_cpu_reset_hold(Object *obj, ResetTy= pe type) } =20 msr =3D (target_ulong)0; - msr |=3D (target_ulong)MSR_HVB; - msr |=3D (target_ulong)1 << MSR_EP; + if (!(env->flags & POWERPC_FLAG_PPE42)) { + msr |=3D (target_ulong)MSR_HVB; + msr |=3D (target_ulong)1 << MSR_EP; #if defined(DO_SINGLE_STEP) && 0 - /* Single step trace mode */ - msr |=3D (target_ulong)1 << MSR_SE; - msr |=3D (target_ulong)1 << MSR_BE; + /* Single step trace mode */ + msr |=3D (target_ulong)1 << MSR_SE; + msr |=3D (target_ulong)1 << MSR_BE; #endif #if defined(CONFIG_USER_ONLY) - msr |=3D (target_ulong)1 << MSR_FP; /* Allow floating point usage */ - msr |=3D (target_ulong)1 << MSR_FE0; /* Allow floating point exception= s */ - msr |=3D (target_ulong)1 << MSR_FE1; - msr |=3D (target_ulong)1 << MSR_VR; /* Allow altivec usage */ - msr |=3D (target_ulong)1 << MSR_VSX; /* Allow VSX usage */ - msr |=3D (target_ulong)1 << MSR_SPE; /* Allow SPE usage */ - msr |=3D (target_ulong)1 << MSR_PR; + msr |=3D (target_ulong)1 << MSR_FP; /* Allow floating point usage = */ + msr |=3D (target_ulong)1 << MSR_FE0; /* Allow floating point excep= tions */ + msr |=3D (target_ulong)1 << MSR_FE1; + msr |=3D (target_ulong)1 << MSR_VR; /* Allow altivec usage */ + msr |=3D (target_ulong)1 << MSR_VSX; /* Allow VSX usage */ + msr |=3D (target_ulong)1 << MSR_SPE; /* Allow SPE usage */ + msr |=3D (target_ulong)1 << MSR_PR; #if defined(TARGET_PPC64) - msr |=3D (target_ulong)1 << MSR_TM; /* Transactional memory */ + msr |=3D (target_ulong)1 << MSR_TM; /* Transactional memory */ #endif #if !TARGET_BIG_ENDIAN - msr |=3D (target_ulong)1 << MSR_LE; /* Little-endian user mode */ - if (!((env->msr_mask >> MSR_LE) & 1)) { - fprintf(stderr, "Selected CPU does not support little-endian.\n"); - exit(1); - } + msr |=3D (target_ulong)1 << MSR_LE; /* Little-endian user mode */ + if (!((env->msr_mask >> MSR_LE) & 1)) { + fprintf(stderr, "Selected CPU does not support little-endian.\= n"); + exit(1); + } #endif #endif =20 #if defined(TARGET_PPC64) - if (mmu_is_64bit(env->mmu_model)) { - msr |=3D (1ULL << MSR_SF); - } + if (mmu_is_64bit(env->mmu_model)) { + msr |=3D (1ULL << MSR_SF); + } #endif - + } hreg_store_msr(env, msr, 1); =20 #if !defined(CONFIG_USER_ONLY) diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index 5f21739749..41b7b939ec 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -308,9 +308,6 @@ int hreg_store_msr(CPUPPCState *env, target_ulong value= , int alter_hv) value &=3D ~(1 << MSR_ME); value |=3D env->msr & (1 << MSR_ME); } - if ((value ^ env->msr) & (R_MSR_IR_MASK | R_MSR_DR_MASK)) { - cpu_interrupt_exittb(cs); - } if ((env->mmu_model =3D=3D POWERPC_MMU_BOOKE || env->mmu_model =3D=3D POWERPC_MMU_BOOKE206) && ((value ^ env->msr) & R_MSR_GS_MASK)) { @@ -321,8 +318,14 @@ int hreg_store_msr(CPUPPCState *env, target_ulong valu= e, int alter_hv) /* Swap temporary saved registers with GPRs */ hreg_swap_gpr_tgpr(env); } - if (unlikely((value ^ env->msr) & R_MSR_EP_MASK)) { - env->excp_prefix =3D FIELD_EX64(value, MSR, EP) * 0xFFF00000; + /* PPE42 uses IR, DR and EP MSR bits for other purposes */ + if (likely(!(env->flags & POWERPC_FLAG_PPE42))) { + if ((value ^ env->msr) & (R_MSR_IR_MASK | R_MSR_DR_MASK)) { + cpu_interrupt_exittb(cs); + } + if (unlikely((value ^ env->msr) & R_MSR_EP_MASK)) { + env->excp_prefix =3D FIELD_EX64(value, MSR, EP) * 0xFFF00000; + } } /* * If PR=3D1 then EE, IR and DR must be 1 @@ -464,6 +467,23 @@ void register_generic_sprs(PowerPCCPU *cpu) SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); + + spr_register(env, SPR_PVR, "PVR", + /* Linux permits userspace to read PVR */ +#if defined(CONFIG_LINUX_USER) + &spr_read_generic, +#else + SPR_NOACCESS, +#endif + SPR_NOACCESS, + &spr_read_generic, SPR_NOACCESS, + pcc->pvr); + + /* PPE42 doesn't support SPRG1-3, SVR or TB regs */ + if (env->insns_flags2 & PPC2_PPE42) { + return; + } + spr_register(env, SPR_SPRG1, "SPRG1", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, @@ -477,17 +497,6 @@ void register_generic_sprs(PowerPCCPU *cpu) &spr_read_generic, &spr_write_generic, 0x00000000); =20 - spr_register(env, SPR_PVR, "PVR", - /* Linux permits userspace to read PVR */ -#if defined(CONFIG_LINUX_USER) - &spr_read_generic, -#else - SPR_NOACCESS, -#endif - SPR_NOACCESS, - &spr_read_generic, SPR_NOACCESS, - pcc->pvr); - /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE= */ if (pcc->svr !=3D POWERPC_SVR_NONE) { if (pcc->svr & POWERPC_SVR_E500) { diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 27f90c3cc5..fc817dab54 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -4264,8 +4264,10 @@ static void gen_mtmsr(DisasContext *ctx) /* L=3D1 form only updates EE and RI */ mask &=3D (1ULL << MSR_RI) | (1ULL << MSR_EE); } else { - /* mtmsr does not alter S, ME, or LE */ - mask &=3D ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S)); + if (likely(!(ctx->insns_flags2 & PPC2_PPE42))) { + /* mtmsr does not alter S, ME, or LE */ + mask &=3D ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR= _S)); + } =20 /* * XXX: we need to update nip before the store if we enter --=20 2.43.0