From nobody Sun Sep 28 16:34:28 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1758698913; cv=none; d=zohomail.com; s=zohoarc; b=NqaPir8U5B1PIyCqx7H6mjCPsSILqCG5ZlQUEEp04s/uR4NijKsagFXmJiTlzHNLAR2yCAfEDew31Trg0JT3KnY2WQAGAZ2Ytty9g2mSY8lXTSYrYA0ly2F6o5WKDtZMoD4KU5wLh4LawKjuO6SqnjyKE6/6QYduyp6ACXk3Uwo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758698913; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=Y8Je5iZVgc2ycYZL2Dvu1grRMVwIH4xKSbz9INjaPno=; b=fKdIOt3tqaSbqROP+iwfPWbNNXWMcgAifrvrzaJucRotuXiJkt94Xon/rHhke3+tKyBvuGtDWWt3AxaMMGa9Bo3dcQLAbSEslEorADpjUjR2V+IIBqwTB9dPNrbYgd4kQkVwggLE69SkQxLY/8NZ9fOw+IhS3jq50c/Pd8JPEA4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17586989136411006.6133168664456; Wed, 24 Sep 2025 00:28:33 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v1Jn6-0005SX-BF; Wed, 24 Sep 2025 03:19:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v1Jn1-0005Pa-Dr for qemu-devel@nongnu.org; Wed, 24 Sep 2025 03:19:47 -0400 Received: from rev.ng ([94.130.142.21]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v1Jms-0003Om-8S for qemu-devel@nongnu.org; Wed, 24 Sep 2025 03:19:47 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive:List-Unsubscribe:List-Unsubscribe-Post: List-Help; bh=Y8Je5iZVgc2ycYZL2Dvu1grRMVwIH4xKSbz9INjaPno=; b=AZF4YpIauyDZuXF oqZI2MHtpbE8YA7PpfQ9CJ/FUlk5LkTNdxpoqvk1YTbVzdhc/3mkd48nUAcPU7lQmedXywSTr+6nh s/uaF9kPlzlQOzPcOCA9YUq9hk7DkFCK2AMdZ0V86md0xp8ZfD6VQ5wEcAeJ0szMMNXujbGaw9RCf /Y=; To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org, alistair.francis@wdc.com, palmer@dabbelt.com Subject: [RFC PATCH 08/34] target/riscv: Combine minstretcfg and minstretcfgh Date: Wed, 24 Sep 2025 09:20:58 +0200 Message-ID: <20250924072124.6493-9-anjo@rev.ng> In-Reply-To: <20250924072124.6493-1-anjo@rev.ng> References: <20250924072124.6493-1-anjo@rev.ng> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1758698915674116600 Content-Type: text/plain; charset="utf-8" According to version 20250508 of the privileged specification, minstretcfg is a 64-bit register and minstretcfgh refers to the top 32 bits of this register when XLEN =3D=3D 32. No real advantage is gained by keeping them separate, and combining them allows for slight simplification. Signed-off-by: Anton Johansson --- target/riscv/cpu.h | 3 +-- target/riscv/csr.c | 18 ++++++++++-------- 2 files changed, 11 insertions(+), 10 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 4b80daf117..81719813cf 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -420,8 +420,7 @@ struct CPUArchState { =20 /* PMU cycle & instret privilege mode filtering */ uint64_t mcyclecfg; - target_ulong minstretcfg; - target_ulong minstretcfgh; + uint64_t minstretcfg; =20 /* PMU counter state */ PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS]; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 867f8efe83..4d232b062b 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1116,7 +1116,8 @@ static RISCVException write_mcyclecfgh(CPURISCVState = *env, int csrno, static RISCVException read_minstretcfg(CPURISCVState *env, int csrno, target_ulong *val) { - *val =3D env->minstretcfg; + bool rv32 =3D riscv_cpu_mxl(env) =3D=3D MXL_RV32; + *val =3D extract64(env->minstretcfg, 0, rv32 ? 32 : 64); return RISCV_EXCP_NONE; } =20 @@ -1143,7 +1144,7 @@ static RISCVException write_minstretcfg(CPURISCVState= *env, int csrno, static RISCVException read_minstretcfgh(CPURISCVState *env, int csrno, target_ulong *val) { - *val =3D env->minstretcfgh; + *val =3D extract64(env->minstretcfg, 32, 32); return RISCV_EXCP_NONE; } =20 @@ -1160,7 +1161,8 @@ static RISCVException write_minstretcfgh(CPURISCVStat= e *env, int csrno, inh_avail_mask |=3D (riscv_has_ext(env, RVH) && riscv_has_ext(env, RVS)) ? MINSTRETCFGH_BIT_VSINH := 0; =20 - env->minstretcfgh =3D val & inh_avail_mask; + env->minstretcfg =3D deposit64(env->minstretcfg, 32, 32, + val & inh_avail_mask); return RISCV_EXCP_NONE; } =20 @@ -1250,8 +1252,7 @@ static target_ulong riscv_pmu_ctr_get_fixed_counters_= val(CPURISCVState *env, if (counter_idx =3D=3D 0) { cfg_val =3D env->mcyclecfg; } else if (counter_idx =3D=3D 2) { - cfg_val =3D rv32 ? ((uint64_t)env->minstretcfgh << 32) : - env->minstretcfg; + cfg_val =3D env->minstretcfg; } else { cfg_val =3D env->mhpmevent_val[counter_idx]; cfg_val &=3D MHPMEVENT_FILTER_MASK; @@ -1573,12 +1574,13 @@ static int rmw_cd_ctr_cfgh(CPURISCVState *env, int = cfg_index, target_ulong *val, } break; case 2: /* INSTRETCFGH */ + cfgh =3D extract64(env->minstretcfg, 32, 32); if (wr_mask) { wr_mask &=3D ~MINSTRETCFGH_BIT_MINH; - env->minstretcfgh =3D (new_val & wr_mask) | - (env->minstretcfgh & ~wr_mask); + cfgh =3D (new_val & wr_mask) | (cfgh & ~wr_mask); + env->minstretcfg =3D deposit64(env->minstretcfg, 32, 32, cfgh); } else { - *val =3D env->minstretcfgh; + *val =3D cfgh; } break; default: --=20 2.51.0