From nobody Sun Sep 28 16:34:18 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1758698941; cv=none; d=zohomail.com; s=zohoarc; b=AZ6ETxDPeEzTgOuO1VV51eA4242g5Vt2ZbB8sNfXx8NQvodl6MJkOU5LN8uxknT7nwZd8A8qTZLVPG57palLBGE4mLGv1LXz/Dm4m0Ei2mJLoTeLs2LdRtF0AV5xWbAAiFrb+iynsC7jw+Zx18ylkKH7F0s97Gd6Kz29a+pW6oA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758698941; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=peqAyKMiYbZr6gvwaAolHm42N25xiC9f2kDM2S0sjp4=; b=OqHI52h141eeeiknoBW4/NtOFC/Iuys+81hi9W6yd/dgIPXz3cPzK+cUK3P/qMGwZK6bLl/LyTf5Ope/KkmMLP8ctky4UHlWKxuRHVUnTzu0BdeW6L5mzZuTU/s2KkFpzoOPyikxZ/gOX1lWkfXe3G7lNDSE7lfBR2MQIoPcyyA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1758698941951908.2206765432959; Wed, 24 Sep 2025 00:29:01 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v1Jnl-0005r1-O6; Wed, 24 Sep 2025 03:20:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v1JnZ-0005lT-La for qemu-devel@nongnu.org; Wed, 24 Sep 2025 03:20:23 -0400 Received: from rev.ng ([94.130.142.21]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v1JnR-0003Sm-5V for qemu-devel@nongnu.org; Wed, 24 Sep 2025 03:20:17 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive:List-Unsubscribe:List-Unsubscribe-Post: List-Help; bh=peqAyKMiYbZr6gvwaAolHm42N25xiC9f2kDM2S0sjp4=; b=TkANn3PfKH9PfnJ uD8R0Ql06IuSYoJ5ohLmbfwFxNPQMpJuXWxiXV7GDAESWklKqLy642ttBdvMx5zASuh7agRc/cPdU d385sq//NHWRQBUhZonbRzcZGZWrGyRxCXGYSBPrsFJmAW8sCOwgYMmFLFSUtJ3LnOtFAenC2fhlo KM=; To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org, alistair.francis@wdc.com, palmer@dabbelt.com Subject: [RFC PATCH 24/34] target/riscv: Fix arguments to board IMSIC emulation callbacks Date: Wed, 24 Sep 2025 09:21:14 +0200 Message-ID: <20250924072124.6493-25-anjo@rev.ng> In-Reply-To: <20250924072124.6493-1-anjo@rev.ng> References: <20250924072124.6493-1-anjo@rev.ng> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1758698944183116600 Content-Type: text/plain; charset="utf-8" In hw/ the relevant RISCVIMSICState fields eidelivery, eithreshold, eistate are uint32_t. Signed-off-by: Anton Johansson --- target/riscv/cpu.h | 42 ++++++++++++++++++++------------------- hw/intc/riscv_imsic.c | 34 +++++++++++++++---------------- target/riscv/cpu_helper.c | 12 ++++------- target/riscv/csr.c | 24 ++++++++++++---------- 4 files changed, 57 insertions(+), 55 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 8ca01764fa..b8e62a13eb 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -193,6 +193,24 @@ FIELD(VTYPE, VMA, 7, 1) FIELD(VTYPE, VEDIV, 8, 2) FIELD(VTYPE, RESERVED, 10, sizeof(uint64_t) * 8 - 11) =20 +#ifndef CONFIG_USER_ONLY +/* machine specific AIA ireg read-modify-write callback */ +#define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) = \ + ((uint32_t)((((__xlen) & 0xff) << 24) | = \ + (((__vgein) & 0x3f) << 20) | = \ + (((__virt) & 0x1) << 18) | = \ + (((__priv) & 0x3) << 16) | = \ + (__isel & 0xffff))) +#define AIA_IREG_ISEL(__ireg) ((__ireg) & 0xffff) +#define AIA_IREG_PRIV(__ireg) (((__ireg) >> 16) & 0x3) +#define AIA_IREG_VIRT(__ireg) (((__ireg) >> 18) & 0x1) +#define AIA_IREG_VGEIN(__ireg) (((__ireg) >> 20) & 0x3f) +#define AIA_IREG_XLEN(__ireg) (((__ireg) >> 24) & 0xff) + +typedef int aia_ireg_rmw_fn(void *arg, uint32_t reg, uint64_t *val, + uint64_t new_val, uint64_t write_mask); +#endif + typedef struct PMUCTRState { /* Current value of a counter */ uint64_t mhpmcounter_val; @@ -458,20 +476,8 @@ struct CPUArchState { void *rdtime_fn_arg; =20 /* machine specific AIA ireg read-modify-write callback */ -#define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \ - ((((__xlen) & 0xff) << 24) | \ - (((__vgein) & 0x3f) << 20) | \ - (((__virt) & 0x1) << 18) | \ - (((__priv) & 0x3) << 16) | \ - (__isel & 0xffff)) -#define AIA_IREG_ISEL(__ireg) ((__ireg) & 0xffff) -#define AIA_IREG_PRIV(__ireg) (((__ireg) >> 16) & 0x3) -#define AIA_IREG_VIRT(__ireg) (((__ireg) >> 18) & 0x1) -#define AIA_IREG_VGEIN(__ireg) (((__ireg) >> 20) & 0x3f) -#define AIA_IREG_XLEN(__ireg) (((__ireg) >> 24) & 0xff) - int (*aia_ireg_rmw_fn[4])(void *arg, target_ulong reg, - target_ulong *val, target_ulong new_val, target_ulong write_mask); - void *aia_ireg_rmw_fn_arg[4]; + aia_ireg_rmw_fn *aia_ireg_rmw_cb[4]; + void *aia_ireg_rmw_cb_arg[4]; =20 /* True if in debugger mode. */ bool debugger; @@ -638,12 +644,8 @@ void riscv_cpu_interrupt(CPURISCVState *env); #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value = */ void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), void *arg); -void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, - int (*rmw_fn)(void *arg, - target_ulong reg, - target_ulong *val, - target_ulong new_val, - target_ulong write_mask), +void riscv_cpu_set_aia_ireg_rmw_cb(CPURISCVState *env, uint32_t priv, + aia_ireg_rmw_fn *rmw_fn, void *rmw_fn_arg); =20 RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bi= t); diff --git a/hw/intc/riscv_imsic.c b/hw/intc/riscv_imsic.c index 6174e1a05d..9274a1e842 100644 --- a/hw/intc/riscv_imsic.c +++ b/hw/intc/riscv_imsic.c @@ -88,11 +88,11 @@ static void riscv_imsic_update(RISCVIMSICState *imsic, = uint32_t page) } =20 static int riscv_imsic_eidelivery_rmw(RISCVIMSICState *imsic, uint32_t pag= e, - target_ulong *val, - target_ulong new_val, - target_ulong wr_mask) + uint64_t *val, + uint64_t new_val, + uint64_t wr_mask) { - target_ulong old_val =3D imsic->eidelivery[page]; + uint32_t old_val =3D imsic->eidelivery[page]; =20 if (val) { *val =3D old_val; @@ -106,11 +106,11 @@ static int riscv_imsic_eidelivery_rmw(RISCVIMSICState= *imsic, uint32_t page, } =20 static int riscv_imsic_eithreshold_rmw(RISCVIMSICState *imsic, uint32_t pa= ge, - target_ulong *val, - target_ulong new_val, - target_ulong wr_mask) + uint64_t *val, + uint64_t new_val, + uint64_t wr_mask) { - target_ulong old_val =3D imsic->eithreshold[page]; + uint32_t old_val =3D imsic->eithreshold[page]; =20 if (val) { *val =3D old_val; @@ -124,8 +124,8 @@ static int riscv_imsic_eithreshold_rmw(RISCVIMSICState = *imsic, uint32_t page, } =20 static int riscv_imsic_topei_rmw(RISCVIMSICState *imsic, uint32_t page, - target_ulong *val, target_ulong new_val, - target_ulong wr_mask) + uint64_t *val, uint64_t new_val, + uint64_t wr_mask) { uint32_t base, topei =3D riscv_imsic_topei(imsic, page); =20 @@ -149,11 +149,11 @@ static int riscv_imsic_topei_rmw(RISCVIMSICState *ims= ic, uint32_t page, =20 static int riscv_imsic_eix_rmw(RISCVIMSICState *imsic, uint32_t xlen, uint32_t page, - uint32_t num, bool pend, target_ulong *val, - target_ulong new_val, target_ulong wr_mask) + uint32_t num, bool pend, uint64_t *val, + uint64_t new_val, uint64_t wr_mask) { uint32_t i, base, prev; - target_ulong mask; + uint64_t mask; uint32_t state =3D (pend) ? IMSIC_EISTATE_PENDING : IMSIC_EISTATE_ENAB= LED; =20 if (xlen !=3D 32) { @@ -178,7 +178,7 @@ static int riscv_imsic_eix_rmw(RISCVIMSICState *imsic, continue; } =20 - mask =3D (target_ulong)1 << i; + mask =3D 1ull << i; if (wr_mask & mask) { if (new_val & mask) { prev =3D qatomic_fetch_or(&imsic->eistate[base + i], state= ); @@ -197,8 +197,8 @@ static int riscv_imsic_eix_rmw(RISCVIMSICState *imsic, return 0; } =20 -static int riscv_imsic_rmw(void *arg, target_ulong reg, target_ulong *val, - target_ulong new_val, target_ulong wr_mask) +static int riscv_imsic_rmw(void *arg, uint32_t reg, uint64_t *val, + uint64_t new_val, uint64_t wr_mask) { RISCVIMSICState *imsic =3D arg; uint32_t isel, priv, virt, vgein, xlen, page; @@ -383,7 +383,7 @@ static void riscv_imsic_realize(DeviceState *dev, Error= **errp) } =20 if (!kvm_irqchip_in_kernel()) { - riscv_cpu_set_aia_ireg_rmw_fn(env, (imsic->mmode) ? PRV_M : PR= V_S, + riscv_cpu_set_aia_ireg_rmw_cb(env, (imsic->mmode) ? PRV_M : PR= V_S, riscv_imsic_rmw, imsic); } } diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index c5e94359e4..2945a89a9c 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -766,17 +766,13 @@ void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint= 64_t (*fn)(void *), env->rdtime_fn_arg =3D arg; } =20 -void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, - int (*rmw_fn)(void *arg, - target_ulong reg, - target_ulong *val, - target_ulong new_val, - target_ulong write_mask), +void riscv_cpu_set_aia_ireg_rmw_cb(CPURISCVState *env, uint32_t priv, + aia_ireg_rmw_fn *rmw_fn, void *rmw_fn_arg) { if (priv <=3D PRV_M) { - env->aia_ireg_rmw_fn[priv] =3D rmw_fn; - env->aia_ireg_rmw_fn_arg[priv] =3D rmw_fn_arg; + env->aia_ireg_rmw_cb[priv] =3D rmw_fn; + env->aia_ireg_rmw_cb_arg[priv] =3D rmw_fn_arg; } } =20 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 5db6780b2d..f73dfbe78b 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -2635,6 +2635,7 @@ static RISCVException rmw_xireg_aia(CPURISCVState *en= v, int csrno, int ret =3D -EINVAL; uint8_t *iprio; target_ulong priv, vgein; + uint64_t wide_val; =20 /* VS-mode CSR number passed in has already been translated */ switch (csrno) { @@ -2679,16 +2680,17 @@ static RISCVException rmw_xireg_aia(CPURISCVState *= env, int csrno, } } else if (ISELECT_IMSIC_FIRST <=3D isel && isel <=3D ISELECT_IMSIC_LA= ST) { /* IMSIC registers only available when machine implements it. */ - if (env->aia_ireg_rmw_fn[priv]) { + if (env->aia_ireg_rmw_cb[priv]) { /* Selected guest interrupt file should not be zero */ if (virt && (!vgein || env->geilen < vgein)) { goto done; } /* Call machine specific IMSIC register emulation */ - ret =3D env->aia_ireg_rmw_fn[priv](env->aia_ireg_rmw_fn_arg[pr= iv], + ret =3D env->aia_ireg_rmw_cb[priv](env->aia_ireg_rmw_cb_arg[pr= iv], AIA_MAKE_IREG(isel, priv, virt, vgein, riscv_cpu_mxl_bits(env)), - val, new_val, wr_mask); + &wide_val, new_val, wr_mask); + *val =3D wide_val; } } else { isel_reserved =3D true; @@ -2920,6 +2922,7 @@ static RISCVException rmw_xtopei(CPURISCVState *env, = int csrno, bool virt; int ret =3D -EINVAL; target_ulong priv, vgein; + uint64_t wide_val; =20 /* Translate CSR number for VS-mode */ csrno =3D aia_xlate_vs_csrno(env, csrno); @@ -2945,7 +2948,7 @@ static RISCVException rmw_xtopei(CPURISCVState *env, = int csrno, }; =20 /* IMSIC CSRs only available when machine implements IMSIC. */ - if (!env->aia_ireg_rmw_fn[priv]) { + if (!env->aia_ireg_rmw_cb[priv]) { goto done; } =20 @@ -2958,10 +2961,11 @@ static RISCVException rmw_xtopei(CPURISCVState *env= , int csrno, } =20 /* Call machine specific IMSIC register emulation for TOPEI */ - ret =3D env->aia_ireg_rmw_fn[priv](env->aia_ireg_rmw_fn_arg[priv], + ret =3D env->aia_ireg_rmw_cb[priv](env->aia_ireg_rmw_cb_arg[priv], AIA_MAKE_IREG(ISELECT_IMSIC_TOPEI, priv, virt, vgein, riscv_cpu_mxl_bits(env)), - val, new_val, wr_mask); + &wide_val, new_val, wr_mask); + *val =3D wide_val; =20 done: if (ret) { @@ -4426,7 +4430,7 @@ static RISCVException read_vstopi(CPURISCVState *env,= int csrno, target_ulong *val) { int irq, ret; - target_ulong topei; + uint64_t topei =3D 0; uint64_t vseip, vsgein; uint32_t iid, iprio, hviid, hviprio, gein; uint32_t s, scount =3D 0, siid[VSTOPI_NUM_SRCS], siprio[VSTOPI_NUM_SRC= S]; @@ -4441,13 +4445,13 @@ static RISCVException read_vstopi(CPURISCVState *en= v, int csrno, if (gein <=3D env->geilen && vseip) { siid[scount] =3D IRQ_S_EXT; siprio[scount] =3D IPRIO_MMAXIPRIO + 1; - if (env->aia_ireg_rmw_fn[PRV_S]) { + if (env->aia_ireg_rmw_cb[PRV_S]) { /* * Call machine specific IMSIC register emulation for * reading TOPEI. */ - ret =3D env->aia_ireg_rmw_fn[PRV_S]( - env->aia_ireg_rmw_fn_arg[PRV_S], + ret =3D env->aia_ireg_rmw_cb[PRV_S]( + env->aia_ireg_rmw_cb_arg[PRV_S], AIA_MAKE_IREG(ISELECT_IMSIC_TOPEI, PRV_S, true, ge= in, riscv_cpu_mxl_bits(env)), &topei, 0, 0); --=20 2.51.0