From nobody Sun Sep 28 16:34:26 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1758698447; cv=none; d=zohomail.com; s=zohoarc; b=IxdWPh0MbX6andVUlpH7P6WuZRdf9ppEBENR4d8uZMvX+29URnBuT9CnNwDRMkBT/HyRDDGjlabgy/6jMdBdhFP77gvtjaeQYSL0HOIt2fQm7O6DM0yPRnnHzwkQhb35RKNLZdS7o2qwHuFxczvTcYB2Uk3iAgJIM+rvolrkRgA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758698447; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=2f/lUpVBkdTZv4p6T5HNNfSKogg0M/xXuw7EwsQX/C8=; b=edvwMcWsUrg54ZnjRvygETvH3DIijj6LqHOqYN5Ahg7DuRmPMad8T7fcrkQvLaRbUBh12CmakoOjo9fuPwhg1LVm2KlOQvasYUfsK8x+ydhsjGsQdRVP+nmFAhbqqGIGYg+3k3qVn5Ma3VnMN/FsxbhOOphQORI6fhNj5h75cPU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1758698446973670.409187128985; Wed, 24 Sep 2025 00:20:46 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v1JnF-0005WZ-OP; Wed, 24 Sep 2025 03:20:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v1JnE-0005Vi-0m for qemu-devel@nongnu.org; Wed, 24 Sep 2025 03:20:00 -0400 Received: from rev.ng ([94.130.142.21]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v1Jn8-0003PT-9L for qemu-devel@nongnu.org; Wed, 24 Sep 2025 03:19:59 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive:List-Unsubscribe:List-Unsubscribe-Post: List-Help; bh=2f/lUpVBkdTZv4p6T5HNNfSKogg0M/xXuw7EwsQX/C8=; b=fcSSra2me5NCHi+ 1r8uT5kqx2LQg4iVokwqPeHnT9XBZzj/N4lXR2WZ/a4Y4BEaHayL7Y+8v0dH1OQ3ZkNARs/NZkSYs 1YJY+HwHWimSXLv8gCmpA8RHD8btWKlwClGhj3uQ6BVjDweMkjl1xpqq/OOECsVIJO5ORf4UTB+6v +c=; To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org, alistair.francis@wdc.com, palmer@dabbelt.com Subject: [RFC PATCH 11/34] target/riscv: Fix size of vector CSRs Date: Wed, 24 Sep 2025 09:21:01 +0200 Message-ID: <20250924072124.6493-12-anjo@rev.ng> In-Reply-To: <20250924072124.6493-1-anjo@rev.ng> References: <20250924072124.6493-1-anjo@rev.ng> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1758698448904116600 Content-Type: text/plain; charset="utf-8" According to version 20250508 of the unprivileged specification: - vtype: bits 0..7 used, bit XLEN-1 illegal, rest reserved =3D> fix to 64-bits. - vxsat: bit 0 used, vxrm which would occupy bits 1..2 is stored separately, and bits 3..31 are set to 0 =3D> fix to 8-bits. - vxrm: 2 lowest bits are used for rounding mode, rest set to 0 =3D> fix to 8-bits. - vstart: maximum value of VLMAX-1, where VLMAX is at most 2^16 =3D> fix to 32-bits as vstart is mapped to a TCG global. - vl: maximum value of VLEN which is at most 2^16 =3D> fix to 32-bits as vl is mapped to a TCG global. Fields are shuffled for reduced padding. Signed-off-by: Anton Johansson --- target/riscv/cpu.h | 12 ++++++------ target/riscv/machine.c | 10 +++++----- target/riscv/translate.c | 12 ++++++++---- target/riscv/vector_helper.c | 22 ++++++++++++++++++---- target/riscv/insn_trans/trans_rvv.c.inc | 22 +++++++++++----------- 5 files changed, 48 insertions(+), 30 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 2cd69fa150..8f844405bd 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -191,7 +191,7 @@ FIELD(VTYPE, VSEW, 3, 3) FIELD(VTYPE, VTA, 6, 1) FIELD(VTYPE, VMA, 7, 1) FIELD(VTYPE, VEDIV, 8, 2) -FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) +FIELD(VTYPE, RESERVED, 10, sizeof(uint64_t) * 8 - 11) =20 typedef struct PMUCTRState { /* Current value of a counter */ @@ -217,11 +217,11 @@ struct CPUArchState { =20 /* vector coprocessor state. */ uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); - target_ulong vxrm; - target_ulong vxsat; - target_ulong vl; - target_ulong vstart; - target_ulong vtype; + uint64_t vtype; + uint32_t vl; + uint32_t vstart; + uint8_t vxrm; + uint8_t vxsat; bool vill; =20 target_ulong pc; diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 9a14a805ef..8e3062aabb 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -141,11 +141,11 @@ static const VMStateDescription vmstate_vector =3D { .needed =3D vector_needed, .fields =3D (const VMStateField[]) { VMSTATE_UINT64_ARRAY(env.vreg, RISCVCPU, 32 * RV_VLEN_MAX / 64), - VMSTATE_UINTTL(env.vxrm, RISCVCPU), - VMSTATE_UINTTL(env.vxsat, RISCVCPU), - VMSTATE_UINTTL(env.vl, RISCVCPU), - VMSTATE_UINTTL(env.vstart, RISCVCPU), - VMSTATE_UINTTL(env.vtype, RISCVCPU), + VMSTATE_UINT8(env.vxrm, RISCVCPU), + VMSTATE_UINT8(env.vxsat, RISCVCPU), + VMSTATE_UINT32(env.vl, RISCVCPU), + VMSTATE_UINT32(env.vstart, RISCVCPU), + VMSTATE_UINT64(env.vtype, RISCVCPU), VMSTATE_BOOL(env.vill, RISCVCPU), VMSTATE_END_OF_LIST() } diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 2f8c7a6465..5e8fc3e543 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -38,8 +38,9 @@ #include "tcg/tcg-cpu.h" =20 /* global register indices */ -static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart; +static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc; static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ +static TCGv_i32 cpu_vl, cpu_vstart; static TCGv load_res; static TCGv load_val; =20 @@ -1439,6 +1440,10 @@ void riscv_translate_init(void) size_t field_offset =3D 0; #endif =20 + /* 32 bits in size, no offset needed */ + size_t vl_offset =3D offsetof(CPURISCVState, vl); + size_t vstart_offset =3D offsetof(CPURISCVState, vstart); + for (i =3D 1; i < 32; i++) { cpu_gpr[i] =3D tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, gpr[i]) + field_offset, @@ -1454,9 +1459,8 @@ void riscv_translate_init(void) } =20 cpu_pc =3D tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, pc), "p= c"); - cpu_vl =3D tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, vl), "v= l"); - cpu_vstart =3D tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, vst= art), - "vstart"); + cpu_vl =3D tcg_global_mem_new_i32(tcg_env, vl_offset, "vl"); + cpu_vstart =3D tcg_global_mem_new_i32(tcg_env, vstart_offset, "vstart"= ); load_res =3D tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, load_= res), "load_res"); load_val =3D tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, load_= val), diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 7c67d67a13..2fc5348044 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -360,6 +360,12 @@ vext_page_ldst_us(CPURISCVState *env, void *vd, target= _ulong addr, uint32_t evl =3D env->vstart + elems; MMUAccessType access_type =3D is_load ? MMU_DATA_LOAD : MMU_DATA_STORE; =20 + /* + * Maximum vector length is VLMAX =3D=3D 2^16 =3D=3D LMUL * VL / SEW, = and + * occurs for LMUL =3D=3D 8, SEW =3D=3D 8, VL =3D=3D 2^16. + */ + g_assert(env->vstart < UINT16_MAX && UINT16_MAX - env->vstart >=3D ele= ms); + /* Check page permission/pmp/watchpoint/etc. */ probe_pages(env, addr, size, ra, access_type, mmu_index, &host, &flags, true); @@ -2594,19 +2600,27 @@ static inline uint8_t get_round(int vxrm, uint64_t = v, uint8_t shift) =20 d1 =3D extract64(v, shift - 1, 1); D1 =3D extract64(v, 0, shift); - if (vxrm =3D=3D 0) { /* round-to-nearest-up (add +0.5 LSB) */ + switch (vxrm) { + case 0: + /* round-to-nearest-up (add +0.5 LSB) */ return d1; - } else if (vxrm =3D=3D 1) { /* round-to-nearest-even */ + case 1: + /* round-to-nearest-even */ if (shift > 1) { D2 =3D extract64(v, 0, shift - 1); return d1 & ((D2 !=3D 0) | d); } else { return d1 & d; } - } else if (vxrm =3D=3D 3) { /* round-to-odd (OR bits into LSB, aka "ja= m") */ + case 2: + /* round-down (truncate) */ + return 0; + case 3: + /* round-to-odd (OR bits into LSB, aka "jam") */ return !d & (D1 !=3D 0); + default: + g_assert_not_reached(); } - return 0; /* round-down (truncate) */ } =20 static inline int32_t aadd32(CPURISCVState *env, int vxrm, int32_t a, diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index 71f98fb350..f1b624922a 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -194,7 +194,7 @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1,= TCGv s2) =20 if (rd =3D=3D 0 && rs1 =3D=3D 0) { s1 =3D tcg_temp_new(); - tcg_gen_mov_tl(s1, cpu_vl); + tcg_gen_ext_i32_tl(s1, cpu_vl); } else if (rs1 =3D=3D 0) { /* As the mask is at least one bit, RV_VLEN_MAX is >=3D VLMAX */ s1 =3D tcg_constant_tl(RV_VLEN_MAX); @@ -1213,9 +1213,9 @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs= 1, uint32_t nf, MO_LE | MO_64 | atomicity); } if (i =3D=3D size - 8) { - tcg_gen_movi_tl(cpu_vstart, 0); + tcg_gen_movi_i32(cpu_vstart, 0); } else { - tcg_gen_addi_tl(cpu_vstart, cpu_vstart, 8 >> log2_esz); + tcg_gen_addi_i32(cpu_vstart, cpu_vstart, 8 >> log2_esz= ); } } } else { @@ -1231,9 +1231,9 @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs= 1, uint32_t nf, MO_LE | MO_32 | atomicity); } if (i =3D=3D size - 4) { - tcg_gen_movi_tl(cpu_vstart, 0); + tcg_gen_movi_i32(cpu_vstart, 0); } else { - tcg_gen_addi_tl(cpu_vstart, cpu_vstart, 4 >> log2_esz); + tcg_gen_addi_i32(cpu_vstart, cpu_vstart, 4 >> log2_esz= ); } } } @@ -3459,7 +3459,7 @@ static bool trans_vmv_x_s(DisasContext *s, arg_vmv_x_= s *a) vec_element_loadi(s, t1, a->rs2, 0, true); tcg_gen_trunc_i64_tl(dest, t1); gen_set_gpr(s, a->rd, dest); - tcg_gen_movi_tl(cpu_vstart, 0); + tcg_gen_movi_i32(cpu_vstart, 0); finalize_rvv_inst(s); return true; } @@ -3476,7 +3476,7 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_= x *a) TCGv s1; TCGLabel *over =3D gen_new_label(); =20 - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); + tcg_gen_brcond_i32(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 t1 =3D tcg_temp_new_i64(); =20 @@ -3488,7 +3488,7 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_= x *a) tcg_gen_ext_tl_i64(t1, s1); vec_element_storei(s, a->rd, 0, t1); gen_set_label(over); - tcg_gen_movi_tl(cpu_vstart, 0); + tcg_gen_movi_i32(cpu_vstart, 0); finalize_rvv_inst(s); return true; } @@ -3516,7 +3516,7 @@ static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_= f_s *a) } =20 mark_fs_dirty(s); - tcg_gen_movi_tl(cpu_vstart, 0); + tcg_gen_movi_i32(cpu_vstart, 0); finalize_rvv_inst(s); return true; } @@ -3536,7 +3536,7 @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_= s_f *a) TCGLabel *over =3D gen_new_label(); =20 /* if vstart >=3D vl, skip vector register write back */ - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); + tcg_gen_brcond_i32(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 /* NaN-box f[rs1] */ t1 =3D tcg_temp_new_i64(); @@ -3545,7 +3545,7 @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_= s_f *a) vec_element_storei(s, a->rd, 0, t1); =20 gen_set_label(over); - tcg_gen_movi_tl(cpu_vstart, 0); + tcg_gen_movi_i32(cpu_vstart, 0); finalize_rvv_inst(s); return true; } --=20 2.51.0