From nobody Sun Sep 28 16:34:29 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1758698444; cv=none; d=zohomail.com; s=zohoarc; b=a0WjY0p7d2CXhQeqUDwy7YlaA2RSjYziCvyI6ZHnXLzqiHVo8UztFomMDAAxlnJSIXNAoBB7m02jZEewO8aHVbxSOTwT6w+ejt7/UHvMeiYDvB198M0dbThKgCHY28hfK+2eorSD5IuVp9HUphSR/qfSLW/HPd2BIPrCG4vwvmo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758698444; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=gv/vATm5ZZPYeNw35feJwyefhLISJPLo9ephGqNgcYs=; b=My0Gdn4dxM6XS+5QyS7Y4q3U04Vk6znWTojklns0QMClwdGlBmJs5j4CyTy9GQWwxLedefW8ZsdeZuqMdz7zvr6vKbZ0p6QT0gxxzm8712Zu/ySu1f+PwUiC2wI6BDc49x87MGTes346OG2xvaug/dxDve/5rS0/VRANSwh5nHg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1758698444348293.6802975427447; Wed, 24 Sep 2025 00:20:44 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v1Jn9-0005Tt-F2; Wed, 24 Sep 2025 03:19:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v1Jn6-0005SZ-Ub for qemu-devel@nongnu.org; Wed, 24 Sep 2025 03:19:52 -0400 Received: from rev.ng ([94.130.142.21]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v1Jms-0003Oz-90 for qemu-devel@nongnu.org; Wed, 24 Sep 2025 03:19:51 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive:List-Unsubscribe:List-Unsubscribe-Post: List-Help; bh=gv/vATm5ZZPYeNw35feJwyefhLISJPLo9ephGqNgcYs=; b=wdWuM2Z6BIDnfLY Y4jdamVHHU+gj+eGLggmSsqRQG+7VzaYt9UnCvayLGQ1v6mzbtrFr6byAdHo0VTrw4QOIZjj2it/P /7GZO5FM3jb82iG+6IKVLYmAguovfRA9ue1TQM7QQKIpxdr0Z9ttsIONn2h3EAlCsRjX+sfkPnTTc cI=; To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org, alistair.francis@wdc.com, palmer@dabbelt.com Subject: [RFC PATCH 09/34] target/riscv: Combine mhpmcounter and mhpmcounterh Date: Wed, 24 Sep 2025 09:20:59 +0200 Message-ID: <20250924072124.6493-10-anjo@rev.ng> In-Reply-To: <20250924072124.6493-1-anjo@rev.ng> References: <20250924072124.6493-1-anjo@rev.ng> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1758698446567116600 Content-Type: text/plain; charset="utf-8" According to version 20250508 of the privileged specification, mhpmconter is a 64-bit register and mhpmcounterh refers to the top 32 bits of this register when XLEN =3D=3D 32. No real advantage is gained by keeping them separate, and combining allows for slight simplification. Signed-off-by: Anton Johansson --- target/riscv/cpu.h | 8 +-- target/riscv/csr.c | 74 +++++++++++++-------------- target/riscv/machine.c | 6 +-- target/riscv/pmu.c | 111 +++++++++++------------------------------ 4 files changed, 68 insertions(+), 131 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 81719813cf..b0d6e74ea3 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -195,13 +195,9 @@ FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - = 11) =20 typedef struct PMUCTRState { /* Current value of a counter */ - target_ulong mhpmcounter_val; - /* Current value of a counter in RV32 */ - target_ulong mhpmcounterh_val; + uint64_t mhpmcounter_val; /* Snapshot values of counter */ - target_ulong mhpmcounter_prev; - /* Snapshort value of a counter in RV32 */ - target_ulong mhpmcounterh_prev; + uint64_t mhpmcounter_prev; /* Value beyond UINT32_MAX/UINT64_MAX before overflow interrupt trigge= r */ target_ulong irq_overflow_left; } PMUCTRState; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 4d232b062b..f29a3c9991 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1299,24 +1299,27 @@ static RISCVException riscv_pmu_write_ctr(CPURISCVS= tate *env, target_ulong val, uint32_t ctr_idx) { PMUCTRState *counter =3D &env->pmu_ctrs[ctr_idx]; - uint64_t mhpmctr_val =3D val; + bool rv32 =3D riscv_cpu_mxl(env) =3D=3D MXL_RV32; + int deposit_size =3D rv32 ? 32 : 64; + uint64_t ctr; + + counter->mhpmcounter_val =3D deposit64(counter->mhpmcounter_val, + 0, deposit_size, val); =20 - counter->mhpmcounter_val =3D val; if (!get_field(env->mcountinhibit, BIT(ctr_idx)) && (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || riscv_pmu_ctr_monitor_instructions(env, ctr_idx))) { - counter->mhpmcounter_prev =3D riscv_pmu_ctr_get_fixed_counters_val= (env, - ctr_idx, f= alse); + ctr =3D riscv_pmu_ctr_get_fixed_counters_val(env, ctr_idx, false); + counter->mhpmcounter_prev =3D deposit64(counter->mhpmcounter_prev, + 0, deposit_size, ctr); if (ctr_idx > 2) { - if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { - mhpmctr_val =3D mhpmctr_val | - ((uint64_t)counter->mhpmcounterh_val << 32); - } - riscv_pmu_setup_timer(env, mhpmctr_val, ctr_idx); + riscv_pmu_setup_timer(env, counter->mhpmcounter_val, ctr_idx); } } else { /* Other counters can keep incrementing from the given value */ - counter->mhpmcounter_prev =3D val; + counter->mhpmcounter_prev =3D deposit64(counter->mhpmcounter_prev, + 0, deposit_size, val); + } =20 return RISCV_EXCP_NONE; @@ -1326,21 +1329,22 @@ static RISCVException riscv_pmu_write_ctrh(CPURISCV= State *env, target_ulong val, uint32_t ctr_idx) { PMUCTRState *counter =3D &env->pmu_ctrs[ctr_idx]; - uint64_t mhpmctr_val =3D counter->mhpmcounter_val; - uint64_t mhpmctrh_val =3D val; + uint64_t ctrh; =20 - counter->mhpmcounterh_val =3D val; - mhpmctr_val =3D mhpmctr_val | (mhpmctrh_val << 32); + counter->mhpmcounter_val =3D deposit64(counter->mhpmcounter_val, + 32, 32, val); if (!get_field(env->mcountinhibit, BIT(ctr_idx)) && (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || riscv_pmu_ctr_monitor_instructions(env, ctr_idx))) { - counter->mhpmcounterh_prev =3D riscv_pmu_ctr_get_fixed_counters_va= l(env, - ctr_idx, = true); + ctrh =3D riscv_pmu_ctr_get_fixed_counters_val(env, ctr_idx, true); + counter->mhpmcounter_prev =3D deposit64(counter->mhpmcounter_prev, + 32, 32, ctrh); if (ctr_idx > 2) { - riscv_pmu_setup_timer(env, mhpmctr_val, ctr_idx); + riscv_pmu_setup_timer(env, counter->mhpmcounter_val, ctr_idx); } } else { - counter->mhpmcounterh_prev =3D val; + counter->mhpmcounter_prev =3D deposit64(counter->mhpmcounter_prev, + 32, 32, val); } =20 return RISCV_EXCP_NONE; @@ -1363,13 +1367,17 @@ static RISCVException write_mhpmcounterh(CPURISCVSt= ate *env, int csrno, } =20 RISCVException riscv_pmu_read_ctr(CPURISCVState *env, target_ulong *val, - bool upper_half, uint32_t ctr_idx) + bool upper_half, uint32_t ctr_idx) { PMUCTRState *counter =3D &env->pmu_ctrs[ctr_idx]; - target_ulong ctr_prev =3D upper_half ? counter->mhpmcounterh_prev : - counter->mhpmcounter_prev; - target_ulong ctr_val =3D upper_half ? counter->mhpmcounterh_val : - counter->mhpmcounter_val; + bool rv32 =3D riscv_cpu_mxl(env) =3D=3D MXL_RV32; + int start =3D upper_half ? 32 : 0; + int length =3D rv32 ? 32 : 64; + uint64_t ctr_prev =3D extract64(counter->mhpmcounter_prev, start, leng= th); + uint64_t ctr_val =3D extract64(counter->mhpmcounter_val, start, lengt= h); + + /* Ensure upper_half is only set for XLEN =3D=3D 32 */ + g_assert(rv32 || !upper_half); =20 if (get_field(env->mcountinhibit, BIT(ctr_idx))) { /* @@ -2994,6 +3002,7 @@ static RISCVException write_mcountinhibit(CPURISCVSta= te *env, int csrno, uint32_t present_ctrs =3D cpu->pmu_avail_ctrs | COUNTEREN_CY | COUNTER= EN_IR; target_ulong updated_ctrs =3D (env->mcountinhibit ^ val) & present_ctr= s; uint64_t mhpmctr_val, prev_count, curr_count; + uint64_t ctrh; =20 /* WARL register - disable unavailable counters; TM bit is always 0 */ env->mcountinhibit =3D val & present_ctrs; @@ -3012,17 +3021,13 @@ static RISCVException write_mcountinhibit(CPURISCVS= tate *env, int csrno, counter->mhpmcounter_prev =3D riscv_pmu_ctr_get_fixed_counters_val(env, cidx, false); if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { - counter->mhpmcounterh_prev =3D - riscv_pmu_ctr_get_fixed_counters_val(env, cidx, true); + ctrh =3D riscv_pmu_ctr_get_fixed_counters_val(env, cidx, t= rue); + counter->mhpmcounter_prev =3D deposit64(counter->mhpmcount= er_prev, + 32, 32, ctrh); } =20 if (cidx > 2) { - mhpmctr_val =3D counter->mhpmcounter_val; - if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { - mhpmctr_val =3D mhpmctr_val | - ((uint64_t)counter->mhpmcounterh_val << 32); - } - riscv_pmu_setup_timer(env, mhpmctr_val, cidx); + riscv_pmu_setup_timer(env, counter->mhpmcounter_val, cidx); } } else { curr_count =3D riscv_pmu_ctr_get_fixed_counters_val(env, cidx,= false); @@ -3034,18 +3039,11 @@ static RISCVException write_mcountinhibit(CPURISCVS= tate *env, int csrno, riscv_pmu_ctr_get_fixed_counters_val(env, cidx, true); =20 curr_count =3D curr_count | (tmp << 32); - mhpmctr_val =3D mhpmctr_val | - ((uint64_t)counter->mhpmcounterh_val << 32); - prev_count =3D prev_count | - ((uint64_t)counter->mhpmcounterh_prev << 32); } =20 /* Adjust the counter for later reads. */ mhpmctr_val =3D curr_count - prev_count + mhpmctr_val; counter->mhpmcounter_val =3D mhpmctr_val; - if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { - counter->mhpmcounterh_val =3D mhpmctr_val >> 32; - } } } =20 diff --git a/target/riscv/machine.c b/target/riscv/machine.c index c476bb0089..7b00cb4804 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -338,10 +338,8 @@ static const VMStateDescription vmstate_pmu_ctr_state = =3D { .minimum_version_id =3D 2, .needed =3D pmu_needed, .fields =3D (const VMStateField[]) { - VMSTATE_UINTTL(mhpmcounter_val, PMUCTRState), - VMSTATE_UINTTL(mhpmcounterh_val, PMUCTRState), - VMSTATE_UINTTL(mhpmcounter_prev, PMUCTRState), - VMSTATE_UINTTL(mhpmcounterh_prev, PMUCTRState), + VMSTATE_UINT64(mhpmcounter_val, PMUCTRState), + VMSTATE_UINT64(mhpmcounter_prev, PMUCTRState), VMSTATE_END_OF_LIST() } }; diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index 273822e921..708f2ec7aa 100644 --- a/target/riscv/pmu.c +++ b/target/riscv/pmu.c @@ -101,82 +101,6 @@ static bool riscv_pmu_counter_enabled(RISCVCPU *cpu, u= int32_t ctr_idx) } } =20 -static int riscv_pmu_incr_ctr_rv32(RISCVCPU *cpu, uint32_t ctr_idx) -{ - CPURISCVState *env =3D &cpu->env; - target_ulong max_val =3D UINT32_MAX; - PMUCTRState *counter =3D &env->pmu_ctrs[ctr_idx]; - bool virt_on =3D env->virt_enabled; - - /* Privilege mode filtering */ - if ((env->priv =3D=3D PRV_M && - (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_MINH)) || - (env->priv =3D=3D PRV_S && virt_on && - (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_VSINH)) || - (env->priv =3D=3D PRV_U && virt_on && - (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_VUINH)) || - (env->priv =3D=3D PRV_S && !virt_on && - (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_SINH)) || - (env->priv =3D=3D PRV_U && !virt_on && - (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_UINH))) { - return 0; - } - - /* Handle the overflow scenario */ - if (counter->mhpmcounter_val =3D=3D max_val) { - if (counter->mhpmcounterh_val =3D=3D max_val) { - counter->mhpmcounter_val =3D 0; - counter->mhpmcounterh_val =3D 0; - /* Generate interrupt only if OF bit is clear */ - if (!(env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_OF)) { - env->mhpmevent_val[ctr_idx] |=3D MHPMEVENT_BIT_OF; - riscv_cpu_update_mip(env, MIP_LCOFIP, BOOL_TO_MASK(1)); - } - } else { - counter->mhpmcounterh_val++; - } - } else { - counter->mhpmcounter_val++; - } - - return 0; -} - -static int riscv_pmu_incr_ctr_rv64(RISCVCPU *cpu, uint32_t ctr_idx) -{ - CPURISCVState *env =3D &cpu->env; - PMUCTRState *counter =3D &env->pmu_ctrs[ctr_idx]; - uint64_t max_val =3D UINT64_MAX; - bool virt_on =3D env->virt_enabled; - - /* Privilege mode filtering */ - if ((env->priv =3D=3D PRV_M && - (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_MINH)) || - (env->priv =3D=3D PRV_S && virt_on && - (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_VSINH)) || - (env->priv =3D=3D PRV_U && virt_on && - (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_VUINH)) || - (env->priv =3D=3D PRV_S && !virt_on && - (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_SINH)) || - (env->priv =3D=3D PRV_U && !virt_on && - (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_UINH))) { - return 0; - } - - /* Handle the overflow scenario */ - if (counter->mhpmcounter_val =3D=3D max_val) { - counter->mhpmcounter_val =3D 0; - /* Generate interrupt only if OF bit is clear */ - if (!(env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_OF)) { - env->mhpmevent_val[ctr_idx] |=3D MHPMEVENT_BIT_OF; - riscv_cpu_update_mip(env, MIP_LCOFIP, BOOL_TO_MASK(1)); - } - } else { - counter->mhpmcounter_val++; - } - return 0; -} - /* * Information needed to update counters: * new_priv, new_virt: To correctly save starting snapshot for the newly @@ -275,8 +199,10 @@ void riscv_pmu_update_fixed_ctrs(CPURISCVState *env, t= arget_ulong newpriv, int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_event_idx event_idx) { uint32_t ctr_idx; - int ret; CPURISCVState *env =3D &cpu->env; + uint64_t max_val =3D UINT64_MAX; + bool virt_on =3D env->virt_enabled; + PMUCTRState *counter; gpointer value; =20 if (!cpu->cfg.pmu_mask) { @@ -293,13 +219,34 @@ int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_= event_idx event_idx) return -1; } =20 - if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { - ret =3D riscv_pmu_incr_ctr_rv32(cpu, ctr_idx); + /* Privilege mode filtering */ + if ((env->priv =3D=3D PRV_M && + (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_MINH)) || + (env->priv =3D=3D PRV_S && virt_on && + (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_VSINH)) || + (env->priv =3D=3D PRV_U && virt_on && + (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_VUINH)) || + (env->priv =3D=3D PRV_S && !virt_on && + (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_SINH)) || + (env->priv =3D=3D PRV_U && !virt_on && + (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_UINH))) { + return 0; + } + + /* Handle the overflow scenario */ + counter =3D &env->pmu_ctrs[ctr_idx]; + if (counter->mhpmcounter_val =3D=3D max_val) { + counter->mhpmcounter_val =3D 0; + /* Generate interrupt only if OF bit is clear */ + if (!(env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_OF)) { + env->mhpmevent_val[ctr_idx] |=3D MHPMEVENT_BIT_OF; + riscv_cpu_update_mip(env, MIP_LCOFIP, BOOL_TO_MASK(1)); + } } else { - ret =3D riscv_pmu_incr_ctr_rv64(cpu, ctr_idx); + counter->mhpmcounter_val++; } =20 - return ret; + return 0; } =20 bool riscv_pmu_ctr_monitor_instructions(CPURISCVState *env, @@ -470,8 +417,6 @@ static void pmu_timer_trigger_irq(RISCVCPU *cpu, if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { riscv_pmu_read_ctr(env, (target_ulong *)&curr_ctrh_val, true, ctr_= idx); curr_ctr_val =3D curr_ctr_val | (curr_ctrh_val << 32); - ctr_val =3D ctr_val | - ((uint64_t)counter->mhpmcounterh_val << 32); } =20 /* --=20 2.51.0