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([71.212.157.132]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-77f0da43089sm9899622b3a.90.2025.09.22.19.39.25 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Sep 2025 19:39:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758595166; x=1759199966; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=I7FMx8ch25mi1HM2iSzOFbjlu0abcZfgeYT8ylr/T9c=; b=DgiaA+16cdKkQCxBaEevtLabbaUykaiwHvoBuA2mIE5kSHv5m1eraeWj3cLUZy++86 T8UBfqJXauzQ9gCZjtdlxkn3SlC6RVb6JeSd4l3Z+ikca95502ZyCZR7Ppm6K6Tu3ud8 L+zo+l+Z2diVxxHn4yt2X+E5cu4YUh458v/LxSk1AVqeqsB7UrLQ2sSB29MaU9bmZ1bt CnPJgPaZ44BPJBbJuw1uv2OSoePEzzF7Pdxxsh4PmxyN9xj2krkx9WqQkEMOtVDtFTs/ lzTgb9lYfCbyNodmwCT7QNPFJfOxjZ4RjIb+LGvmT5kktkSovCPj9mJfXuxoGoIJyMNH Ysbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758595166; x=1759199966; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=I7FMx8ch25mi1HM2iSzOFbjlu0abcZfgeYT8ylr/T9c=; b=NuUYDnX9/3VvFD3fFUPHRoHO7CHpVq1nDSHpA1EW2W2WGM8yxlZL4RZtip1ZUPBT9C iMrYdzgi1K6J399GzeMIJLDFfS3gVyHYY2lyWpeyceN9GwFbCcZwdOlXTHNuc8v+77nA 32mtyITo48eKfTG/WDPJXi2bYaurY/31UfJKKnyRbNRYLfpaU9xTUTHRH1YkTXaZsulh EMQvF3VI8r3KYjyUyqN4sDax3cxDeyDrTMqRk2fSivfce2wDnZDmA9xClRzzy5wOQ3Hh WWVWQYvojzPNJdHZMNziOC4cuA0iPR4J2FbeZvFc4eD2cWN5fWviRzHB8pF02vMnKZzF YnSQ== X-Gm-Message-State: AOJu0Yy0mN23x9jFMamOLdIggSspfGzYxQu9t5FupA0MHIDza6zEshQn d+2dTJRG5NPxChQzwVEkiPK0fr4imbMioCI/1GciRu165vL6qUpmKMonELV+93NIedmUNlYe5Cd AKznp X-Gm-Gg: ASbGncv0rQeCMdPAEvgh3biFUaULg1IYEs0q8ehbBL34PJLcJV4e2kRI/OVS9WynPM8 EHHef4B6y0UG3oL1b4TdZ2Fea1KDdNcVku6aLPkNvvQjtYt3dyQajIZJQ6GW1RRYIYY27fAg1xX bezDnEzaxDMwiVSNHuQYspyzL/3iL5Gvetmy/b2+UzitsBet1zRV6C0vtFvkkSSZHthRWsCydyK rHswvk00n6ayFvJGDYLqrFs0e25GhzY3q9CyxWHnDw64zpCA9TeRfdy0rkVSTaB97nFpcoB1qxh REXdMtikH2ZJ0Um0MArlSfDFaiw2++vm5DRReX4IqP5R4fikQ51k3hJy41epRecvFf/elzRjTzV ElhEMQ8oTmKdqViZFkhVXHgMZ/gOv X-Google-Smtp-Source: AGHT+IEicq4MIqnZXV1Dwrod3IW6O3/D0dOoMSoc/ubULa18kIa+bAPZkTRLO/siljOYHjyUmJ/WgQ== X-Received: by 2002:a05:6a00:1825:b0:772:4b05:78b0 with SMTP id d2e1a72fcca58-77f53887f3emr1124770b3a.7.1758595166094; Mon, 22 Sep 2025 19:39:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 03/12] target/alpha: Simplify call_pal implementation Date: Mon, 22 Sep 2025 19:39:07 -0700 Message-ID: <20250923023922.3102471-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250923023922.3102471-1-richard.henderson@linaro.org> References: <20250923023922.3102471-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758595402547116600 Content-Type: text/plain; charset="utf-8" Since 288a5fe980f, we don't link translation blocks directly to palcode entry points. If we load palbr from env instead of encoding the constant, we avoid all need for tb_flush(). Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/alpha/helper.h | 1 - target/alpha/sys_helper.c | 6 ------ target/alpha/translate.c | 21 ++++++--------------- 3 files changed, 6 insertions(+), 22 deletions(-) diff --git a/target/alpha/helper.h b/target/alpha/helper.h index d60f208703..788d2fbf28 100644 --- a/target/alpha/helper.h +++ b/target/alpha/helper.h @@ -90,7 +90,6 @@ DEF_HELPER_FLAGS_2(ieee_input_s, TCG_CALL_NO_WG, void, en= v, i64) #if !defined (CONFIG_USER_ONLY) DEF_HELPER_FLAGS_1(tbia, TCG_CALL_NO_RWG, void, env) DEF_HELPER_FLAGS_2(tbis, TCG_CALL_NO_RWG, void, env, i64) -DEF_HELPER_FLAGS_1(tb_flush, TCG_CALL_NO_RWG, void, env) =20 DEF_HELPER_1(halt, void, i64) =20 diff --git a/target/alpha/sys_helper.c b/target/alpha/sys_helper.c index 51e3254428..87e37605c1 100644 --- a/target/alpha/sys_helper.c +++ b/target/alpha/sys_helper.c @@ -20,7 +20,6 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/cputlb.h" -#include "exec/tb-flush.h" #include "exec/helper-proto.h" #include "system/runstate.h" #include "system/system.h" @@ -38,11 +37,6 @@ void helper_tbis(CPUAlphaState *env, uint64_t p) tlb_flush_page(env_cpu(env), p); } =20 -void helper_tb_flush(CPUAlphaState *env) -{ - tb_flush(env_cpu(env)); -} - void helper_halt(uint64_t restart) { if (restart) { diff --git a/target/alpha/translate.c b/target/alpha/translate.c index cebab0318c..f11b382438 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -48,8 +48,6 @@ struct DisasContext { =20 #ifdef CONFIG_USER_ONLY MemOp unalign; -#else - uint64_t palbr; #endif uint32_t tbflags; int mem_idx; @@ -1155,7 +1153,6 @@ static DisasJumpType gen_call_pal(DisasContext *ctx, = int palcode) #else { TCGv tmp =3D tcg_temp_new(); - uint64_t entry; =20 gen_pc_disp(ctx, tmp, 0); if (ctx->tbflags & ENV_FLAG_PAL_MODE) { @@ -1165,12 +1162,11 @@ static DisasJumpType gen_call_pal(DisasContext *ctx= , int palcode) } tcg_gen_st_i64(tmp, tcg_env, offsetof(CPUAlphaState, exc_addr)); =20 - entry =3D ctx->palbr; - entry +=3D (palcode & 0x80 - ? 0x2000 + (palcode - 0x80) * 64 - : 0x1000 + palcode * 64); - - tcg_gen_movi_i64(cpu_pc, entry); + tcg_gen_ld_i64(cpu_pc, tcg_env, offsetof(CPUAlphaState, palbr)); + tcg_gen_addi_i64(cpu_pc, cpu_pc, + palcode & 0x80 + ? 0x2000 + (palcode - 0x80) * 64 + : 0x1000 + palcode * 64); return DISAS_PC_UPDATED; } #endif @@ -1292,11 +1288,7 @@ static DisasJumpType gen_mtpr(DisasContext *ctx, TCG= v vb, int regno) case 7: /* PALBR */ tcg_gen_st_i64(vb, tcg_env, offsetof(CPUAlphaState, palbr)); - /* Changing the PAL base register implies un-chaining all of the T= Bs - that ended with a CALL_PAL. Since the base register usually on= ly - changes during boot, flushing everything works well. */ - gen_helper_tb_flush(tcg_env); - return DISAS_PC_STALE; + break; =20 case 32 ... 39: /* Accessing the "non-shadow" general registers. */ @@ -2874,7 +2866,6 @@ static void alpha_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cpu) ctx->ir =3D cpu_std_ir; ctx->unalign =3D (ctx->tbflags & TB_FLAG_UNALIGN ? MO_UNALN : MO_ALIGN= ); #else - ctx->palbr =3D env->palbr; ctx->ir =3D (ctx->tbflags & ENV_FLAG_PAL_MODE ? cpu_pal_ir : cpu_std_i= r); #endif =20 --=20 2.43.0