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([71.212.157.132]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-77f335995cbsm4490399b3a.63.2025.09.22.12.29.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Sep 2025 12:29:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758569383; x=1759174183; darn=nongnu.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=W6jjoifMhsz3D5D+KPnArq2qaNpW1k7zris8SQE/uuE=; b=Msw9mLaBUbmd9hAaT4IQhDLfZ2Y+3ioNDV+ppYYVUaTfX7CXzq7UXOY7uTXnswdVwX BzIaYh7aPVbPf7ZiYNQsrq8iO+CaLEwNfkrV7xC7rrPCWJavOeVImxuVGbwaxX8JdO33 nyi7SimNe4BqqbfesubETs6FMxaevV7BpwCdsweHpvk1S5Lz4oqEo5zqcvKfB8ZdWnIM 4pohqDpMCFhGtnAMCOAVmra8YIU03/xuP6BTQH7Jz531L5FaZj5s+icZlDn9Cp5aEF8V ZcoJUnECaf7A5Bq5JN2IXwXSNj49NsQ7dJ0U551scSyxrA+DIVg9YIADjtizxS77684r T0VQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758569383; x=1759174183; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=W6jjoifMhsz3D5D+KPnArq2qaNpW1k7zris8SQE/uuE=; b=cTz2zN1ulOOCzMZsAkSmC9zrRWAfGpcVIyNDAQfufhyXHxKbDTJGNsG36Ft820DUp0 +Cw4G4vCCaI2Z6eVMhOxwllsAcoE3qHVj/DEcVIUpyvc2ou0mF+zvy63WSVXmCvXLYOF MPfFaXkxEI3TsaMPlvCIsz+qTIbo1u1pgdTTLoYMrJI4ucEhwY6NFskd7wFoLS6KVn+P VzVi9TpcqFoJNeExiwXuIfN9ISgv9xmkAS3kQarxUGpXYqWPxJ+Bvgy1xlQ9Kqgu6eK5 7h1swh9D7R9AqZ/babob+8o7h+sDWccOQ341aJCpsgmre6k84CZ8zlHtj4V3WyrydMFP zw5A== X-Gm-Message-State: AOJu0Yxskt5nB7WE/aLQHLypHGrZC0+R89M5DmnpghzH+B8H0Kph8HOW 01bq8nOz62/B4RvqaMqxeBJ9UQR74t+a4Ga3DM0YDGUzfoCO58XtSG2VqUes4wvQv3d2SVxfSw0 xTSBB X-Gm-Gg: ASbGnct4SZGe+XMes63SATyHxT0Qfisffq/Y8l+7on5ErxQwBEygzADrZzyytrUbuAa VquO0AGlzQmxS+s6CmaDEORq38oH0PzIpvlCNfV/kAZSjRqFByTL3yb/3i2reJjJCUe2pm1xMMG WHs81IRr2P+qvGGwlqJeLjV2KH8DddIcmtX6chSv+r9IIjJhsE6uYqHhzeExkE1VmR9cptF8NcU yF+awp2F9RIY8oCfLw9Qj052/5bogal4uVQdJhgbH1vA2T7z2xRz1TrS0sdRsjFQxPbdQRAF54l M9brIckh8T1Wse97ThGtE5Q82QUxy99uWcpqXqs/+76StURRTAI63RekvDOeYo+OZIySV2HGjGH MGAo9m8ekCNYkicl4awX2SQgMLltPQEQt+Apk/wo= X-Google-Smtp-Source: AGHT+IGZ0M6fDfwbMFyO67/SWh6p+PNblSW8J/Xw58ZsOogfKpU7enbRycakzrurRahws47IlrG89A== X-Received: by 2002:a17:90b:4ac1:b0:32e:3830:65d5 with SMTP id 98e67ed59e1d1-332a96fd8c1mr66577a91.36.1758569382286; Mon, 22 Sep 2025 12:29:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: thuth@redhat.com Subject: [PATCH] system/memory: Split address_space_write_rom_internal Date: Mon, 22 Sep 2025 12:29:40 -0700 Message-ID: <20250922192940.2908002-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758569502018116600 Content-Type: text/plain; charset="utf-8" In 2dbaf58bbe7 we conditionally skipped the increment of buf because ubsan warns incrementing NULL, and buf is always NULL for FLUSH_CACHE. However, the existence of the test for NULL caused Coverity to warn that the memcpy in the WRITE_DATA case lacked a test for NULL. Duplicate address_space_write_rom_internal into the two callers, dropping enum write_rom_type, and simplify. This eliminates buf in the flush case, and eliminates the conditional increment of buf in the write case. Coverity: CID 1621220 Fixes: 2dbaf58bbe7 ("system/physmem: Silence warning from ubsan") Signed-off-by: Richard Henderson Reviewed-by: Thomas Huth --- system/physmem.c | 90 ++++++++++++++++++++---------------------------- 1 file changed, 37 insertions(+), 53 deletions(-) diff --git a/system/physmem.c b/system/physmem.c index ae8ecd50ea..5f76a5f767 100644 --- a/system/physmem.c +++ b/system/physmem.c @@ -3187,63 +3187,33 @@ void cpu_physical_memory_rw(hwaddr addr, void *buf, buf, len, is_write); } =20 -enum write_rom_type { - WRITE_DATA, - FLUSH_CACHE, -}; - -static inline MemTxResult address_space_write_rom_internal(AddressSpace *a= s, - hwaddr addr, - MemTxAttrs attr= s, - const void *ptr, - hwaddr len, - enum write_rom_= type type) -{ - hwaddr l; - uint8_t *ram_ptr; - hwaddr addr1; - MemoryRegion *mr; - const uint8_t *buf =3D ptr; - - RCU_READ_LOCK_GUARD(); - while (len > 0) { - l =3D len; - mr =3D address_space_translate(as, addr, &addr1, &l, true, attrs); - - if (!memory_region_supports_direct_access(mr)) { - l =3D memory_access_size(mr, l, addr1); - } else { - /* ROM/RAM case */ - ram_ptr =3D qemu_map_ram_ptr(mr->ram_block, addr1); - switch (type) { - case WRITE_DATA: - memcpy(ram_ptr, buf, l); - invalidate_and_set_dirty(mr, addr1, l); - break; - case FLUSH_CACHE: - flush_idcache_range((uintptr_t)ram_ptr, (uintptr_t)ram_ptr= , l); - break; - } - } - len -=3D l; - addr +=3D l; - if (buf) { - buf +=3D l; - } - } - return MEMTX_OK; -} - /* used for ROM loading : can write in RAM and ROM */ MemTxResult address_space_write_rom(AddressSpace *as, hwaddr addr, MemTxAttrs attrs, const void *buf, hwaddr len) { - return address_space_write_rom_internal(as, addr, attrs, - buf, len, WRITE_DATA); + RCU_READ_LOCK_GUARD(); + while (len > 0) { + hwaddr addr1, l =3D len; + MemoryRegion *mr =3D address_space_translate(as, addr, &addr1, &l, + true, attrs); + + if (!memory_region_supports_direct_access(mr)) { + l =3D memory_access_size(mr, l, addr1); + } else { + /* ROM/RAM case */ + void *ram_ptr =3D qemu_map_ram_ptr(mr->ram_block, addr1); + memcpy(ram_ptr, buf, l); + invalidate_and_set_dirty(mr, addr1, l); + } + len -=3D l; + addr +=3D l; + buf +=3D l; + } + return MEMTX_OK; } =20 -void cpu_flush_icache_range(hwaddr start, hwaddr len) +void cpu_flush_icache_range(hwaddr addr, hwaddr len) { /* * This function should do the same thing as an icache flush that was @@ -3255,9 +3225,23 @@ void cpu_flush_icache_range(hwaddr start, hwaddr len) return; } =20 - address_space_write_rom_internal(&address_space_memory, - start, MEMTXATTRS_UNSPECIFIED, - NULL, len, FLUSH_CACHE); + RCU_READ_LOCK_GUARD(); + while (len > 0) { + hwaddr addr1, l =3D len; + MemoryRegion *mr =3D address_space_translate(&address_space_memory, + addr, &addr1, &l, true, + MEMTXATTRS_UNSPECIFIED); + + if (!memory_region_supports_direct_access(mr)) { + l =3D memory_access_size(mr, l, addr1); + } else { + /* ROM/RAM case */ + void *ram_ptr =3D qemu_map_ram_ptr(mr->ram_block, addr1); + flush_idcache_range((uintptr_t)ram_ptr, (uintptr_t)ram_ptr, l); + } + len -=3D l; + addr +=3D l; + } } =20 /* --=20 2.43.0