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([71.212.157.132]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-77e5fe6de75sm10583861b3a.19.2025.09.22.11.49.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Sep 2025 11:49:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758566977; x=1759171777; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=w2rBRozKEd87zp0jXWm3YMjmof4kQNhr2ot0ultU52Y=; b=vm25QWfmp1ZbnIH9B4CuHAjkAXuOznUr2gCCM7QGEJDtq2tHdm0Wal8Gh+xCZLN4nO MTjRe4I0vZaiAAKVrwFxiYSXWfBHtH8pIskPnonwCTUDsspAAmsCPNgGbGeAIb6Zgn2N AShxKfoFvEeALwZ+tzXJQTZvr+du5B2DQ0JfZQX4qAbDMFwpT+bOINSJK+Yex1rWmLDE V5axznxaQcMvx2+qyPT1WOJwPJelYcxtbo/7ifTnr38oIRvQTnutSJn5PGd3VUX/istz s2+4DezHEPcgvb/c/LGslKoVA75djce4tPff8T1ipQs6fmi5yV83CPwfpsNcsUaoUUm5 U2rg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758566977; x=1759171777; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=w2rBRozKEd87zp0jXWm3YMjmof4kQNhr2ot0ultU52Y=; b=aKkMfuagYDn4U/24ka7GIDNT6pyP8H6vHXkc5c+zpUOmqitx7x2ZJkQtwUBMvhbj5y iW1RDysJf8Ht2Xv9KbZqPqWvAfPzkjbJnWKrck4b8Cx12ickfdLYI38I+ZS62yWRDF1a Rkcq9o7hjEKT6NxFmYtoNsIPefbQ7rkACWabkVGT7JrP73dxKTBh0FpIxTMewhdntzWE cbT3XAeRrCbHOKwki6PDnE2kEU3FcS2p+0yKtt7hX9KzY5OlX7C0TEFyw16M1T3fBxEw OAnJQ48dU+MHsSnXzrvxZtBAECf2960TeGtlONm+5o0hFCLC8Uw6bOZ3HiFcFrpJZL9d CvUg== X-Gm-Message-State: AOJu0Yw+wa1qScd6SYsk7iHnb9YVmRAzIlX+k6lugdyXfCMIkhOuwEoy R2uhFmRRJnC6k+XMi6jmOBIWffEaEswI3V7DBF77brmGvx1e9Y9eMTdN3Jv3e6uNsLz+vIsuR0B GDoLr X-Gm-Gg: ASbGncurL3rUWlMjdae1TNh8iBS2yd7kHWZbiT2WiCrTIhaVEEQ5d8Kry3tjaxR2gxd VapqfBjAUa+R8A59enh+DNdu4yKcswd/sDGTK6V9nsjo6lDP6H433tofnLpw8QqklNtaxZDYIJB 8/FA2ateTtEikEDDD/MN+xfUVfKsWLKm3PsGS3WNKZR5l77AIIaR/CKmEgP0JuSN46FpxxZXfhL ZhMU2m23u8lhTulUls0K8eOIeTV+bNnMJhnlOXSlh/ia5VnZFsliakdPGYdSXVzeWzPsvoTmmvq wnoeFlXFFHpwMy/odl8rU6Dmr2TOmQ6bJSVmcjFyrYpkM6N39IspSyURTS0q2Q334VFPAzvxHAo onf1twJ0qbBhV9CcC8OFqOe0Jmnjyhl0bC1n0Q1w= X-Google-Smtp-Source: AGHT+IGcZkuu58nGoulniswH9n8OgRK7reB6bHSUbs+eDGr5jRp99dCxcIRVIJjF9ZIXfJycucRD3g== X-Received: by 2002:a05:6a00:2194:b0:77f:2978:30b0 with SMTP id d2e1a72fcca58-77f29783c90mr7096659b3a.11.1758566976669; Mon, 22 Sep 2025 11:49:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Pierrick Bouvier Subject: [PATCH v5 08/76] target/arm: Implement get_S2prot_indirect Date: Mon, 22 Sep 2025 11:48:16 -0700 Message-ID: <20250922184924.2754205-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250922184924.2754205-1-richard.henderson@linaro.org> References: <20250922184924.2754205-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758567197478116600 Content-Type: text/plain; charset="utf-8" Move the stage2 permissions for normal accesses to GetPhysAddrResult.s2prot. Put the stage2 permissions for page table walking in CPUTLBEntryFull.prot. This allows the permission checks in S1_ptw_translate and arm_casq_ptw to see the right permission. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/internals.h | 7 ++++ target/arm/ptw.c | 81 +++++++++++++++++++++++++++++++----------- 2 files changed, 68 insertions(+), 20 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index b7a1b69561..aa41054af0 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1572,6 +1572,13 @@ typedef struct ARMCacheAttrs { typedef struct GetPhysAddrResult { CPUTLBEntryFull f; ARMCacheAttrs cacheattrs; + /* + * For ARMMMUIdx_Stage2*, the protection installed into f.prot + * is the result for AccessType_TTW, i.e. the page table walk itself. + * The protection installed info s2prot is the one to be merged + * with the stage1 protection. + */ + int s2prot; } GetPhysAddrResult; =20 /** diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 4fb4436db1..6dcd3adbdf 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1280,7 +1280,7 @@ do_fault: * @xn: XN (execute-never) bits * @s1_is_el0: true if this is S2 of an S1+2 walk for EL0 */ -static int get_S2prot_noexecute(int s2ap) +static int get_S2prot(CPUARMState *env, int s2ap, int xn, bool s1_is_el0) { int prot =3D 0; =20 @@ -1290,12 +1290,6 @@ static int get_S2prot_noexecute(int s2ap) if (s2ap & 2) { prot |=3D PAGE_WRITE; } - return prot; -} - -static int get_S2prot(CPUARMState *env, int s2ap, int xn, bool s1_is_el0) -{ - int prot =3D get_S2prot_noexecute(s2ap); =20 if (cpu_isar_feature(any_tts2uxn, env_archcpu(env))) { switch (xn) { @@ -1327,6 +1321,44 @@ static int get_S2prot(CPUARMState *env, int s2ap, in= t xn, bool s1_is_el0) return prot; } =20 +static int get_S2prot_indirect(CPUARMState *env, GetPhysAddrResult *result, + int pi_index, int po_index, bool s1_is_el0) +{ + /* Last index is (priv, unpriv, ttw) */ + static const uint8_t perm_table[16][3] =3D { + /* 0 */ { 0, 0, 0 }, /* no access */ + /* 1 */ { 0, 0, 0 }, /* reserved */ + /* 2 */ { PAGE_READ, PAGE_READ, PAGE_READ | PAGE_WRITE }, + /* 3 */ { PAGE_READ, PAGE_READ, PAGE_READ | PAGE_WRITE }, + /* 4 */ { PAGE_WRITE, PAGE_WRITE, 0 }, + /* 5 */ { 0, 0, 0 }, /* reserved */ + /* 6 */ { PAGE_READ, PAGE_READ, PAGE_READ | PAGE_WRITE }, + /* 7 */ { PAGE_READ, PAGE_READ, PAGE_READ | PAGE_WRITE }, + /* 8 */ { PAGE_READ, PAGE_READ, PAGE_READ }, + /* 9 */ { PAGE_READ, PAGE_READ | PAGE_EXEC, PAGE_READ }, + /* A */ { PAGE_READ | PAGE_EXEC, PAGE_READ, PAGE_READ }, + /* B */ { PAGE_READ | PAGE_EXEC, PAGE_READ | PAGE_EXEC, PAGE_READ = }, + /* C */ { PAGE_READ | PAGE_WRITE, + PAGE_READ | PAGE_WRITE, + PAGE_READ | PAGE_WRITE }, + /* D */ { PAGE_READ | PAGE_WRITE, + PAGE_READ | PAGE_WRITE | PAGE_EXEC, + PAGE_READ | PAGE_WRITE }, + /* E */ { PAGE_READ | PAGE_WRITE | PAGE_EXEC, + PAGE_READ | PAGE_WRITE, + PAGE_READ | PAGE_WRITE }, + /* F */ { PAGE_READ | PAGE_WRITE | PAGE_EXEC, + PAGE_READ | PAGE_WRITE | PAGE_EXEC, + PAGE_READ | PAGE_WRITE }, + }; + + uint64_t pir =3D (env->cp15.scr_el3 & SCR_PIEN ? env->cp15.s2pir_el2 := 0); + int s2pi =3D extract64(pir, pi_index * 4, 4); + + result->f.prot =3D perm_table[s2pi][2]; + return perm_table[s2pi][s1_is_el0]; +} + /* * Translate section/page access permissions to protection flags * @env: CPUARMState @@ -1777,7 +1809,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Tr= anslate *ptw, int32_t stride; int addrsize, inputsize, outputsize; uint64_t tcr =3D regime_tcr(env, mmu_idx); - int ap; + int ap, prot; uint32_t el =3D regime_el(env, mmu_idx); uint64_t descaddrmask; bool aarch64 =3D arm_el_is_aa64(env, el); @@ -2101,6 +2133,18 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1T= ranslate *ptw, ap =3D extract32(attrs, 6, 2); out_space =3D ptw->in_space; if (regime_is_stage2(mmu_idx)) { + if (param.pie) { + int pi =3D extract64(attrs, 6, 1) + | (extract64(attrs, 51, 1) << 1) + | (extract64(attrs, 53, 2) << 2); + int po =3D extract64(attrs, 60, 3); + prot =3D get_S2prot_indirect(env, result, pi, po, ptw->in_s1_i= s_el0); + } else { + int xn =3D extract64(attrs, 53, 2); + prot =3D get_S2prot(env, ap, xn, ptw->in_s1_is_el0); + /* Install TTW permissions in f.prot. */ + result->f.prot =3D prot & (PAGE_READ | PAGE_WRITE); + } /* * R_GYNXY: For stage2 in Realm security state, bit 55 is NS. * The bit remains ignored for other security states. @@ -2109,11 +2153,9 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1T= ranslate *ptw, */ if (out_space =3D=3D ARMSS_Realm && extract64(attrs, 55, 1)) { out_space =3D ARMSS_NonSecure; - result->f.prot =3D get_S2prot_noexecute(ap); - } else { - int xn =3D extract64(attrs, 53, 2); - result->f.prot =3D get_S2prot(env, ap, xn, ptw->in_s1_is_el0); + prot &=3D ~PAGE_EXEC; } + result->s2prot =3D prot; =20 result->cacheattrs.is_s2_format =3D true; result->cacheattrs.attrs =3D extract32(attrs, 2, 4); @@ -2185,9 +2227,8 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Tr= anslate *ptw, * Note that we modified ptw->in_space earlier for NSTable, but * result->f.attrs retains a copy of the original security spa= ce. */ - result->f.prot =3D get_S1prot_indirect(env, ptw, mmu_idx, pi, = po, - result->f.attrs.space, - out_space); + prot =3D get_S1prot_indirect(env, ptw, mmu_idx, pi, po, + result->f.attrs.space, out_space); } else { int xn =3D extract64(attrs, 54, 1); int pxn =3D extract64(attrs, 53, 1); @@ -2216,10 +2257,10 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1= Translate *ptw, * Note that we modified ptw->in_space earlier for NSTable, but * result->f.attrs retains a copy of the original security spa= ce. */ - result->f.prot =3D get_S1prot(env, mmu_idx, aarch64, - user_rw, prot_rw, xn, pxn, - result->f.attrs.space, out_space); + prot =3D get_S1prot(env, mmu_idx, aarch64, user_rw, prot_rw, x= n, pxn, + result->f.attrs.space, out_space); } + result->f.prot =3D prot; =20 /* Index into MAIR registers for cache attributes */ attrindx =3D extract32(attrs, 2, 3); @@ -2265,7 +2306,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Tr= anslate *ptw, result->f.tlb_fill_flags =3D 0; } =20 - if (ptw->in_prot_check & ~result->f.prot) { + if (ptw->in_prot_check & ~prot) { fi->type =3D ARMFault_Permission; goto do_fault; } @@ -3463,7 +3504,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, = S1Translate *ptw, fi->s2addr =3D ipa; =20 /* Combine the S1 and S2 perms. */ - result->f.prot &=3D s1_prot; + result->f.prot =3D s1_prot & result->s2prot; =20 /* If S2 fails, return early. */ if (ret) { --=20 2.43.0