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([71.212.157.132]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-77e5fe6de75sm10583861b3a.19.2025.09.22.11.49.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Sep 2025 11:49:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758566976; x=1759171776; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Og9JNUSJhtxcO4q7du8DvVfoQI0JDprhWczIVzB4Jaw=; b=LGbNeFMdYP1Dt2Tvr/h/fZ4btB1ZqG9xED/DvHP8g+1Ta2blqm6p4UOXISjYBYyw28 PhUqUMwbGxNeGmHghUO65mFzX5jTFL9mvaTZG6yQsZwvoT4k3MngNbYnN4EnLos5Lrsi 99rS02Z7T2eLkR72Qz7WCuH0ZuGouPFDH8hqdtqh1RjHHfZIC7lLP9A95vREcPvyxU18 Akq+EpGt+xh/278sDRfKL+g4zfGO1Nb/CZ2rO8ypKDgoFdGrtb+dNp9/YXGjhwcK9kte VSRieX7kIlB/j41Ja0R6s6F3ZryyEf/RemSvz1niUlrF2qVJlND3lipn9IUql289qAFY qQVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758566976; x=1759171776; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Og9JNUSJhtxcO4q7du8DvVfoQI0JDprhWczIVzB4Jaw=; b=nxSc3Yc5z0gOn1OgQI+jWK44AITsFxIE+vPbdC9ApI64V6e1KHj941VpASpkXQmNu8 Nvp185mBi4TLJ8uXnJPkvqoza0Vt/nVAuw6kpgn/PaoHWbpz27s2AdFlqpL4s7DECNGd W9bog8cEWufngGyrjRwDPlrJyuwlcq+a0qPLNd3jG4tvNWlviwHzsvex2202cAv7v1Qo YFbJim9PEDBfwGFzeWq1yTpE8p6ZN5rzJRLdqlQemaOijRkpINGyfnq3dUsaFyw/bIaL p6+ztcigeBGKXePteH9gbREQEq2d//NUayPJRNDGkIfFCcbFdo29GHCn9JuQQ/notGHn eG8A== X-Gm-Message-State: AOJu0YyfyE456j36dW4Go9RZpuqBHbRgtcnId0dCpO/EdTrOHTfyaDFV uyEJpMbpcP7lcanC3EXrdW8bZ1sbqobwT02Jv6yUVZoXqfoEYuwSRqmIvJNwu1jXQEzblXg0dV2 3PVoG X-Gm-Gg: ASbGncvC/Xwm5inrZF6SF13LBjz60Vil1eRMl32wPp6wZ1d1xeD1GCip6oC0qUqNtkw QRpLrxxlg6S0nZxzQ+HSqgp3R/lybd+VYe6dRD92inMKgl5nc4DH9fDjpBAjdRwQoprmcs0602c RqYaJk4IeuPUaf80kLhMTHZCR4cpKx5XiCnyJpjAN/BOajs9WxPNy9wNPYCPuwAfkPf4RGvLUik s61S5DCTeuKgTT20z2QX+o/smr/+8qHGRpqYFYDMXZindYPamx09oh4YVn/9CaE+ZgfAFtkJdan Ibg/iZAjEDXrrUD+pdmeoCm/OBWmIjarjSWeMVC3stZJKomgMupFyqzJt3T8i3EJ6jqND68M18X o/HfrMAjEDKYT/BS7KoVDsJUwkaN+ X-Google-Smtp-Source: AGHT+IGdWYZL90qwpY09ICZdypBV24pVOOo/K8jdSfx+E4CZvwPzjpIGQ+J5lVLJ3HlG+kic6iBBTg== X-Received: by 2002:a05:6a20:a10c:b0:246:7032:2c1d with SMTP id adf61e73a8af0-2cfdfe1be61mr116046637.23.1758566975680; Mon, 22 Sep 2025 11:49:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Pierrick Bouvier Subject: [PATCH v5 07/76] target/arm: Implement get_S1prot_indirect Date: Mon, 22 Sep 2025 11:48:15 -0700 Message-ID: <20250922184924.2754205-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250922184924.2754205-1-richard.henderson@linaro.org> References: <20250922184924.2754205-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758567213662116600 Content-Type: text/plain; charset="utf-8" This approximately corresponds to AArch64.S1IndirectBasePermissions and the tail of AArch64.S1ComputePermissions which applies WXN. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/ptw.c | 169 +++++++++++++++++++++++++++++++++++++++-------- 1 file changed, 143 insertions(+), 26 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index d6d704e2a9..4fb4436db1 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1448,6 +1448,106 @@ static int get_S1prot(CPUARMState *env, ARMMMUIdx m= mu_idx, bool is_aa64, return prot_rw | PAGE_EXEC; } =20 +/* Extra page permission bits, during get_S1prot_indirect only. */ +#define PAGE_GCS (1 << 3) +#define PAGE_WXN (1 << 4) +#define PAGE_OVERLAY (1 << 5) +QEMU_BUILD_BUG_ON(PAGE_RWX & (PAGE_GCS | PAGE_WXN | PAGE_OVERLAY)); + +static int get_S1prot_indirect(CPUARMState *env, S1Translate *ptw, + ARMMMUIdx mmu_idx, int pi_index, int po_ind= ex, + ARMSecuritySpace in_pa, ARMSecuritySpace ou= t_pa) +{ + static const uint8_t perm_table[16] =3D { + /* 0 */ PAGE_OVERLAY, /* no access */ + /* 1 */ PAGE_OVERLAY | PAGE_READ, + /* 2 */ PAGE_OVERLAY | PAGE_EXEC, + /* 3 */ PAGE_OVERLAY | PAGE_READ | PAGE_EXEC, + /* 4 */ PAGE_OVERLAY, /* reserved */ + /* 5 */ PAGE_OVERLAY | PAGE_READ | PAGE_WRITE, + /* 6 */ PAGE_OVERLAY | PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_W= XN, + /* 7 */ PAGE_OVERLAY | PAGE_READ | PAGE_WRITE | PAGE_EXEC, + /* 8 */ PAGE_READ, + /* 9 */ PAGE_READ | PAGE_GCS, + /* A */ PAGE_READ | PAGE_EXEC, + /* B */ 0, /* reserved */ + /* C */ PAGE_READ | PAGE_WRITE, + /* D */ 0, /* reserved */ + /* E */ PAGE_READ | PAGE_WRITE | PAGE_EXEC, + /* F */ 0, /* reserved */ + }; + + uint32_t el =3D regime_el(env, mmu_idx); + uint64_t pir =3D env->cp15.pir_el[el]; + uint64_t pire0 =3D 0; + int perm; + + if (el < 3) { + if (arm_feature(env, ARM_FEATURE_EL3) + && !(env->cp15.scr_el3 & SCR_PIEN)) { + pir =3D 0; + } else if (el =3D=3D 2) { + pire0 =3D env->cp15.pire0_el2; + } else if (!ptw->in_nv1) { + pire0 =3D env->cp15.pir_el[0]; + } + } + perm =3D perm_table[extract64(pir, pi_index * 4, 4)]; + + if (regime_has_2_ranges(mmu_idx)) { + int p_perm =3D perm; + int u_perm =3D perm_table[extract64(pire0, pi_index * 4, 4)]; + + if ((p_perm & (PAGE_EXEC | PAGE_GCS)) && + (u_perm & (PAGE_WRITE | PAGE_GCS))) { + p_perm &=3D ~(PAGE_RWX | PAGE_GCS); + u_perm &=3D ~(PAGE_RWX | PAGE_GCS); + } + if ((u_perm & (PAGE_RWX | PAGE_GCS)) && regime_is_pan(env, mmu_idx= )) { + p_perm &=3D ~(PAGE_READ | PAGE_WRITE); + } + perm =3D regime_is_user(env, mmu_idx) ? u_perm : p_perm; + } + + if (in_pa !=3D out_pa) { + switch (in_pa) { + case ARMSS_Root: + /* + * R_ZWRVD: permission fault for insn fetched from non-Root, + * I_WWBFB: SIF has no effect in EL3. + */ + perm &=3D ~(PAGE_EXEC | PAGE_GCS); + break; + case ARMSS_Realm: + /* + * R_PKTDS: permission fault for insn fetched from non-Realm, + * for Realm EL2 or EL2&0. The corresponding fault for EL1&0 + * happens during any stage2 translation. + */ + if (el =3D=3D 2) { + perm &=3D ~(PAGE_EXEC | PAGE_GCS); + } + break; + case ARMSS_Secure: + if (env->cp15.scr_el3 & SCR_SIF) { + perm &=3D ~(PAGE_EXEC | PAGE_GCS); + } + break; + default: + /* Input NonSecure must have output NonSecure. */ + g_assert_not_reached(); + } + } + + if (perm & PAGE_WXN) { + perm &=3D ~PAGE_EXEC; + } + + /* TODO: FEAT_GCS */ + + return perm & PAGE_RWX; +} + static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va, ARMMMUIdx mmu_idx) { @@ -1677,7 +1777,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Tr= anslate *ptw, int32_t stride; int addrsize, inputsize, outputsize; uint64_t tcr =3D regime_tcr(env, mmu_idx); - int ap, xn, pxn; + int ap; uint32_t el =3D regime_el(env, mmu_idx); uint64_t descaddrmask; bool aarch64 =3D arm_el_is_aa64(env, el); @@ -2011,7 +2111,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Tr= anslate *ptw, out_space =3D ARMSS_NonSecure; result->f.prot =3D get_S2prot_noexecute(ap); } else { - xn =3D extract64(attrs, 53, 2); + int xn =3D extract64(attrs, 53, 2); result->f.prot =3D get_S2prot(env, ap, xn, ptw->in_s1_is_el0); } =20 @@ -2027,7 +2127,6 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Tr= anslate *ptw, int nse, ns =3D extract32(attrs, 5, 1); uint8_t attrindx; uint64_t mair; - int user_rw, prot_rw; =20 switch (out_space) { case ARMSS_Root: @@ -2076,33 +2175,51 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1= Translate *ptw, default: g_assert_not_reached(); } - xn =3D extract64(attrs, 54, 1); - pxn =3D extract64(attrs, 53, 1); =20 - if (el =3D=3D 1 && ptw->in_nv1) { + if (param.pie) { + int pi =3D extract64(attrs, 6, 1) + | (extract64(attrs, 51, 1) << 1) + | (extract64(attrs, 53, 2) << 2); + int po =3D extract64(attrs, 60, 3); /* - * With FEAT_NV, when HCR_EL2.{NV,NV1} =3D=3D {1,1}, the block= /page - * descriptor bit 54 holds PXN, 53 is RES0, and the effective = value - * of UXN is 0. Similarly for bits 59 and 60 in table descript= ors - * (which we have already folded into bits 53 and 54 of attrs). - * AP[1] (descriptor bit 6, our ap bit 0) is treated as 0. - * Similarly, APTable[0] from the table descriptor is treated = as 0; - * we already folded this into AP[1] and squashing that to 0 d= oes - * the right thing. + * Note that we modified ptw->in_space earlier for NSTable, but + * result->f.attrs retains a copy of the original security spa= ce. */ - pxn =3D xn; - xn =3D 0; - ap &=3D ~1; - } + result->f.prot =3D get_S1prot_indirect(env, ptw, mmu_idx, pi, = po, + result->f.attrs.space, + out_space); + } else { + int xn =3D extract64(attrs, 54, 1); + int pxn =3D extract64(attrs, 53, 1); + int user_rw, prot_rw; =20 - user_rw =3D simple_ap_to_rw_prot_is_user(ap, true); - prot_rw =3D simple_ap_to_rw_prot_is_user(ap, false); - /* - * Note that we modified ptw->in_space earlier for NSTable, but - * result->f.attrs retains a copy of the original security space. - */ - result->f.prot =3D get_S1prot(env, mmu_idx, aarch64, user_rw, prot= _rw, - xn, pxn, result->f.attrs.space, out_sp= ace); + if (el =3D=3D 1 && ptw->in_nv1) { + /* + * With FEAT_NV, when HCR_EL2.{NV,NV1} =3D=3D {1,1}, + * the block/page descriptor bit 54 holds PXN, + * 53 is RES0, and the effective value of UXN is 0. + * Similarly for bits 59 and 60 in table descriptors + * (which we have already folded into bits 53 and 54 of at= trs). + * AP[1] (descriptor bit 6, our ap bit 0) is treated as 0. + * Similarly, APTable[0] from the table descriptor is trea= ted + * as 0; we already folded this into AP[1] and squashing + * that to 0 does the right thing. + */ + pxn =3D xn; + xn =3D 0; + ap &=3D ~1; + } + + user_rw =3D simple_ap_to_rw_prot_is_user(ap, true); + prot_rw =3D simple_ap_to_rw_prot_is_user(ap, false); + /* + * Note that we modified ptw->in_space earlier for NSTable, but + * result->f.attrs retains a copy of the original security spa= ce. + */ + result->f.prot =3D get_S1prot(env, mmu_idx, aarch64, + user_rw, prot_rw, xn, pxn, + result->f.attrs.space, out_space); + } =20 /* Index into MAIR registers for cache attributes */ attrindx =3D extract32(attrs, 2, 3); --=20 2.43.0