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([71.212.157.132]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2698018a472sm138554795ad.58.2025.09.22.11.53.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Sep 2025 11:53:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758567197; x=1759171997; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=oWIuoMSiqJF4N4o+nZ0K+Ku+FE0azEDKcujW4yFEPEA=; b=u6CLfyD1pPdkC9zQ3VzVGrl3xfihIdDcnR1Yg21fnQ2z81zdjmO+CMA6HS614B8SFG M7NJeeoHzyJOuQU282zBQnXXD8tWoRBExOzGVPHecYz9usI8krJeGzUGvxuS4EuGuzco bWmym+odK0ccrxkjEPgkGF0dyaFCxtQy6tpq1ofCQ89oSK6vAy3wLhnUr/r+6Xy51Muv 7mxc1Qdy/maAbpNGlvH1RSOgmE2fPm1VSw8e6+P2CydnaawckdHsP2GZnAyxHMkQKs7A +MrAK2MjVfI5fEHxdJA+VberUc1h466U2VVZgLN4fSS50iL2pi4l3gCRRV4QV7h8gnzC BlOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758567197; x=1759171997; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oWIuoMSiqJF4N4o+nZ0K+Ku+FE0azEDKcujW4yFEPEA=; b=OEVk+AXEAfDFM28nnAZDS8Rr5Gq4QIVUMnSZIlsBSDG+DTIeH/paM1Ob7/loeUs6VC ojdSNWolIzH6i2cArYe/q0UOkldORmqneBsjGZ2G90TYmCf6qi+6g9V4kZ0icucVQ3wV /3p3SvNVcxDFGC4ndF646LIR7eDhrXn/VWIMrz/yvbkWFZh2Kwe+i9M2/xVJAxXr5P6/ WFUdwdDpso86+lshO5kk3L5z0CAqtZZ58uqUYXEejoZAbMMIMvFxj5En9s4qf34OTIAi PM0j5i6dTrtwtpGxrZ+8Z9+IgMgTZtwqHjQpUxDRD9xknkiC30uw9+z0JuzFU65hEk4t 8oJQ== X-Gm-Message-State: AOJu0YxetCSKvgvr6lgoGyWS4Ghekv+1hZsRUOjJ3SPwrNVpua4joTrC 5dJ9WPvrH7RKzKY6Pvs12LUHIzEIqv6FuTjnln7XtAJEx1z8DgAeg2ute6+7b66rFwpZzG8beKq oNJqx X-Gm-Gg: ASbGncum8iHSOLSISup01KPZ3pgH4vtVqm6aGDcT0tb4Whnro8tPFmv705UJRSPnUA5 QMXDnCD70EAnWLO7B4bnDQYYzkrp5BtWngAaAcZdMBjb1U/cQC42kDlOyZBvByvup4sIg119vmf f/jClQAbJ89MvbCACVL7jbWdvcJ43YNKsbNQCrPMLIgCj2DEwAVQeS6V87oupvYRT8dwJE+ojEC ZAA+7P9c7zV//5ZrE0BvXa91cPxD1g7ZWfD8VrWyflJmxvYvxnr7TQqSD8iKDJSuQU7+pUPtiE/ zZd93/AbQej0/ZoX+yLM6IB9hO1ZYtIf48oex40tjpxeQ8s2U+FbPf/wXOgjWLs1+s+u8+C/aUk dpZ5PF/87dTa45orfz1O8xIJgZMAw X-Google-Smtp-Source: AGHT+IHQ8yqIpuAQK5OfMvs330q4027hPqWVvFRYu9qRAIabFv8sgYFsak3FJwKKkqmaWnpbwYalFA== X-Received: by 2002:a17:903:1b0b:b0:267:a942:788c with SMTP id d9443c01a7336-269ba3fa0afmr206941515ad.1.1758567197368; Mon, 22 Sep 2025 11:53:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Pierrick Bouvier Subject: [PATCH v5 45/76] target/arm: Split {full,core}_a64_user_mem_index Date: Mon, 22 Sep 2025 11:48:53 -0700 Message-ID: <20250922184924.2754205-46-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250922184924.2754205-1-richard.henderson@linaro.org> References: <20250922184924.2754205-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758567464567116600 Content-Type: text/plain; charset="utf-8" Separate get_a64_user_mem_index into two separate functions, one which returns the full ARMMMUIdx and one which returns the core mmu_idx. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 24 +++++++++++++++--------- 1 file changed, 15 insertions(+), 9 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index ce5d597c93..f0331830b5 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -93,7 +93,7 @@ void a64_translate_init(void) } =20 /* - * Return the core mmu_idx to use for A64 load/store insns which + * Return the full arm mmu_idx to use for A64 load/store insns which * have a "unprivileged load/store" variant. Those insns access * EL0 if executed from an EL which has control over EL0 (usually * EL1) but behave like normal loads and stores if executed from @@ -103,7 +103,7 @@ void a64_translate_init(void) * normal encoding (in which case we will return the same * thing as get_mem_index(). */ -static int get_a64_user_mem_index(DisasContext *s, bool unpriv) +static ARMMMUIdx full_a64_user_mem_index(DisasContext *s, bool unpriv) { /* * If AccType_UNPRIV is not used, the insn uses AccType_NORMAL, @@ -130,7 +130,13 @@ static int get_a64_user_mem_index(DisasContext *s, boo= l unpriv) g_assert_not_reached(); } } - return arm_to_core_mmu_idx(useridx); + return useridx; +} + +/* Return the core mmu_idx per above. */ +static int core_a64_user_mem_index(DisasContext *s, bool unpriv) +{ + return arm_to_core_mmu_idx(full_a64_user_mem_index(s, unpriv)); } =20 static void set_btype_raw(int val) @@ -3577,7 +3583,7 @@ static void op_addr_ldst_imm_pre(DisasContext *s, arg= _ldst_imm *a, if (!a->p) { tcg_gen_addi_i64(*dirty_addr, *dirty_addr, offset); } - memidx =3D get_a64_user_mem_index(s, a->unpriv); + memidx =3D core_a64_user_mem_index(s, a->unpriv); *clean_addr =3D gen_mte_check1_mmuidx(s, *dirty_addr, is_store, a->w || a->rn !=3D 31, mop, a->unpriv, memidx); @@ -3598,7 +3604,7 @@ static bool trans_STR_i(DisasContext *s, arg_ldst_imm= *a) { bool iss_sf, iss_valid =3D !a->w; TCGv_i64 clean_addr, dirty_addr, tcg_rt; - int memidx =3D get_a64_user_mem_index(s, a->unpriv); + int memidx =3D core_a64_user_mem_index(s, a->unpriv); MemOp mop =3D finalize_memop(s, a->sz + a->sign * MO_SIGN); =20 op_addr_ldst_imm_pre(s, a, &clean_addr, &dirty_addr, a->imm, true, mop= ); @@ -3616,7 +3622,7 @@ static bool trans_LDR_i(DisasContext *s, arg_ldst_imm= *a) { bool iss_sf, iss_valid =3D !a->w; TCGv_i64 clean_addr, dirty_addr, tcg_rt; - int memidx =3D get_a64_user_mem_index(s, a->unpriv); + int memidx =3D core_a64_user_mem_index(s, a->unpriv); MemOp mop =3D finalize_memop(s, a->sz + a->sign * MO_SIGN); =20 op_addr_ldst_imm_pre(s, a, &clean_addr, &dirty_addr, a->imm, false, mo= p); @@ -4514,7 +4520,7 @@ static bool do_SET(DisasContext *s, arg_set *a, bool = is_epilogue, return false; } =20 - memidx =3D get_a64_user_mem_index(s, a->unpriv); + memidx =3D core_a64_user_mem_index(s, a->unpriv); =20 /* * We pass option_a =3D=3D true, matching our implementation; @@ -4568,8 +4574,8 @@ static bool do_CPY(DisasContext *s, arg_cpy *a, bool = is_epilogue, CpyFn fn) return false; } =20 - rmemidx =3D get_a64_user_mem_index(s, runpriv); - wmemidx =3D get_a64_user_mem_index(s, wunpriv); + rmemidx =3D core_a64_user_mem_index(s, runpriv); + wmemidx =3D core_a64_user_mem_index(s, wunpriv); =20 /* * We pass option_a =3D=3D true, matching our implementation; --=20 2.43.0