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Enable SCR_GCSEN in scr_write. Enable HCRX_GCSEN in hcrx_write. Default HCRX_GCSEN on if EL2 disabled. Add the GCSCR* and GCSPR* registers. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/cpregs.h | 2 + target/arm/cpu-features.h | 5 +++ target/arm/cpu.h | 12 +++++ target/arm/internals.h | 3 ++ target/arm/cpregs-gcs.c | 95 +++++++++++++++++++++++++++++++++++++++ target/arm/cpu.c | 3 ++ target/arm/helper.c | 10 +++++ target/arm/meson.build | 2 + 8 files changed, 132 insertions(+) create mode 100644 target/arm/cpregs-gcs.c diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index f48c4df30f..bd2121a336 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -779,6 +779,8 @@ typedef enum FGTBit { DO_BIT(HFGRTR, VBAR_EL1), DO_BIT(HFGRTR, ICC_IGRPENN_EL1), DO_BIT(HFGRTR, ERRIDR_EL1), + DO_REV_BIT(HFGRTR, NGCS_EL0), + DO_REV_BIT(HFGRTR, NGCS_EL1), DO_REV_BIT(HFGRTR, NSMPRI_EL1), DO_REV_BIT(HFGRTR, NTPIDR2_EL0), DO_REV_BIT(HFGRTR, NPIRE0_EL1), diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 30226814bb..4a35cf6b69 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -729,6 +729,11 @@ static inline bool isar_feature_aa64_nmi(const ARMISAR= egisters *id) return FIELD_EX64_IDREG(id, ID_AA64PFR1, NMI) !=3D 0; } =20 +static inline bool isar_feature_aa64_gcs(const ARMISARegisters *id) +{ + return FIELD_EX64_IDREG(id, ID_AA64PFR1, GCS) !=3D 0; +} + static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id) { return FIELD_SEX64_IDREG(id, ID_AA64MMFR0, TGRAN4) >=3D 1; diff --git a/target/arm/cpu.h b/target/arm/cpu.h index d5a45e9b43..14a08d2f99 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -580,6 +580,9 @@ typedef struct CPUArchState { =20 /* NV2 register */ uint64_t vncr_el2; + + uint64_t gcscr_el[4]; /* GCSCRE0_EL1, GCSCR_EL[123] */ + uint64_t gcspr_el[4]; /* GCSPR_EL[0123] */ } cp15; =20 struct { @@ -1717,6 +1720,7 @@ static inline void xpsr_write(CPUARMState *env, uint3= 2_t val, uint32_t mask) #define SCR_ENAS0 (1ULL << 36) #define SCR_ADEN (1ULL << 37) #define SCR_HXEN (1ULL << 38) +#define SCR_GCSEN (1ULL << 39) #define SCR_TRNDR (1ULL << 40) #define SCR_ENTP2 (1ULL << 41) #define SCR_TCR2EN (1ULL << 43) @@ -1725,6 +1729,14 @@ static inline void xpsr_write(CPUARMState *env, uint= 32_t val, uint32_t mask) #define SCR_GPF (1ULL << 48) #define SCR_NSE (1ULL << 62) =20 +/* GCSCR_ELx fields */ +#define GCSCR_PCRSEL (1ULL << 0) +#define GCSCR_RVCHKEN (1ULL << 5) +#define GCSCR_EXLOCKEN (1ULL << 6) +#define GCSCR_PUSHMEN (1ULL << 8) +#define GCSCR_STREN (1ULL << 9) +#define GCSCRE0_NTR (1ULL << 10) + /* Return the current FPSCR value. */ uint32_t vfp_get_fpscr(CPUARMState *env); void vfp_set_fpscr(CPUARMState *env, uint32_t val); diff --git a/target/arm/internals.h b/target/arm/internals.h index dc6bf3548e..f72e95a5ba 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -251,6 +251,7 @@ FIELD(VSTCR, SA, 30, 1) #define HCRX_MSCEN (1ULL << 11) #define HCRX_TCR2EN (1ULL << 14) #define HCRX_SCTLR2EN (1ULL << 15) +#define HCRX_GCSEN (1ULL << 22) =20 #define HPFAR_NS (1ULL << 63) =20 @@ -1778,6 +1779,8 @@ void define_tlb_insn_regs(ARMCPU *cpu); void define_at_insn_regs(ARMCPU *cpu); /* Add the cpreg definitions for PM cpregs */ void define_pm_cpregs(ARMCPU *cpu); +/* Add the cpreg definitions for GCS cpregs */ +void define_gcs_cpregs(ARMCPU *cpu); =20 /* Effective value of MDCR_EL2 */ static inline uint64_t arm_mdcr_el2_eff(CPUARMState *env) diff --git a/target/arm/cpregs-gcs.c b/target/arm/cpregs-gcs.c new file mode 100644 index 0000000000..1ff041811d --- /dev/null +++ b/target/arm/cpregs-gcs.c @@ -0,0 +1,95 @@ +/* + * QEMU ARM CP Register GCS regiters and instructions + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/timer.h" +#include "exec/icount.h" +#include "hw/irq.h" +#include "cpu.h" +#include "cpu-features.h" +#include "cpregs.h" +#include "internals.h" + + +static CPAccessResult access_gcs(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + if (arm_current_el(env) < 3 + && arm_feature(env, ARM_FEATURE_EL3) + && !(env->cp15.scr_el3 & SCR_GCSEN)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + +static CPAccessResult access_gcs_el0(CPUARMState *env, const ARMCPRegInfo = *ri, + bool isread) +{ + if (arm_current_el(env) =3D=3D 0 && !(env->cp15.gcscr_el[0] & GCSCRE0_= NTR)) { + return CP_ACCESS_TRAP_EL1; + } + return access_gcs(env, ri, isread); +} + +static void gcspr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* + * Bits [2:0] are RES0, so we might as well clear them now, + * rather than upon each usage a-la GetCurrentGCSPointer. + */ + raw_write(env, ri, value & ~7); +} + +static const ARMCPRegInfo gcs_reginfo[] =3D { + { .name =3D "GCSCRE0_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 5, .opc2 =3D 2, + .access =3D PL1_RW, .accessfn =3D access_gcs, .fgt =3D FGT_NGCS_EL0, + .fieldoffset =3D offsetof(CPUARMState, cp15.gcscr_el[0]) }, + { .name =3D "GCSCR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 5, .opc2 =3D 0, + .access =3D PL1_RW, .accessfn =3D access_gcs, .fgt =3D FGT_NGCS_EL1, + .nv2_redirect_offset =3D 0x8d0 | NV2_REDIR_NV1, + .vhe_redir_to_el2 =3D ENCODE_AA64_CP_REG(3, 4, 2, 5, 0), + .vhe_redir_to_el01 =3D ENCODE_AA64_CP_REG(3, 5, 2, 5, 0), + .fieldoffset =3D offsetof(CPUARMState, cp15.gcscr_el[1]) }, + { .name =3D "GCSCR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 5, .opc2 =3D 0, + .access =3D PL2_RW, .accessfn =3D access_gcs, + .fieldoffset =3D offsetof(CPUARMState, cp15.gcscr_el[2]) }, + { .name =3D "GCSCR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 2, .crm =3D 5, .opc2 =3D 0, + .access =3D PL3_RW, + .fieldoffset =3D offsetof(CPUARMState, cp15.gcscr_el[3]) }, + + { .name =3D "GCSPR_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 2, .crm =3D 5, .opc2 =3D 1, + .access =3D PL0_R | PL1_W, .accessfn =3D access_gcs_el0, + .fgt =3D FGT_NGCS_EL0, .writefn =3D gcspr_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.gcspr_el[0]) }, + { .name =3D "GCSPR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 5, .opc2 =3D 1, + .access =3D PL1_RW, .accessfn =3D access_gcs, + .fgt =3D FGT_NGCS_EL1, .writefn =3D gcspr_write, + .nv2_redirect_offset =3D 0x8c0 | NV2_REDIR_NV1, + .vhe_redir_to_el2 =3D ENCODE_AA64_CP_REG(3, 4, 2, 5, 1), + .vhe_redir_to_el01 =3D ENCODE_AA64_CP_REG(3, 5, 2, 5, 1), + .fieldoffset =3D offsetof(CPUARMState, cp15.gcspr_el[1]) }, + { .name =3D "GCSPR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 5, .opc2 =3D 1, + .access =3D PL2_RW, .accessfn =3D access_gcs, .writefn =3D gcspr_wri= te, + .fieldoffset =3D offsetof(CPUARMState, cp15.gcspr_el[2]) }, + { .name =3D "GCSPR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 2, .crm =3D 5, .opc2 =3D 1, + .access =3D PL3_RW, .writefn =3D gcspr_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.gcspr_el[2]) }, +}; + +void define_gcs_cpregs(ARMCPU *cpu) +{ + if (cpu_isar_feature(aa64_gcs, cpu)) { + define_arm_cp_regs(cpu, gcs_reginfo); + } +} diff --git a/target/arm/cpu.c b/target/arm/cpu.c index d4bc2e6a92..aab7250399 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -629,6 +629,9 @@ void arm_emulate_firmware_reset(CPUState *cpustate, int= target_el) if (cpu_isar_feature(aa64_fgt, cpu)) { env->cp15.scr_el3 |=3D SCR_FGTEN; } + if (cpu_isar_feature(aa64_gcs, cpu)) { + env->cp15.scr_el3 |=3D SCR_GCSEN; + } if (cpu_isar_feature(aa64_tcr2, cpu)) { env->cp15.scr_el3 |=3D SCR_TCR2EN; } diff --git a/target/arm/helper.c b/target/arm/helper.c index 65f38727d6..3b9e7a822e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -766,6 +766,9 @@ static void scr_write(CPUARMState *env, const ARMCPRegI= nfo *ri, uint64_t value) if (cpu_isar_feature(aa64_ecv, cpu)) { valid_mask |=3D SCR_ECVEN; } + if (cpu_isar_feature(aa64_gcs, cpu)) { + valid_mask |=3D SCR_GCSEN; + } if (cpu_isar_feature(aa64_tcr2, cpu)) { valid_mask |=3D SCR_TCR2EN; } @@ -3948,6 +3951,9 @@ static void hcrx_write(CPUARMState *env, const ARMCPR= egInfo *ri, if (cpu_isar_feature(aa64_sctlr2, cpu)) { valid_mask |=3D HCRX_SCTLR2EN; } + if (cpu_isar_feature(aa64_gcs, cpu)) { + valid_mask |=3D HCRX_GCSEN; + } =20 /* Clear RES0 bits. */ env->cp15.hcrx_el2 =3D value & valid_mask; @@ -4018,6 +4024,9 @@ uint64_t arm_hcrx_el2_eff(CPUARMState *env) if (cpu_isar_feature(aa64_sctlr2, cpu)) { hcrx |=3D HCRX_SCTLR2EN; } + if (cpu_isar_feature(aa64_gcs, cpu)) { + hcrx |=3D HCRX_GCSEN; + } return hcrx; } if (arm_feature(env, ARM_FEATURE_EL3) && !(env->cp15.scr_el3 & SCR_HXE= N)) { @@ -7247,6 +7256,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) } =20 define_pm_cpregs(cpu); + define_gcs_cpregs(cpu); } =20 /* diff --git a/target/arm/meson.build b/target/arm/meson.build index 91630a1f72..8c82304fde 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -27,6 +27,7 @@ arm_user_ss.add(when: 'TARGET_AARCH64', if_false: files( 'cpu32-stubs.c', )) arm_user_ss.add(files( + 'cpregs-gcs.c', 'cpregs-pmu.c', 'debug_helper.c', 'helper.c', @@ -42,6 +43,7 @@ arm_common_system_ss.add(files( 'arch_dump.c', 'arm-powerctl.c', 'cortex-regs.c', + 'cpregs-gcs.c', 'cpregs-pmu.c', 'debug_helper.c', 'helper.c', --=20 2.43.0