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Mon, 22 Sep 2025 11:50:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Pierrick Bouvier Subject: [PATCH v5 33/76] target/arm: Implement gcs bit for data abort Date: Mon, 22 Sep 2025 11:48:41 -0700 Message-ID: <20250922184924.2754205-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250922184924.2754205-1-richard.henderson@linaro.org> References: <20250922184924.2754205-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758567288308116600 Content-Type: text/plain; charset="utf-8" Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/tcg/tlb_helper.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c index ae2acd6727..f1983a5732 100644 --- a/target/arm/tcg/tlb_helper.c +++ b/target/arm/tcg/tlb_helper.c @@ -28,7 +28,7 @@ static inline uint64_t merge_syn_data_abort(uint32_t temp= late_syn, ARMMMUFaultInfo *fi, unsigned int target_el, bool same_el, bool is_write, - int fsc) + int fsc, bool gcs) { uint64_t syn; =20 @@ -78,6 +78,7 @@ static inline uint64_t merge_syn_data_abort(uint32_t temp= late_syn, =20 /* Form ISS2 at the top of the syndrome. */ syn |=3D (uint64_t)fi->dirtybit << 37; + syn |=3D (uint64_t)gcs << 40; =20 return syn; } @@ -252,9 +253,10 @@ void arm_deliver_fault(ARMCPU *cpu, vaddr addr, syn =3D syn_insn_abort(same_el, fi->ea, fi->s1ptw, fsc); exc =3D EXCP_PREFETCH_ABORT; } else { + bool gcs =3D regime_is_gcs(core_to_arm_mmu_idx(env, mmu_idx)); syn =3D merge_syn_data_abort(env->exception.syndrome, fi, target_e= l, same_el, access_type =3D=3D MMU_DATA_ST= ORE, - fsc); + fsc, gcs); if (access_type =3D=3D MMU_DATA_STORE && arm_feature(env, ARM_FEATURE_V6)) { fsr |=3D (1 << 11); --=20 2.43.0