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Mon, 22 Sep 2025 11:49:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pierrick Bouvier Subject: [PATCH v5 26/76] target/arm: Remove unused env argument from regime_is_user Date: Mon, 22 Sep 2025 11:48:34 -0700 Message-ID: <20250922184924.2754205-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250922184924.2754205-1-richard.henderson@linaro.org> References: <20250922184924.2754205-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758567148914116601 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/internals.h | 2 +- target/arm/helper.c | 2 +- target/arm/ptw.c | 16 ++++++++-------- 3 files changed, 10 insertions(+), 10 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index b180499ecf..ad5584eb0b 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1032,7 +1032,7 @@ static inline bool regime_is_stage2(ARMMMUIdx mmu_idx) return mmu_idx =3D=3D ARMMMUIdx_Stage2 || mmu_idx =3D=3D ARMMMUIdx_Sta= ge2_S; } =20 -static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx) +static inline bool regime_is_user(ARMMMUIdx mmu_idx) { switch (mmu_idx) { case ARMMMUIdx_E10_0: diff --git a/target/arm/helper.c b/target/arm/helper.c index 83a675cc22..c0e808a9e8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9436,7 +9436,7 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, = uint64_t va, ds =3D extract64(tcr, 59, 1); =20 if (e0pd && cpu_isar_feature(aa64_e0pd, cpu) && - regime_is_user(env, mmu_idx)) { + regime_is_user(mmu_idx)) { epd =3D true; } =20 diff --git a/target/arm/ptw.c b/target/arm/ptw.c index db51e55cd2..b72c1fc348 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -964,7 +964,7 @@ static int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mm= u_idx, int ap, int domain_prot) { return ap_to_rw_prot_is_user(env, mmu_idx, ap, domain_prot, - regime_is_user(env, mmu_idx)); + regime_is_user(mmu_idx)); } =20 /* @@ -990,7 +990,7 @@ static int simple_ap_to_rw_prot_is_user(int ap, bool is= _user) =20 static int simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int a= p) { - return simple_ap_to_rw_prot_is_user(ap, regime_is_user(env, mmu_idx)); + return simple_ap_to_rw_prot_is_user(ap, regime_is_user(mmu_idx)); } =20 static bool get_phys_addr_v5(CPUARMState *env, S1Translate *ptw, @@ -1376,7 +1376,7 @@ static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu= _idx, bool is_aa64, ARMSecuritySpace in_pa, ARMSecuritySpace out_pa) { ARMCPU *cpu =3D env_archcpu(env); - bool is_user =3D regime_is_user(env, mmu_idx); + bool is_user =3D regime_is_user(mmu_idx); bool have_wxn; int wxn =3D 0; =20 @@ -1538,7 +1538,7 @@ static int get_S1prot_indirect(CPUARMState *env, S1Tr= anslate *ptw, if ((u_perm & (PAGE_RWX | PAGE_GCS)) && regime_is_pan(mmu_idx)) { p_perm &=3D ~(PAGE_READ | PAGE_WRITE); } - perm =3D regime_is_user(env, mmu_idx) ? u_perm : p_perm; + perm =3D regime_is_user(mmu_idx) ? u_perm : p_perm; } =20 if (in_pa !=3D out_pa) { @@ -2389,7 +2389,7 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t mask; uint32_t base; ARMMMUIdx mmu_idx =3D ptw->in_mmu_idx; - bool is_user =3D regime_is_user(env, mmu_idx); + bool is_user =3D regime_is_user(mmu_idx); =20 if (regime_translation_disabled(env, mmu_idx, ptw->in_space)) { /* MPU disabled. */ @@ -2556,7 +2556,7 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, ARMCPU *cpu =3D env_archcpu(env); int n; ARMMMUIdx mmu_idx =3D ptw->in_mmu_idx; - bool is_user =3D regime_is_user(env, mmu_idx); + bool is_user =3D regime_is_user(mmu_idx); bool secure =3D arm_space_is_secure(ptw->in_space); =20 result->f.phys_addr =3D address; @@ -2776,7 +2776,7 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t add= ress, * memory system to use a subpage. */ ARMCPU *cpu =3D env_archcpu(env); - bool is_user =3D regime_is_user(env, mmu_idx); + bool is_user =3D regime_is_user(mmu_idx); int n; int matchregion =3D -1; bool hit =3D false; @@ -3656,7 +3656,7 @@ static bool get_phys_addr_nogpc(CPUARMState *env, S1T= ranslate *ptw, break; } =20 - result->f.attrs.user =3D regime_is_user(env, mmu_idx); + result->f.attrs.user =3D regime_is_user(mmu_idx); =20 /* * Fast Context Switch Extension. This doesn't exist at all in v8. --=20 2.43.0