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Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/internals.h | 1 + target/arm/ptw.c | 16 ++++++++++++++++ target/arm/tcg/tlb_helper.c | 12 +++++++++--- 3 files changed, 26 insertions(+), 3 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 0ebcf566ec..a2ee5f8739 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -752,6 +752,7 @@ struct ARMMMUFaultInfo { bool s1ptw; bool s1ns; bool ea; + bool dirtybit; /* FEAT_S1PIE, FEAT_S2PIE */ }; =20 /** diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 6dcd3adbdf..be3629a745 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2311,6 +2311,22 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1T= ranslate *ptw, goto do_fault; } =20 + /* S1PIE and S2PIE both have a bit for software dirty page tracking. */ + if (access_type =3D=3D MMU_DATA_STORE && param.pie) { + /* + * For S1PIE, bit 7 is nDirty and both HA and HD are checked. + * For S2PIE, bit 7 is Dirty and only HD is checked. + */ + bool bit7 =3D extract64(attrs, 7, 1); + if (regime_is_stage2(mmu_idx) + ? !bit7 && !param.hd + : bit7 && !(param.ha && param.hd)) { + fi->type =3D ARMFault_Permission; + fi->dirtybit =3D true; + goto do_fault; + } + } + /* If FEAT_HAFDBS has made changes, update the PTE. */ if (new_descriptor !=3D descriptor) { new_descriptor =3D arm_casq_ptw(env, descriptor, new_descriptor, p= tw, fi); diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c index 23c72a99f5..ae2acd6727 100644 --- a/target/arm/tcg/tlb_helper.c +++ b/target/arm/tcg/tlb_helper.c @@ -24,13 +24,13 @@ bool arm_s1_regime_using_lpae_format(CPUARMState *env, = ARMMMUIdx mmu_idx) return regime_using_lpae_format(env, mmu_idx); } =20 -static inline uint32_t merge_syn_data_abort(uint32_t template_syn, +static inline uint64_t merge_syn_data_abort(uint32_t template_syn, ARMMMUFaultInfo *fi, unsigned int target_el, bool same_el, bool is_write, int fsc) { - uint32_t syn; + uint64_t syn; =20 /* * ISV is only set for stage-2 data aborts routed to EL2 and @@ -75,6 +75,10 @@ static inline uint32_t merge_syn_data_abort(uint32_t tem= plate_syn, /* Merge the runtime syndrome with the template syndrome. */ syn |=3D template_syn; } + + /* Form ISS2 at the top of the syndrome. */ + syn |=3D (uint64_t)fi->dirtybit << 37; + return syn; } =20 @@ -176,7 +180,9 @@ void arm_deliver_fault(ARMCPU *cpu, vaddr addr, int target_el =3D exception_target_el(env); int current_el =3D arm_current_el(env); bool same_el; - uint32_t syn, exc, fsr, fsc; + uint32_t exc, fsr, fsc; + uint64_t syn; + /* * We know this must be a data or insn abort, and that * env->exception.syndrome contains the template syndrome set --=20 2.43.0