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Mon, 22 Sep 2025 02:37:19 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: Palmer Dabbelt , Alexandre Iooss , Mahmoud Mandour , qemu-riscv@nongnu.org, Daniel Henrique Barboza , Thomas Huth , Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Alistair Francis , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Weiwei Li , Pierrick Bouvier , Liu Zhiwei , Richard Henderson Subject: [PATCH 10/25] include/semihosting/common-semi: extract common_semi API Date: Mon, 22 Sep 2025 10:36:55 +0100 Message-ID: <20250922093711.2768983-11-alex.bennee@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20250922093711.2768983-1-alex.bennee@linaro.org> References: <20250922093711.2768983-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758534218587116600 From: Pierrick Bouvier We transform target/{arm,riscv}/common-semi-target.h headers to proper compilation units, and use them in arm-compat-semi.c. This way, we can include only the declaration header (which is target agnostic), and selectively link the appropriate implementation based on current target. Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Message-ID: <20250822150058.18692-8-pierrick.bouvier@linaro.org> Signed-off-by: Alex Benn=C3=A9e --- include/semihosting/common-semi.h | 6 ++++++ semihosting/arm-compat-semi.c | 3 +-- ...mon-semi-target.h =3D> common-semi-target.c} | 20 +++++++++---------- ...mon-semi-target.h =3D> common-semi-target.c} | 19 +++++++++--------- target/arm/meson.build | 4 ++++ target/riscv/meson.build | 4 ++++ 6 files changed, 33 insertions(+), 23 deletions(-) rename target/arm/{common-semi-target.h =3D> common-semi-target.c} (64%) rename target/riscv/{common-semi-target.h =3D> common-semi-target.c} (59%) diff --git a/include/semihosting/common-semi.h b/include/semihosting/common= -semi.h index 0a91db7c414..aa511a46f42 100644 --- a/include/semihosting/common-semi.h +++ b/include/semihosting/common-semi.h @@ -35,5 +35,11 @@ #define COMMON_SEMI_H =20 void do_common_semihosting(CPUState *cs); +uint64_t common_semi_arg(CPUState *cs, int argno); +void common_semi_set_ret(CPUState *cs, uint64_t ret); +bool is_64bit_semihosting(CPUArchState *env); +bool common_semi_sys_exit_is_extended(CPUState *cs); +uint64_t common_semi_stack_bottom(CPUState *cs); +bool common_semi_has_synccache(CPUArchState *env); =20 #endif /* COMMON_SEMI_H */ diff --git a/semihosting/arm-compat-semi.c b/semihosting/arm-compat-semi.c index 26263a06b7a..604a69e3646 100644 --- a/semihosting/arm-compat-semi.c +++ b/semihosting/arm-compat-semi.c @@ -174,8 +174,7 @@ static LayoutInfo common_semi_find_bases(CPUState *cs) =20 #endif =20 -#include "cpu.h" -#include "common-semi-target.h" +#include "semihosting/common-semi.h" =20 /* * Read the input value from the argument block; fail the semihosting diff --git a/target/arm/common-semi-target.h b/target/arm/common-semi-targe= t.c similarity index 64% rename from target/arm/common-semi-target.h rename to target/arm/common-semi-target.c index 6775a270aaa..2b77ce9c17b 100644 --- a/target/arm/common-semi-target.h +++ b/target/arm/common-semi-target.c @@ -7,12 +7,12 @@ * SPDX-License-Identifier: GPL-2.0-or-later */ =20 -#ifndef TARGET_ARM_COMMON_SEMI_TARGET_H -#define TARGET_ARM_COMMON_SEMI_TARGET_H - +#include "qemu/osdep.h" +#include "cpu.h" +#include "semihosting/common-semi.h" #include "target/arm/cpu-qom.h" =20 -static inline uint64_t common_semi_arg(CPUState *cs, int argno) +uint64_t common_semi_arg(CPUState *cs, int argno) { ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; @@ -23,7 +23,7 @@ static inline uint64_t common_semi_arg(CPUState *cs, int = argno) } } =20 -static inline void common_semi_set_ret(CPUState *cs, uint64_t ret) +void common_semi_set_ret(CPUState *cs, uint64_t ret) { ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; @@ -34,27 +34,25 @@ static inline void common_semi_set_ret(CPUState *cs, ui= nt64_t ret) } } =20 -static inline bool common_semi_sys_exit_is_extended(CPUState *cs) +bool common_semi_sys_exit_is_extended(CPUState *cs) { return is_a64(cpu_env(cs)); } =20 -static inline bool is_64bit_semihosting(CPUArchState *env) +bool is_64bit_semihosting(CPUArchState *env) { return is_a64(env); } =20 -static inline uint64_t common_semi_stack_bottom(CPUState *cs) +uint64_t common_semi_stack_bottom(CPUState *cs) { ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; return is_a64(env) ? env->xregs[31] : env->regs[13]; } =20 -static inline bool common_semi_has_synccache(CPUArchState *env) +bool common_semi_has_synccache(CPUArchState *env) { /* Ok for A64, invalid for A32/T32 */ return is_a64(env); } - -#endif diff --git a/target/riscv/common-semi-target.h b/target/riscv/common-semi-t= arget.c similarity index 59% rename from target/riscv/common-semi-target.h rename to target/riscv/common-semi-target.c index 663dedfdad2..aeaeb88d536 100644 --- a/target/riscv/common-semi-target.h +++ b/target/riscv/common-semi-target.c @@ -8,43 +8,42 @@ * SPDX-License-Identifier: GPL-2.0-or-later */ =20 -#ifndef TARGET_RISCV_COMMON_SEMI_TARGET_H -#define TARGET_RISCV_COMMON_SEMI_TARGET_H +#include "qemu/osdep.h" +#include "cpu.h" +#include "semihosting/common-semi.h" =20 -static inline uint64_t common_semi_arg(CPUState *cs, int argno) +uint64_t common_semi_arg(CPUState *cs, int argno) { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; return env->gpr[xA0 + argno]; } =20 -static inline void common_semi_set_ret(CPUState *cs, uint64_t ret) +void common_semi_set_ret(CPUState *cs, uint64_t ret) { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; env->gpr[xA0] =3D ret; } =20 -static inline bool is_64bit_semihosting(CPUArchState *env) +bool is_64bit_semihosting(CPUArchState *env) { return riscv_cpu_mxl(env) !=3D MXL_RV32; } =20 -static inline bool common_semi_sys_exit_is_extended(CPUState *cs) +bool common_semi_sys_exit_is_extended(CPUState *cs) { return is_64bit_semihosting(cpu_env(cs)); } =20 -static inline uint64_t common_semi_stack_bottom(CPUState *cs) +uint64_t common_semi_stack_bottom(CPUState *cs) { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; return env->gpr[xSP]; } =20 -static inline bool common_semi_has_synccache(CPUArchState *env) +bool common_semi_has_synccache(CPUArchState *env) { return true; } - -#endif diff --git a/target/arm/meson.build b/target/arm/meson.build index 914f1498fc5..638ee62525f 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -28,12 +28,16 @@ arm_user_ss.add(files( 'vfp_fpscr.c', 'el2-stubs.c', )) +arm_user_ss.add(when: 'CONFIG_ARM_COMPATIBLE_SEMIHOSTING', + if_true: files('common-semi-target.c')) =20 arm_common_system_ss.add(files('cpu.c')) arm_common_system_ss.add(when: 'TARGET_AARCH64', if_false: files( 'cpu32-stubs.c')) arm_common_system_ss.add(when: 'CONFIG_KVM', if_false: files('kvm-stub.c')) arm_common_system_ss.add(when: 'CONFIG_HVF', if_false: files('hvf-stub.c')) +arm_common_system_ss.add(when: 'CONFIG_ARM_COMPATIBLE_SEMIHOSTING', + if_true: files('common-semi-target.c')) arm_common_system_ss.add(files( 'arch_dump.c', 'arm-powerctl.c', diff --git a/target/riscv/meson.build b/target/riscv/meson.build index a4bd61e52a9..fdefe88ccdd 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -8,6 +8,10 @@ gen =3D [ =20 riscv_ss =3D ss.source_set() riscv_ss.add(gen) + +riscv_ss.add(when: 'CONFIG_ARM_COMPATIBLE_SEMIHOSTING', + if_true: files('common-semi-target.c')) + riscv_ss.add(files( 'cpu.c', 'cpu_helper.c', --=20 2.47.3