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Mon, 22 Sep 2025 02:37:22 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: Palmer Dabbelt , Alexandre Iooss , Mahmoud Mandour , qemu-riscv@nongnu.org, Daniel Henrique Barboza , Thomas Huth , Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Alistair Francis , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Weiwei Li , Pierrick Bouvier , Liu Zhiwei , Richard Henderson Subject: [PATCH 09/25] target/{arm, riscv}/common-semi-target: eradicate target_ulong Date: Mon, 22 Sep 2025 10:36:54 +0100 Message-ID: <20250922093711.2768983-10-alex.bennee@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20250922093711.2768983-1-alex.bennee@linaro.org> References: <20250922093711.2768983-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758534080527116600 From: Pierrick Bouvier We replace mechanically with uint64_t. There is no semantic change, and allows us to extract a proper API from this set of functions. Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Message-ID: <20250822150058.18692-7-pierrick.bouvier@linaro.org> Signed-off-by: Alex Benn=C3=A9e --- target/arm/common-semi-target.h | 6 +++--- target/riscv/common-semi-target.h | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/target/arm/common-semi-target.h b/target/arm/common-semi-targe= t.h index 7bb442f24ca..6775a270aaa 100644 --- a/target/arm/common-semi-target.h +++ b/target/arm/common-semi-target.h @@ -12,7 +12,7 @@ =20 #include "target/arm/cpu-qom.h" =20 -static inline target_ulong common_semi_arg(CPUState *cs, int argno) +static inline uint64_t common_semi_arg(CPUState *cs, int argno) { ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; @@ -23,7 +23,7 @@ static inline target_ulong common_semi_arg(CPUState *cs, = int argno) } } =20 -static inline void common_semi_set_ret(CPUState *cs, target_ulong ret) +static inline void common_semi_set_ret(CPUState *cs, uint64_t ret) { ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; @@ -44,7 +44,7 @@ static inline bool is_64bit_semihosting(CPUArchState *env) return is_a64(env); } =20 -static inline target_ulong common_semi_stack_bottom(CPUState *cs) +static inline uint64_t common_semi_stack_bottom(CPUState *cs) { ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; diff --git a/target/riscv/common-semi-target.h b/target/riscv/common-semi-t= arget.h index 7e6ea8da02c..663dedfdad2 100644 --- a/target/riscv/common-semi-target.h +++ b/target/riscv/common-semi-target.h @@ -11,14 +11,14 @@ #ifndef TARGET_RISCV_COMMON_SEMI_TARGET_H #define TARGET_RISCV_COMMON_SEMI_TARGET_H =20 -static inline target_ulong common_semi_arg(CPUState *cs, int argno) +static inline uint64_t common_semi_arg(CPUState *cs, int argno) { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; return env->gpr[xA0 + argno]; } =20 -static inline void common_semi_set_ret(CPUState *cs, target_ulong ret) +static inline void common_semi_set_ret(CPUState *cs, uint64_t ret) { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; @@ -35,7 +35,7 @@ static inline bool common_semi_sys_exit_is_extended(CPUSt= ate *cs) return is_64bit_semihosting(cpu_env(cs)); } =20 -static inline target_ulong common_semi_stack_bottom(CPUState *cs) +static inline uint64_t common_semi_stack_bottom(CPUState *cs) { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; --=20 2.47.3