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charset="utf-8" Invalidating the entire address space (i.e. range of [0, ~0ULL]) is a valid and required operation by vIOMMU implementations. However, such invalidations currently trigger an assertion unless they originate from device IOTLB invalidations. Although in recent Linux guests this case is not exercised by the VTD implementation due to various optimizations, the assertion will be hit by upcoming AMD vIOMMU changes to support DMA address translation. More specifically, when running a Linux guest with VFIO passthrough device, and a kernel that does not contain commmit 3f2571fed2fa ("iommu/amd: Remove redundant domain flush from attach_device()"). Remove the assertion altogether and adjust the range to ensure it does not cross notifier boundaries. Signed-off-by: Alejandro Jimenez Acked-by: Michael S. Tsirkin Acked-by: David Hildenbrand Acked-by: Peter Xu --- system/memory.c | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/system/memory.c b/system/memory.c index cf8cad6961156..5c6ccc5c57412 100644 --- a/system/memory.c +++ b/system/memory.c @@ -2044,13 +2044,9 @@ void memory_region_notify_iommu_one(IOMMUNotifier *n= otifier, return; } =20 - if (notifier->notifier_flags & IOMMU_NOTIFIER_DEVIOTLB_UNMAP) { - /* Crop (iova, addr_mask) to range */ - tmp.iova =3D MAX(tmp.iova, notifier->start); - tmp.addr_mask =3D MIN(entry_end, notifier->end) - tmp.iova; - } else { - assert(entry->iova >=3D notifier->start && entry_end <=3D notifier= ->end); - } + /* Crop (iova, addr_mask) to range */ + tmp.iova =3D MAX(tmp.iova, notifier->start); + tmp.addr_mask =3D MIN(entry_end, notifier->end) - tmp.iova; =20 if (event->type & notifier->notifier_flags) { notifier->notify(notifier, &tmp); --=20 2.43.5 From nobody Sun Sep 28 16:28:07 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Document the common parameters used when emulating AMD vIOMMU. Besides the two amd-iommu specific options: 'xtsup' and 'dma-remap', the the generic x86 IOMMU option 'intremap' is also included, since it is typically specified in QEMU command line examples and mailing list threads. Signed-off-by: Alejandro Jimenez --- qemu-options.hx | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/qemu-options.hx b/qemu-options.hx index 075f4be2e3e67..6615123e6a11a 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -1238,6 +1238,29 @@ SRST Accepts either the default root complex (pcie.0) or a pxb-pcie based root complex. =20 +``-device amd-iommu[,option=3D...]`` + Enables emulation of an AMD-Vi I/O Memory Management Unit (IOMMU). + Only available with ``-machine q35``, it supports the following option= s: + + ``dma-remap=3Don|off`` (default: off) + Support for DMA address translation and access permission checking= for + guests attaching passthrough devices to paging domains, using the = AMD v1 + I/O Page Table format. This enables ``-device vfio-pci,...`` to wo= rk + correctly with a guest using the DMA remapping feature of the vIOM= MU. + + ``intremap=3Don|off`` (default: auto) + Generic x86 IOMMU functionality implemented by ``amd-iommu`` devic= e. + Enables interrupt remapping feature in guests, which is also requi= red to + enable x2apic support. + Currently only available with ``kernel-irqchip=3Doff|split``, it is + automatically enabled when either of those modes is in use, and di= sabled + with ``kernel-irqchip=3Don``. + + ``xtsup=3Don|off`` (default: off) + Interrupt remapping table supports x2apic mode, enabling the use of + 128-bit IRTE format with 32-bit destination field by the guest. Re= quired + to support routing interrupts to vCPUs with APIC IDs larger than 0= xff. + ERST =20 DEF("name", HAS_ARG, QEMU_OPTION_name, --=20 2.43.5 From nobody Sun Sep 28 16:28:07 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oracle.com ARC-Seal: i=1; a=rsa-sha256; t=1758317815; cv=none; d=zohomail.com; s=zohoarc; b=nDhkKXyz3WPcdM3P7/imBCZvukeIa/GVkWqWVRIpCA129qOaH9np2XQXWMyLsEaFAp3wQ+62W0xtVm2qVVOaDZDlrFsmtisB0No+Jt6cuPAoAuT0R70p2+kG3+BV1hlDxPSTDcyRiuEWUDxKPmvqw0F4MEjQyk5R/bFdKpalvSw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758317815; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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charset="utf-8" Move code related to Device Table and Page Table to an earlier location in the file, where it does not require forward declarations to be used by the various invalidation functions that will need to query the DTE and walk the page table in upcoming changes. This change consist of code movement only, no functional change intended. Signed-off-by: Alejandro Jimenez --- hw/i386/amd_iommu.c | 172 ++++++++++++++++++++++---------------------- 1 file changed, 86 insertions(+), 86 deletions(-) diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index 26be69bec8ae2..3cbc9499dbcc4 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -438,6 +438,92 @@ static void amdvi_completion_wait(AMDVIState *s, uint6= 4_t *cmd) trace_amdvi_completion_wait(addr, data); } =20 +static inline uint64_t amdvi_get_perms(uint64_t entry) +{ + return (entry & (AMDVI_DEV_PERM_READ | AMDVI_DEV_PERM_WRITE)) >> + AMDVI_DEV_PERM_SHIFT; +} + +/* validate that reserved bits are honoured */ +static bool amdvi_validate_dte(AMDVIState *s, uint16_t devid, + uint64_t *dte) +{ + if ((dte[0] & AMDVI_DTE_QUAD0_RESERVED) || + (dte[1] & AMDVI_DTE_QUAD1_RESERVED) || + (dte[2] & AMDVI_DTE_QUAD2_RESERVED) || + (dte[3] & AMDVI_DTE_QUAD3_RESERVED)) { + amdvi_log_illegaldevtab_error(s, devid, + s->devtab + + devid * AMDVI_DEVTAB_ENTRY_SIZE, 0); + return false; + } + + return true; +} + +/* get a device table entry given the devid */ +static bool amdvi_get_dte(AMDVIState *s, int devid, uint64_t *entry) +{ + uint32_t offset =3D devid * AMDVI_DEVTAB_ENTRY_SIZE; + + if (dma_memory_read(&address_space_memory, s->devtab + offset, entry, + AMDVI_DEVTAB_ENTRY_SIZE, MEMTXATTRS_UNSPECIFIED)) { + trace_amdvi_dte_get_fail(s->devtab, offset); + /* log error accessing dte */ + amdvi_log_devtab_error(s, devid, s->devtab + offset, 0); + return false; + } + + *entry =3D le64_to_cpu(*entry); + if (!amdvi_validate_dte(s, devid, entry)) { + trace_amdvi_invalid_dte(entry[0]); + return false; + } + + return true; +} + +/* get pte translation mode */ +static inline uint8_t get_pte_translation_mode(uint64_t pte) +{ + return (pte >> AMDVI_DEV_MODE_RSHIFT) & AMDVI_DEV_MODE_MASK; +} + +static inline uint64_t pte_override_page_mask(uint64_t pte) +{ + uint8_t page_mask =3D 13; + uint64_t addr =3D (pte & AMDVI_DEV_PT_ROOT_MASK) >> 12; + /* find the first zero bit */ + while (addr & 1) { + page_mask++; + addr =3D addr >> 1; + } + + return ~((1ULL << page_mask) - 1); +} + +static inline uint64_t pte_get_page_mask(uint64_t oldlevel) +{ + return ~((1UL << ((oldlevel * 9) + 3)) - 1); +} + +static inline uint64_t amdvi_get_pte_entry(AMDVIState *s, uint64_t pte_add= r, + uint16_t devid) +{ + uint64_t pte; + + if (dma_memory_read(&address_space_memory, pte_addr, + &pte, sizeof(pte), MEMTXATTRS_UNSPECIFIED)) { + trace_amdvi_get_pte_hwerror(pte_addr); + amdvi_log_pagetab_error(s, devid, pte_addr, 0); + pte =3D 0; + return pte; + } + + pte =3D le64_to_cpu(pte); + return pte; +} + /* log error without aborting since linux seems to be using reserved bits = */ static void amdvi_inval_devtab_entry(AMDVIState *s, uint64_t *cmd) { @@ -894,92 +980,6 @@ static void amdvi_mmio_write(void *opaque, hwaddr addr= , uint64_t val, } } =20 -static inline uint64_t amdvi_get_perms(uint64_t entry) -{ - return (entry & (AMDVI_DEV_PERM_READ | AMDVI_DEV_PERM_WRITE)) >> - AMDVI_DEV_PERM_SHIFT; -} - -/* validate that reserved bits are honoured */ -static bool amdvi_validate_dte(AMDVIState *s, uint16_t devid, - uint64_t *dte) -{ - if ((dte[0] & AMDVI_DTE_QUAD0_RESERVED) || - (dte[1] & AMDVI_DTE_QUAD1_RESERVED) || - (dte[2] & AMDVI_DTE_QUAD2_RESERVED) || - (dte[3] & AMDVI_DTE_QUAD3_RESERVED)) { - amdvi_log_illegaldevtab_error(s, devid, - s->devtab + - devid * AMDVI_DEVTAB_ENTRY_SIZE, 0); - return false; - } - - return true; -} - -/* get a device table entry given the devid */ -static bool amdvi_get_dte(AMDVIState *s, int devid, uint64_t *entry) -{ - uint32_t offset =3D devid * AMDVI_DEVTAB_ENTRY_SIZE; - - if (dma_memory_read(&address_space_memory, s->devtab + offset, entry, - AMDVI_DEVTAB_ENTRY_SIZE, MEMTXATTRS_UNSPECIFIED)) { - trace_amdvi_dte_get_fail(s->devtab, offset); - /* log error accessing dte */ - amdvi_log_devtab_error(s, devid, s->devtab + offset, 0); - return false; - } - - *entry =3D le64_to_cpu(*entry); - if (!amdvi_validate_dte(s, devid, entry)) { - trace_amdvi_invalid_dte(entry[0]); - return false; - } - - return true; -} - -/* get pte translation mode */ -static inline uint8_t get_pte_translation_mode(uint64_t pte) -{ - return (pte >> AMDVI_DEV_MODE_RSHIFT) & AMDVI_DEV_MODE_MASK; -} - -static inline uint64_t pte_override_page_mask(uint64_t pte) -{ - uint8_t page_mask =3D 13; - uint64_t addr =3D (pte & AMDVI_DEV_PT_ROOT_MASK) >> 12; - /* find the first zero bit */ - while (addr & 1) { - page_mask++; - addr =3D addr >> 1; - } - - return ~((1ULL << page_mask) - 1); -} - -static inline uint64_t pte_get_page_mask(uint64_t oldlevel) -{ - return ~((1UL << ((oldlevel * 9) + 3)) - 1); -} - -static inline uint64_t amdvi_get_pte_entry(AMDVIState *s, uint64_t pte_add= r, - uint16_t devid) -{ - uint64_t pte; - - if (dma_memory_read(&address_space_memory, pte_addr, - &pte, sizeof(pte), MEMTXATTRS_UNSPECIFIED)) { - trace_amdvi_get_pte_hwerror(pte_addr); - amdvi_log_pagetab_error(s, devid, pte_addr, 0); - pte =3D 0; - return pte; - } - - pte =3D le64_to_cpu(pte); - return pte; -} - static void amdvi_page_walk(AMDVIAddressSpace *as, uint64_t *dte, IOMMUTLBEntry *ret, unsigned perms, hwaddr addr) --=20 2.43.5 From nobody Sun Sep 28 16:28:07 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oracle.com ARC-Seal: i=1; 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Fri, 19 Sep 2025 21:35:28 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oracle.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=corp-2025-04-25; bh=lWTXc PDkzvOTy2E4xjFLqSMtjw16XmwocuiKRJX1u1o=; b=bGwritF65P/3BzRkRjTf1 /C4gZSWvH/Jm6SZFxhSdK/qY5P4P6KEbi2rt2cZyFb3RuKQ56Aa2CzClFc8IRfCp nGo5YK7xB/hzxeA69ZYHPm+HINQvknTqwj9g+iw6PcUvrm4/VPcjymaYvj65R/as ZCcueyKXndPofOE/TuwR6CnMqYlFNOtlJ6MuPBgVfZiTmnd0HWBpGl3fXot770le W5TqftIauGSMJ8RWKF/eAbLtfAnrwzq8dgbg4S+aqSHwDgy3jIZv+3cSCBU4Wqjo kxivuqy2MQVgs+D2K5jcTjpgre6mIOyx7jkcZ1D3ho+s7ibwmhRLjHVfp+eeacZn Q== From: Alejandro Jimenez To: qemu-devel@nongnu.org Cc: mst@redhat.com, clement.mathieu--drif@eviden.com, pbonzini@redhat.com, richard.henderson@linaro.org, eduardo@habkost.net, peterx@redhat.com, david@redhat.com, philmd@linaro.org, marcel.apfelbaum@gmail.com, alex.williamson@redhat.com, imammedo@redhat.com, anisinha@redhat.com, vasant.hegde@amd.com, suravee.suthikulpanit@amd.com, santosh.shukla@amd.com, sarunkod@amd.com, Wei.Huang2@amd.com, Ankit.Soni@amd.com, ethan.milon@eviden.com, joao.m.martins@oracle.com, boris.ostrovsky@oracle.com, alejandro.j.jimenez@oracle.com Subject: [PATCH v3 04/22] amd_iommu: Helper to decode size of page invalidation command Date: Fri, 19 Sep 2025 21:34:57 +0000 Message-ID: <20250919213515.917111-5-alejandro.j.jimenez@oracle.com> X-Mailer: git-send-email 2.43.5 In-Reply-To: <20250919213515.917111-1-alejandro.j.jimenez@oracle.com> References: <20250919213515.917111-1-alejandro.j.jimenez@oracle.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-19_03,2025-09-19_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 phishscore=0 bulkscore=0 adultscore=0 mlxlogscore=999 spamscore=0 mlxscore=0 suspectscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2508110000 definitions=main-2509190201 X-Authority-Analysis: v=2.4 cv=b9Oy4sGx c=1 sm=1 tr=0 ts=68cdcca1 b=1 cx=c_pps a=WeWmnZmh0fydH62SvGsd2A==:117 a=WeWmnZmh0fydH62SvGsd2A==:17 a=yJojWOMRYYMA:10 a=yPCof4ZbAAAA:8 a=ZVecacK4M2hnvEF20eUA:9 X-Proofpoint-GUID: btv3tGqiRoglQaD-k5j1S01KJeATnkFN X-Proofpoint-ORIG-GUID: btv3tGqiRoglQaD-k5j1S01KJeATnkFN X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTE2MDIwMyBTYWx0ZWRfX0xUqhg+zWcj0 ETzPAGQpvRt5LfaEgpwhMjIiNqDTiZU/TsV8u3hcxFguqqa8q/QXYpSTRs4ABBvYOAe5dhN7nxe IKRji58fOIjQb3X4DV1rnryPYgiXopLn2qI1weO0nQ7Ab89aJjI9uTcfTkGjocOws7v58U63OSr K4fE0iaNQXKqi6r1oUBbqrGHovNe4oWfSSBYLzCGp1tbRp5bAFFc0Aqy1WtLMeAcUZ81IB2Efcn PoaKZQhQcFSUJdngcLjO938MvmmoQe1WNnP5N2lMC1ZUrPelWWiRTNgL75KMiG5EtVlXPJgGBUC 4xrM5xhi+VCOkm9t5mvlfahxzWLFKrjyPKE+u21gCryXEQY9JeJo9Mhb1NFFht9N/ib9RzEzzAV i17j3Rl2 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.165.32; envelope-from=alejandro.j.jimenez@oracle.com; helo=mx0a-00069f02.pphosted.com X-Spam_score_int: -23 X-Spam_score: -2.4 X-Spam_bar: -- X-Spam_report: (-2.4 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @oracle.com) X-ZM-MESSAGEID: 1758317993765116600 Content-Type: text/plain; charset="utf-8" The size of the region to invalidate depends on the S bit and address encoded in the command. Add a helper to extract this information, which will be used to sync shadow page tables in upcoming changes. Signed-off-by: Alejandro Jimenez --- hw/i386/amd_iommu.c | 34 ++++++++++++++++++++++++++++++++++ hw/i386/amd_iommu.h | 4 ++++ 2 files changed, 38 insertions(+) diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index 3cbc9499dbcc4..202f0f8c6e90c 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -577,6 +577,40 @@ static gboolean amdvi_iotlb_remove_by_domid(gpointer k= ey, gpointer value, return entry->domid =3D=3D domid; } =20 +/* + * Helper to decode the size of the range to invalidate encoded in the + * INVALIDATE_IOMMU_PAGES Command format. + * The size of the region to invalidate depends on the S bit and address. + * S bit value: + * 0 : Invalidation size is 4 Kbytes. + * 1 : Invalidation size is determined by first zero bit in the address + * starting from Address[12]. + * + * In the AMD IOMMU Linux driver, an invalidation command with address + * ((1 << 63) - 1) is sent when intending to clear the entire cache. + * However, Table 14: Example Page Size Encodings shows that an address of + * ((1ULL << 51) - 1) encodes the entire cache, so effectively any address= with + * first zero at bit 51 or larger is a request to invalidate the entire ad= dress + * space. + */ +static uint64_t __attribute__((unused)) +amdvi_decode_invalidation_size(hwaddr addr, uint16_t flags) +{ + uint64_t size =3D AMDVI_PAGE_SIZE; + uint8_t fzbit =3D 0; + + if (flags & AMDVI_CMD_INVAL_IOMMU_PAGES_S) { + fzbit =3D cto64(addr | 0xFFF); + + if (fzbit >=3D 51) { + size =3D AMDVI_INV_ALL_PAGES; + } else { + size =3D 1ULL << (fzbit + 1); + } + } + return size; +} + /* we don't have devid - we can't remove pages by address */ static void amdvi_inval_pages(AMDVIState *s, uint64_t *cmd) { diff --git a/hw/i386/amd_iommu.h b/hw/i386/amd_iommu.h index 2476296c49023..c1170a820257e 100644 --- a/hw/i386/amd_iommu.h +++ b/hw/i386/amd_iommu.h @@ -126,6 +126,10 @@ #define AMDVI_CMD_COMPLETE_PPR_REQUEST 0x07 #define AMDVI_CMD_INVAL_AMDVI_ALL 0x08 =20 + +#define AMDVI_CMD_INVAL_IOMMU_PAGES_S (1ULL << 0) +#define AMDVI_INV_ALL_PAGES (1ULL << 52) + #define AMDVI_DEVTAB_ENTRY_SIZE 32 =20 /* Device table entry bits 0:63 */ --=20 2.43.5 From nobody Sun Sep 28 16:28:07 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" Extracting the DTE from a given AMDVIAddressSpace pointer structure is a common operation required for syncing the shadow page tables. Implement a helper to do it and check for common error conditions. Signed-off-by: Alejandro Jimenez --- hw/i386/amd_iommu.c | 48 +++++++++++++++++++++++++++++++++++++++------ 1 file changed, 42 insertions(+), 6 deletions(-) diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index 202f0f8c6e90c..dc7531fd4a8b9 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -77,6 +77,18 @@ typedef struct AMDVIIOTLBEntry { uint64_t page_mask; /* physical page size */ } AMDVIIOTLBEntry; =20 +/* + * These 'fault' reasons have an overloaded meaning since they are not only + * intended for describing reasons that generate an IO_PAGE_FAULT as per t= he AMD + * IOMMU specification, but are also used to signal internal errors in the + * emulation code. + */ +typedef enum AMDVIFaultReason { + AMDVI_FR_DTE_RTR_ERR =3D 1, /* Failure to retrieve DTE */ + AMDVI_FR_DTE_V, /* DTE[V] =3D 0 */ + AMDVI_FR_DTE_TV, /* DTE[TV] =3D 0 */ +} AMDVIFaultReason; + uint64_t amdvi_extended_feature_register(AMDVIState *s) { uint64_t feature =3D AMDVI_DEFAULT_EXT_FEATURES; @@ -524,6 +536,28 @@ static inline uint64_t amdvi_get_pte_entry(AMDVIState = *s, uint64_t pte_addr, return pte; } =20 +static int amdvi_as_to_dte(AMDVIAddressSpace *as, uint64_t *dte) +{ + uint16_t devid =3D PCI_BUILD_BDF(as->bus_num, as->devfn); + AMDVIState *s =3D as->iommu_state; + + if (!amdvi_get_dte(s, devid, dte)) { + /* Unable to retrieve DTE for devid */ + return -AMDVI_FR_DTE_RTR_ERR; + } + + if (!(dte[0] & AMDVI_DEV_VALID)) { + /* DTE[V] not set, address is passed untranslated for devid */ + return -AMDVI_FR_DTE_V; + } + + if (!(dte[0] & AMDVI_DEV_TRANSLATION_VALID)) { + /* DTE[TV] not set, host page table not valid for devid */ + return -AMDVI_FR_DTE_TV; + } + return 0; +} + /* log error without aborting since linux seems to be using reserved bits = */ static void amdvi_inval_devtab_entry(AMDVIState *s, uint64_t *cmd) { @@ -1081,6 +1115,7 @@ static void amdvi_do_translate(AMDVIAddressSpace *as,= hwaddr addr, uint16_t devid =3D PCI_BUILD_BDF(as->bus_num, as->devfn); AMDVIIOTLBEntry *iotlb_entry =3D amdvi_iotlb_lookup(s, addr, devid); uint64_t entry[4]; + int dte_ret; =20 if (iotlb_entry) { trace_amdvi_iotlb_hit(PCI_BUS_NUM(devid), PCI_SLOT(devid), @@ -1092,13 +1127,14 @@ static void amdvi_do_translate(AMDVIAddressSpace *a= s, hwaddr addr, return; } =20 - if (!amdvi_get_dte(s, devid, entry)) { - return; - } + dte_ret =3D amdvi_as_to_dte(as, entry); =20 - /* devices with V =3D 0 are not translated */ - if (!(entry[0] & AMDVI_DEV_VALID)) { - goto out; + if (dte_ret < 0) { + if (dte_ret =3D=3D -AMDVI_FR_DTE_V) { + /* DTE[V]=3D0, address is passed untranslated */ + goto out; + } + return; } =20 amdvi_page_walk(as, entry, ret, --=20 2.43.5 From nobody Sun Sep 28 16:28:07 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oracle.com ARC-Seal: i=1; a=rsa-sha256; t=1758317997; cv=none; d=zohomail.com; s=zohoarc; b=E8aYpyYmJKQMpS7PT545yyqE1thViTSeB41fzSAUxTKk7HEFGWuKjtlc4I92GwLcm8OmSl2JA1lHk2VsBve07M4u/rrmw+hRPJwDv1iqIqtK+4KSfvL8byBANdI13qpOMB9+cqEHfrQsvws1qTAWGcWYrWDg/MlV9swinmy2MQE= ARC-Message-Signature: i=1; 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b=D7vX675QFUcV2ECmi+jX9 naR7kAdh1u2DGX6M9ZTPTOVD6+dpJ/WsdvY1qu+Ysm3Pl8z7zThTZfT03hrCXnHU nOlmr3cWUxt61ttc+L7PVDouOw6/sJhUcBv5rAq9oNEWN8wfF1aVIDC9bXHqtot0 Kukz8Asa39MT62UA2oXdOHMV5KZV09ks3Fv2q9HyakeJ2RhzjPOSPW8K6oOOS1/N Tj92zuxXv+KOiGiVpHXVvxM0ft3NPedV9TxlkbBe8hzU5ycEXl9gr3SmVjUQAxjC JXygnHAA1idKxyEXPPqxyHgOhJcnP+9+B6QVUONBO5a1YVdjZmLqQ3YDPRxTTH7J g== From: Alejandro Jimenez To: qemu-devel@nongnu.org Cc: mst@redhat.com, clement.mathieu--drif@eviden.com, pbonzini@redhat.com, richard.henderson@linaro.org, eduardo@habkost.net, peterx@redhat.com, david@redhat.com, philmd@linaro.org, marcel.apfelbaum@gmail.com, alex.williamson@redhat.com, imammedo@redhat.com, anisinha@redhat.com, vasant.hegde@amd.com, suravee.suthikulpanit@amd.com, santosh.shukla@amd.com, sarunkod@amd.com, Wei.Huang2@amd.com, Ankit.Soni@amd.com, ethan.milon@eviden.com, joao.m.martins@oracle.com, boris.ostrovsky@oracle.com, alejandro.j.jimenez@oracle.com Subject: [PATCH v3 06/22] amd_iommu: Return an error when unable to read PTE from guest memory Date: Fri, 19 Sep 2025 21:34:59 +0000 Message-ID: <20250919213515.917111-7-alejandro.j.jimenez@oracle.com> X-Mailer: git-send-email 2.43.5 In-Reply-To: <20250919213515.917111-1-alejandro.j.jimenez@oracle.com> References: <20250919213515.917111-1-alejandro.j.jimenez@oracle.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-19_03,2025-09-19_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 phishscore=0 bulkscore=0 adultscore=0 mlxlogscore=999 spamscore=0 mlxscore=0 suspectscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2508110000 definitions=main-2509190201 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTE2MDIwMiBTYWx0ZWRfX0uOTTIR7DdZ/ ih9ay55qMiMZT/btvh9dA8B32/WCCcJZHtHCY2QcT2Ln4WokJ/zKFAO1jieFX69BrGEg7qRJ085 WToF8kT7WqiemKSpX8f76PTvuuOZFU92/Dtr79ffHBIvaarNe/fEGfOhFvqRkZGeKnnaDOA3ll7 b3kM7TBGfH6db802kTfqdO4+7fK3UdG1RK5+b9GwFNuXYb4FInJx+o4sppPFnVV96+IVUB5YXr6 Ztjh+mhgVe0RnUQwAAjv8aXyB0lLS5Y2QjJY27C6OcviPyMWD5pGG03v4Kslu5UCD9/WRBjFhG/ u1gjs3SpYhD6agifJnnPBOrsXOfN23MzAaxchz99Sd0qbFwZBErWA+KZB83gdpXbKMYpZBLbu5c wD9ruir3 X-Authority-Analysis: v=2.4 cv=X5RSKHTe c=1 sm=1 tr=0 ts=68cdcca6 b=1 cx=c_pps a=WeWmnZmh0fydH62SvGsd2A==:117 a=WeWmnZmh0fydH62SvGsd2A==:17 a=yJojWOMRYYMA:10 a=yPCof4ZbAAAA:8 a=R37TJkT3toX5d3LG1KMA:9 a=FjD-8dGO14Yd8gSk4-3N:22 X-Proofpoint-GUID: ka7UQ2L7KNsql_Z6A6UwMCKSIxKpf8h- X-Proofpoint-ORIG-GUID: ka7UQ2L7KNsql_Z6A6UwMCKSIxKpf8h- Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Make amdvi_get_pte_entry() return an error value (-1) in cases where the memory read fails, versus the current return of 0 to indicate failure. The reason is that 0 is also a valid value to have stored in the PTE in guest memory i.e. the guest does not have a mapping. Before this change, amdvi_get_pte_entry() returned 0 for both an error and for empty PTEs, but the page walker implementation that will be introduced in upcoming changes needs a method to differentiate between the two scenarios. Signed-off-by: Alejandro Jimenez --- hw/i386/amd_iommu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index dc7531fd4a8b9..29ed3f0ef292e 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -528,7 +528,7 @@ static inline uint64_t amdvi_get_pte_entry(AMDVIState *= s, uint64_t pte_addr, &pte, sizeof(pte), MEMTXATTRS_UNSPECIFIED)) { trace_amdvi_get_pte_hwerror(pte_addr); amdvi_log_pagetab_error(s, devid, pte_addr, 0); - pte =3D 0; + pte =3D (uint64_t)-1; return pte; } =20 @@ -1081,7 +1081,7 @@ static void amdvi_page_walk(AMDVIAddressSpace *as, ui= nt64_t *dte, /* add offset and load pte */ pte_addr +=3D ((addr >> (3 + 9 * level)) & 0x1FF) << 3; pte =3D amdvi_get_pte_entry(as->iommu_state, pte_addr, as->dev= fn); - if (!pte) { + if (!pte || (pte =3D=3D (uint64_t)-1)) { return; } oldlevel =3D level; --=20 2.43.5 From nobody Sun Sep 28 16:28:07 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" The current amdvi_page_walk() is designed to be called by the replay() method. Rather than drastically altering it, introduce helpers to fetch guest PTEs that will be used by a page walker implementation. Signed-off-by: Alejandro Jimenez --- hw/i386/amd_iommu.c | 123 ++++++++++++++++++++++++++++++++++++++++++++ hw/i386/amd_iommu.h | 40 ++++++++++++++ 2 files changed, 163 insertions(+) diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index 29ed3f0ef292e..c25981ff93c02 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -87,6 +87,8 @@ typedef enum AMDVIFaultReason { AMDVI_FR_DTE_RTR_ERR =3D 1, /* Failure to retrieve DTE */ AMDVI_FR_DTE_V, /* DTE[V] =3D 0 */ AMDVI_FR_DTE_TV, /* DTE[TV] =3D 0 */ + AMDVI_FR_PT_ROOT_INV, /* Page Table Root ptr invalid */ + AMDVI_FR_PT_ENTRY_INV, /* Failure to read PTE from guest memory */ } AMDVIFaultReason; =20 uint64_t amdvi_extended_feature_register(AMDVIState *s) @@ -558,6 +560,127 @@ static int amdvi_as_to_dte(AMDVIAddressSpace *as, uin= t64_t *dte) return 0; } =20 +/* + * For a PTE encoding a large page, return the page size it encodes as des= cribed + * by the AMD IOMMU Specification Table 14: Example Page Size Encodings. + * No need to adjust the value of the PTE to point to the first PTE in the= large + * page since the encoding guarantees all "base" PTEs in the large page ar= e the + * same. + */ +static uint64_t large_pte_page_size(uint64_t pte) +{ + assert(PTE_NEXT_LEVEL(pte) =3D=3D 7); + + /* Determine size of the large/contiguous page encoded in the PTE */ + return PTE_LARGE_PAGE_SIZE(pte); +} + +/* + * Helper function to fetch a PTE using AMD v1 pgtable format. + * On successful page walk, returns 0 and pte parameter points to a valid = PTE. + * On failure, returns: + * -AMDVI_FR_PT_ROOT_INV: A page walk is not possible due to conditions li= ke DTE + * with invalid permissions, Page Table Root can not be read from DTE= , or a + * larger IOVA than supported by page table level encoded in DTE[Mode= ]. + * -AMDVI_FR_PT_ENTRY_INV: A PTE could not be read from guest memory durin= g a + * page table walk. This means that the DTE has valid data, but one o= f the + * lower level entries in the Page Table could not be read. + */ +static int __attribute__((unused)) +fetch_pte(AMDVIAddressSpace *as, hwaddr address, uint64_t dte, uint64_t *p= te, + hwaddr *page_size) +{ + IOMMUAccessFlags perms =3D amdvi_get_perms(dte); + + uint8_t level, mode; + uint64_t pte_addr; + + *pte =3D dte; + *page_size =3D 0; + + if (perms =3D=3D IOMMU_NONE) { + return -AMDVI_FR_PT_ROOT_INV; + } + + /* + * The Linux kernel driver initializes the default mode to 3, correspo= nding + * to a 39-bit GPA space, where each entry in the pagetable translates= to a + * 1GB (2^30) page size. + */ + level =3D mode =3D get_pte_translation_mode(dte); + assert(mode > 0 && mode < 7); + + /* + * If IOVA is larger than the max supported by the current pgtable lev= el, + * there is nothing to do. + */ + if (address > PT_LEVEL_MAX_ADDR(mode - 1)) { + /* IOVA too large for the current DTE */ + return -AMDVI_FR_PT_ROOT_INV; + } + + do { + level -=3D 1; + + /* Update the page_size */ + *page_size =3D PTE_LEVEL_PAGE_SIZE(level); + + /* Permission bits are ANDed at every level, including the DTE */ + perms &=3D amdvi_get_perms(*pte); + if (perms =3D=3D IOMMU_NONE) { + return 0; + } + + /* Not Present */ + if (!IOMMU_PTE_PRESENT(*pte)) { + return 0; + } + + /* Large or Leaf PTE found */ + if (PTE_NEXT_LEVEL(*pte) =3D=3D 7 || PTE_NEXT_LEVEL(*pte) =3D=3D 0= ) { + /* Leaf PTE found */ + break; + } + + /* + * Index the pgtable using the IOVA bits corresponding to current = level + * and walk down to the lower level. + */ + pte_addr =3D NEXT_PTE_ADDR(*pte, level, address); + *pte =3D amdvi_get_pte_entry(as->iommu_state, pte_addr, as->devfn); + + if (*pte =3D=3D (uint64_t)-1) { + /* + * A returned PTE of -1 indicates a failure to read the page t= able + * entry from guest memory. + */ + if (level =3D=3D mode - 1) { + /* Failure to retrieve the Page Table from Root Pointer */ + *page_size =3D 0; + return -AMDVI_FR_PT_ROOT_INV; + } else { + /* Failure to read PTE. Page walk skips a page_size chunk = */ + return -AMDVI_FR_PT_ENTRY_INV; + } + } + } while (level > 0); + + assert(PTE_NEXT_LEVEL(*pte) =3D=3D 0 || PTE_NEXT_LEVEL(*pte) =3D=3D 7 = || + level =3D=3D 0); + /* + * Page walk ends when Next Level field on PTE shows that either a lea= f PTE + * or a series of large PTEs have been reached. In the latter case, ev= en if + * the range starts in the middle of a contiguous page, the returned P= TE + * must be the first PTE of the series. + */ + if (PTE_NEXT_LEVEL(*pte) =3D=3D 7) { + /* Update page_size with the large PTE page size */ + *page_size =3D large_pte_page_size(*pte); + } + + return 0; +} + /* log error without aborting since linux seems to be using reserved bits = */ static void amdvi_inval_devtab_entry(AMDVIState *s, uint64_t *cmd) { diff --git a/hw/i386/amd_iommu.h b/hw/i386/amd_iommu.h index c1170a820257e..9f833b297d25c 100644 --- a/hw/i386/amd_iommu.h +++ b/hw/i386/amd_iommu.h @@ -178,6 +178,46 @@ #define AMDVI_GATS_MODE (2ULL << 12) #define AMDVI_HATS_MODE (2ULL << 10) =20 +/* Page Table format */ + +#define AMDVI_PTE_PR (1ULL << 0) +#define AMDVI_PTE_NEXT_LEVEL_MASK GENMASK64(11, 9) + +#define IOMMU_PTE_PRESENT(pte) ((pte) & AMDVI_PTE_PR) + +/* Using level=3D0 for leaf PTE at 4K page size */ +#define PT_LEVEL_SHIFT(level) (12 + ((level) * 9)) + +/* Return IOVA bit group used to index the Page Table at specific level */ +#define PT_LEVEL_INDEX(level, iova) (((iova) >> PT_LEVEL_SHIFT(level))= & \ + GENMASK64(8, 0)) + +/* Return the max address for a specified level i.e. max_oaddr */ +#define PT_LEVEL_MAX_ADDR(x) (((x) < 5) ? \ + ((1ULL << PT_LEVEL_SHIFT((x + 1))) - 1) : \ + (~(0ULL))) + +/* Extract the NextLevel field from PTE/PDE */ +#define PTE_NEXT_LEVEL(pte) (((pte) & AMDVI_PTE_NEXT_LEVEL_MASK) >> 9) + +/* Take page table level and return default pagetable size for level */ +#define PTE_LEVEL_PAGE_SIZE(level) (1ULL << (PT_LEVEL_SHIFT(level))) + +/* + * Return address of lower level page table encoded in PTE and specified by + * current level and corresponding IOVA bit group at such level. + */ +#define NEXT_PTE_ADDR(pte, level, iova) (((pte) & AMDVI_DEV_PT_ROOT_MASK) = + \ + (PT_LEVEL_INDEX(level, iova) * 8)) + +/* + * Take a PTE value with mode=3D0x07 and return the page size it encodes. + */ +#define PTE_LARGE_PAGE_SIZE(pte) (1ULL << (1 + cto64(((pte) | 0xfffULL)= ))) + +/* Return number of PTEs to use for a given page size (expected power of 2= ) */ +#define PAGE_SIZE_PTE_COUNT(pgsz) (1ULL << ((ctz64(pgsz) - 12) % 9)) + /* IOTLB */ #define AMDVI_IOTLB_MAX_SIZE 1024 #define AMDVI_DEVID_SHIFT 36 --=20 2.43.5 From nobody Sun Sep 28 16:28:07 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" For the specified address range, walk the page table identifying regions as mapped or unmapped and invoke registered notifiers with the corresponding event type. Signed-off-by: Alejandro Jimenez --- hw/i386/amd_iommu.c | 80 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index c25981ff93c02..0e45435c77be9 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -681,6 +681,86 @@ fetch_pte(AMDVIAddressSpace *as, hwaddr address, uint6= 4_t dte, uint64_t *pte, return 0; } =20 +/* + * Walk the guest page table for an IOVA and range and signal the register= ed + * notifiers to sync the shadow page tables in the host. + * Must be called with a valid DTE for DMA remapping i.e. V=3D1,TV=3D1 + */ +static void __attribute__((unused)) +amdvi_sync_shadow_page_table_range(AMDVIAddressSpace *as, uint64_t *dte, + hwaddr addr, uint64_t size, bool send_u= nmap) +{ + IOMMUTLBEvent event; + + hwaddr iova_next, page_mask, pagesize; + hwaddr iova =3D addr; + hwaddr end =3D iova + size - 1; + + uint64_t pte; + int ret; + + while (iova < end) { + + ret =3D fetch_pte(as, iova, dte[0], &pte, &pagesize); + + if (ret =3D=3D -AMDVI_FR_PT_ROOT_INV) { + /* + * Invalid conditions such as the IOVA being larger than suppo= rted + * by current page table mode as configured in the DTE, or a f= ailure + * to fetch the Page Table from the Page Table Root Pointer in= DTE. + */ + assert(pagesize =3D=3D 0); + return; + } + /* PTE has been validated for major errors and pagesize is set */ + assert(pagesize); + page_mask =3D ~(pagesize - 1); + iova_next =3D (iova & page_mask) + pagesize; + + if (ret =3D=3D -AMDVI_FR_PT_ENTRY_INV) { + /* + * Failure to read PTE from memory, the pagesize matches the c= urrent + * level. Unable to determine the region type, so a safe strat= egy is + * to skip the range and continue the page walk. + */ + goto next; + } + + event.entry.target_as =3D &address_space_memory; + event.entry.iova =3D iova & page_mask; + /* translated_addr is irrelevant for the unmap case */ + event.entry.translated_addr =3D (pte & AMDVI_DEV_PT_ROOT_MASK) & + page_mask; + event.entry.addr_mask =3D ~page_mask; + event.entry.perm =3D amdvi_get_perms(pte); + + /* + * In cases where the leaf PTE is not found, or it has invalid + * permissions, an UNMAP type notification is sent, but only if the + * caller requested it. + */ + if (!IOMMU_PTE_PRESENT(pte) || (event.entry.perm =3D=3D IOMMU_NONE= )) { + if (!send_unmap) { + goto next; + } + event.type =3D IOMMU_NOTIFIER_UNMAP; + } else { + event.type =3D IOMMU_NOTIFIER_MAP; + } + + /* Invoke the notifiers registered for this address space */ + memory_region_notify_iommu(&as->iommu, 0, event); + +next: + /* Check for 64-bit overflow and terminate walk in such cases */ + if (iova_next < iova) { + break; + } else { + iova =3D iova_next; + } + } +} + /* log error without aborting since linux seems to be using reserved bits = */ static void amdvi_inval_devtab_entry(AMDVIState *s, uint64_t *cmd) { --=20 2.43.5 From nobody Sun Sep 28 16:28:07 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oracle.com ARC-Seal: i=1; a=rsa-sha256; t=1758318005; cv=none; d=zohomail.com; s=zohoarc; b=dhKu+jn01ZQaGbmSAg2+CLNGGVFCJYVv7oAs1x6QvW9FAEOrMJDUI7PR7ynY5hjEdPDoSww4o5PEnvxn4NyNTBdD/GwUbQPNa3lO3NppBBuyYq4YdfUmCw5Gxn43rU1oqxlztGWcdZLuWyrmEdCCp2uF2KnIjUggkmYdh/HDBKc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758318005; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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charset="utf-8" Add the minimal data structures required to maintain a list of address spaces (i.e. devices) with registered notifiers, and to update the type of events that require notifications. Note that the ability to register for MAP notifications is not available. It will be unblocked by following changes that enable the synchronization of guest I/O page tables with host IOMMU state, at which point an amd-iommu device property will be introduced to control this capability. Signed-off-by: Alejandro Jimenez --- hw/i386/amd_iommu.c | 20 ++++++++++++++++++++ hw/i386/amd_iommu.h | 3 +++ 2 files changed, 23 insertions(+) diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index 0e45435c77be9..d8a451b3a5ff1 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -66,6 +66,11 @@ struct AMDVIAddressSpace { MemoryRegion iommu_nodma; /* Alias of shared nodma memory region */ MemoryRegion iommu_ir; /* Device's interrupt remapping region */ AddressSpace as; /* device's corresponding address space */ + + /* DMA address translation support */ + IOMMUNotifierFlag notifier_flags; + /* entry in list of Address spaces with registered notifiers */ + QLIST_ENTRY(AMDVIAddressSpace) next; }; =20 /* AMDVI cache entry */ @@ -1773,6 +1778,7 @@ static AddressSpace *amdvi_host_dma_iommu(PCIBus *bus= , void *opaque, int devfn) iommu_as[devfn]->bus_num =3D (uint8_t)bus_num; iommu_as[devfn]->devfn =3D (uint8_t)devfn; iommu_as[devfn]->iommu_state =3D s; + iommu_as[devfn]->notifier_flags =3D IOMMU_NOTIFIER_NONE; =20 amdvi_dev_as =3D iommu_as[devfn]; =20 @@ -1846,6 +1852,7 @@ static int amdvi_iommu_notify_flag_changed(IOMMUMemor= yRegion *iommu, Error **errp) { AMDVIAddressSpace *as =3D container_of(iommu, AMDVIAddressSpace, iommu= ); + AMDVIState *s =3D as->iommu_state; =20 if (new & IOMMU_NOTIFIER_MAP) { error_setg(errp, @@ -1854,6 +1861,19 @@ static int amdvi_iommu_notify_flag_changed(IOMMUMemo= ryRegion *iommu, PCI_FUNC(as->devfn)); return -EINVAL; } + + /* + * Update notifier flags for address space and the list of address spa= ces + * with registered notifiers. + */ + as->notifier_flags =3D new; + + if (old =3D=3D IOMMU_NOTIFIER_NONE) { + QLIST_INSERT_HEAD(&s->amdvi_as_with_notifiers, as, next); + } else if (new =3D=3D IOMMU_NOTIFIER_NONE) { + QLIST_REMOVE(as, next); + } + return 0; } =20 diff --git a/hw/i386/amd_iommu.h b/hw/i386/amd_iommu.h index 9f833b297d25c..b51aa74368995 100644 --- a/hw/i386/amd_iommu.h +++ b/hw/i386/amd_iommu.h @@ -409,6 +409,9 @@ struct AMDVIState { /* for each served device */ AMDVIAddressSpace **address_spaces[PCI_BUS_MAX]; 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charset="utf-8" When the guest issues an INVALIDATE_IOMMU_PAGES command, decode the address and size of the invalidation and sync the guest page table state with the host. This requires walking the guest page table and calling notifiers registered for address spaces matching the domain ID encoded in the command. Signed-off-by: Alejandro Jimenez --- hw/i386/amd_iommu.c | 82 ++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 74 insertions(+), 8 deletions(-) diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index d8a451b3a5ff1..caae65c4b3565 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -591,9 +591,8 @@ static uint64_t large_pte_page_size(uint64_t pte) * page table walk. This means that the DTE has valid data, but one o= f the * lower level entries in the Page Table could not be read. */ -static int __attribute__((unused)) -fetch_pte(AMDVIAddressSpace *as, hwaddr address, uint64_t dte, uint64_t *p= te, - hwaddr *page_size) +static uint64_t fetch_pte(AMDVIAddressSpace *as, hwaddr address, uint64_t = dte, + uint64_t *pte, hwaddr *page_size) { IOMMUAccessFlags perms =3D amdvi_get_perms(dte); =20 @@ -691,9 +690,9 @@ fetch_pte(AMDVIAddressSpace *as, hwaddr address, uint64= _t dte, uint64_t *pte, * notifiers to sync the shadow page tables in the host. * Must be called with a valid DTE for DMA remapping i.e. V=3D1,TV=3D1 */ -static void __attribute__((unused)) -amdvi_sync_shadow_page_table_range(AMDVIAddressSpace *as, uint64_t *dte, - hwaddr addr, uint64_t size, bool send_u= nmap) +static void amdvi_sync_shadow_page_table_range(AMDVIAddressSpace *as, + uint64_t *dte, hwaddr addr, + uint64_t size, bool send_un= map) { IOMMUTLBEvent event; =20 @@ -835,8 +834,7 @@ static gboolean amdvi_iotlb_remove_by_domid(gpointer ke= y, gpointer value, * first zero at bit 51 or larger is a request to invalidate the entire ad= dress * space. */ -static uint64_t __attribute__((unused)) -amdvi_decode_invalidation_size(hwaddr addr, uint16_t flags) +static uint64_t amdvi_decode_invalidation_size(hwaddr addr, uint16_t flags) { uint64_t size =3D AMDVI_PAGE_SIZE; uint8_t fzbit =3D 0; @@ -853,10 +851,76 @@ amdvi_decode_invalidation_size(hwaddr addr, uint16_t = flags) return size; } =20 +/* + * Synchronize the guest page tables with the shadow page tables kept in t= he + * host for the specified range. + * The invalidation command issued by the guest and intercepted by the VMM + * does not specify a device, but a domain, since all devices in the same = domain + * share the same page tables. However, vIOMMU emulation creates separate + * address spaces per device, so it is necessary to traverse the list of a= ll of + * address spaces (i.e. devices) that have notifiers registered in order to + * propagate the changes to the host page tables. + * We cannot return early from this function once a matching domain has be= en + * identified and its page tables synced (based on the fact that all devic= es in + * the same domain share the page tables). The reason is that different de= vices + * (i.e. address spaces) could have different notifiers registered, and by + * skipping address spaces that appear later on the amdvi_as_with_notifier= s list + * their notifiers (which could differ from the ones registered for the fi= rst + * device/address space) would not be invoked. + */ +static void amdvi_sync_domain(AMDVIState *s, uint16_t domid, uint64_t addr, + uint16_t flags) +{ + AMDVIAddressSpace *as; + + uint64_t size =3D amdvi_decode_invalidation_size(addr, flags); + + if (size =3D=3D AMDVI_INV_ALL_PAGES) { + addr =3D 0; /* Set start address to 0 and invalidate entire = AS */ + } else { + addr &=3D ~(size - 1); + } + + /* + * Call notifiers that have registered for each address space matching= the + * domain ID, in order to sync the guest pagetable state with the host. + */ + QLIST_FOREACH(as, &s->amdvi_as_with_notifiers, next) { + + uint64_t dte[4] =3D { 0 }; + + /* + * Retrieve the Device Table entry for the devid corresponding to = the + * current address space, and verify the DomainID matches i.e. the= page + * tables to be synced belong to devices in the domain. + */ + if (amdvi_as_to_dte(as, dte)) { + continue; + } + + /* Only need to sync the Page Tables for a matching domain */ + if (domid !=3D (dte[1] & AMDVI_DEV_DOMID_ID_MASK)) { + continue; + } + + /* + * We have determined that there is a valid Device Table Entry for= a + * device matching the DomainID in the INV_IOMMU_PAGES command iss= ued by + * the guest. Walk the guest page table to sync shadow page table. + */ + if (as->notifier_flags & IOMMU_NOTIFIER_MAP) { + /* Sync guest IOMMU mappings with host */ + amdvi_sync_shadow_page_table_range(as, &dte[0], addr, size, tr= ue); + } + } +} + /* we don't have devid - we can't remove pages by address */ static void amdvi_inval_pages(AMDVIState *s, uint64_t *cmd) { uint16_t domid =3D cpu_to_le16((uint16_t)extract64(cmd[0], 32, 16)); + uint64_t addr =3D cpu_to_le64(extract64(cmd[1], 12, 52)) << 12; + uint16_t flags =3D cpu_to_le16((uint16_t)extract64(cmd[1], 0, 3)); =20 if (extract64(cmd[0], 20, 12) || extract64(cmd[0], 48, 12) || extract64(cmd[1], 3, 9)) { @@ -866,6 +930,8 @@ static void amdvi_inval_pages(AMDVIState *s, uint64_t *= cmd) =20 g_hash_table_foreach_remove(s->iotlb, amdvi_iotlb_remove_by_domid, &domid); + + amdvi_sync_domain(s, domid, addr, flags); trace_amdvi_pages_inval(domid); } =20 --=20 2.43.5 From nobody Sun Sep 28 16:28:07 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Fri, 19 Sep 2025 21:35:45 GMT Received: from alaljimee5bm-ol9-20250405.osdevelopmeniad.oraclevcn.com (alaljimee5bm-ol9-20250405.allregionaliads.osdevelopmeniad.oraclevcn.com [100.100.254.235]) by phxpaimrmta03.imrmtpd1.prodappphxaev1.oraclevcn.com (PPS) with ESMTP id 494y2gwra3-12; Fri, 19 Sep 2025 21:35:45 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oracle.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=corp-2025-04-25; bh=E0Bs0 /46oRg89iiuFWOJK9F3iaA6Z78rrdoKygG43eg=; b=iu8YbFTMVRNqsU+Rsj2w/ XrFtvGnHuAvvfAUB0z0R9987OCqO5P7hDfcznlT5LpzYO7bHR85L3zeJumoJfdv8 fZt9vSnmD61S9mnUdu5+dKRtpSzqmVIaN2cAs4nuPaScgMB+4CuqfgU1jlvXC5sN 9fjtK2ZtsVload1viSr1UoNgbEdLTjuKYo/q59syg1eTRTnaCqlvKfrEJz8o2K12 lEaFmblwDpdb8QG3hwL4Nbcsg05kanI94aRJSOhLprng/t2UtaaBu2BjAPLHP3+4 +ikL5DB5XtkfG7TWDPfyRaLTLd51LMAKTvpBQ45AWlqnl9fvLTOoMckCTEbEVzVa w== From: Alejandro Jimenez To: qemu-devel@nongnu.org Cc: mst@redhat.com, clement.mathieu--drif@eviden.com, pbonzini@redhat.com, richard.henderson@linaro.org, eduardo@habkost.net, peterx@redhat.com, david@redhat.com, philmd@linaro.org, marcel.apfelbaum@gmail.com, alex.williamson@redhat.com, imammedo@redhat.com, anisinha@redhat.com, vasant.hegde@amd.com, suravee.suthikulpanit@amd.com, santosh.shukla@amd.com, sarunkod@amd.com, Wei.Huang2@amd.com, Ankit.Soni@amd.com, ethan.milon@eviden.com, joao.m.martins@oracle.com, boris.ostrovsky@oracle.com, alejandro.j.jimenez@oracle.com Subject: [PATCH v3 11/22] amd_iommu: Use iova_tree records to determine large page size on UNMAP Date: Fri, 19 Sep 2025 21:35:04 +0000 Message-ID: <20250919213515.917111-12-alejandro.j.jimenez@oracle.com> X-Mailer: git-send-email 2.43.5 In-Reply-To: <20250919213515.917111-1-alejandro.j.jimenez@oracle.com> References: <20250919213515.917111-1-alejandro.j.jimenez@oracle.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-19_03,2025-09-19_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 phishscore=0 bulkscore=0 adultscore=0 mlxlogscore=999 spamscore=0 mlxscore=0 suspectscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2508110000 definitions=main-2509190201 X-Proofpoint-ORIG-GUID: HCacK4PMSGOErmKEWGqkm-hUGfKK3cOu X-Proofpoint-GUID: HCacK4PMSGOErmKEWGqkm-hUGfKK3cOu X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTE2MDIwMiBTYWx0ZWRfX/5GdS2BGNdmx hUWlxZLpj1BNRgP8ld0sqtJyCndhG2JzfO4MsMBT5/NHfmmAn5uA6IFE26XxqhMRsD9Gt55fc5m oN64TnOG8oZ6a3Zstv+PFIhUonjLShjwzlE8hCo3djZwef63yQzGFvTtMxuirJ4t58hCRjpVr9d oMlXpY7IGyrQGe/qYo3Q1cXMo10aUtq7hb3rDhJbSBnrnTAOdbe8JD8JV+uvuYVqyOf8sOfhdak 4BPNuUjrcb/9IO1QT2614geKHT0OsCM8NFCLLRpg0f/STIs0RqwLwBOnECBamcY7VKE+XTlcU+G 9kNOfYmp7mKly0Uyz8Uwtil7RjlXhZJExcwzeY3tik/ulLZwl0XW8UqMyoBmGtpSOH53Fsns9hc olLHFfNa X-Authority-Analysis: v=2.4 cv=N/QpF39B c=1 sm=1 tr=0 ts=68cdccb3 b=1 cx=c_pps a=WeWmnZmh0fydH62SvGsd2A==:117 a=WeWmnZmh0fydH62SvGsd2A==:17 a=yJojWOMRYYMA:10 a=yPCof4ZbAAAA:8 a=7d1lPJd8Oj0-l-ugTcUA:9 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Keep a record of mapped IOVA ranges per address space, using the iova_tree implementation. Besides enabling optimizations like avoiding unnecessary notifications, a record of existing mappings makes it possible to determine if a specific IOVA is mapped by the guest using a large page, and adjust the size when notifying UNMAP events. When unmapping a large page, the information in the guest PTE encoding the page size is lost, since the guest clears the PTE before issuing the invalidation command to the IOMMU. In such case, the size of the original mapping can be retrieved from the iova_tree and used to issue the UNMAP notification. Using the correct size is essential since the VFIO IOMMU Type1v2 driver in the host kernel will reject unmap requests that do not fully cover previous mappings. Signed-off-by: Alejandro Jimenez --- hw/i386/amd_iommu.c | 95 ++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 89 insertions(+), 6 deletions(-) diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index caae65c4b3565..4376e977f8886 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -33,6 +33,7 @@ #include "hw/i386/apic-msidef.h" #include "hw/qdev-properties.h" #include "kvm/kvm_i386.h" +#include "qemu/iova-tree.h" =20 /* used AMD-Vi MMIO registers */ const char *amdvi_mmio_low[] =3D { @@ -71,6 +72,8 @@ struct AMDVIAddressSpace { IOMMUNotifierFlag notifier_flags; /* entry in list of Address spaces with registered notifiers */ QLIST_ENTRY(AMDVIAddressSpace) next; + /* Record DMA translation ranges */ + IOVATree *iova_tree; }; =20 /* AMDVI cache entry */ @@ -685,6 +688,75 @@ static uint64_t fetch_pte(AMDVIAddressSpace *as, hwadd= r address, uint64_t dte, return 0; } =20 +/* + * Invoke notifiers registered for the address space. Update record of map= ped + * ranges in IOVA Tree. + */ +static void amdvi_notify_iommu(AMDVIAddressSpace *as, IOMMUTLBEvent *event) +{ + IOMMUTLBEntry *entry =3D &event->entry; + + DMAMap target =3D { + .iova =3D entry->iova, + .size =3D entry->addr_mask, + .translated_addr =3D entry->translated_addr, + .perm =3D entry->perm, + }; + + /* + * Search the IOVA Tree for an existing translation for the target, an= d skip + * the notification if the mapping is already recorded. + * When the guest uses large pages, comparing against the record makes= it + * possible to determine the size of the original MAP and adjust the U= NMAP + * request to match it. This avoids failed checks against the mappings= kept + * by the VFIO kernel driver. + */ + const DMAMap *mapped =3D iova_tree_find(as->iova_tree, &target); + + if (event->type =3D=3D IOMMU_NOTIFIER_UNMAP) { + if (!mapped) { + /* No record exists of this mapping, nothing to do */ + return; + } + /* + * Adjust the size based on the original record. This is essential= to + * determine when large/contiguous pages are used, since the guest= has + * already cleared the PTE (erasing the pagesize encoded on it) be= fore + * issuing the invalidation command. + */ + if (mapped->size !=3D target.size) { + assert(mapped->size > target.size); + target.size =3D mapped->size; + /* Adjust event to invoke notifier with correct range */ + entry->addr_mask =3D mapped->size; + } + iova_tree_remove(as->iova_tree, target); + } else { /* IOMMU_NOTIFIER_MAP */ + if (mapped) { + /* + * If a mapping is present and matches the request, skip the + * notification. + */ + if (!memcmp(mapped, &target, sizeof(DMAMap))) { + return; + } else { + /* + * This should never happen unless a buggy guest OS omits = or + * sends incorrect invalidation(s). Report an error in the= event + * it does happen. + */ + error_report("Found conflicting translation. This could be= due " + "to an incorrect or missing invalidation comm= and"); + } + } + /* Record the new mapping */ + iova_tree_insert(as->iova_tree, &target); + } + + /* Invoke the notifiers registered for this address space */ + memory_region_notify_iommu(&as->iommu, 0, *event); +} + /* * Walk the guest page table for an IOVA and range and signal the register= ed * notifiers to sync the shadow page tables in the host. @@ -696,7 +768,7 @@ static void amdvi_sync_shadow_page_table_range(AMDVIAdd= ressSpace *as, { IOMMUTLBEvent event; =20 - hwaddr iova_next, page_mask, pagesize; + hwaddr page_mask, pagesize; hwaddr iova =3D addr; hwaddr end =3D iova + size - 1; =20 @@ -719,7 +791,6 @@ static void amdvi_sync_shadow_page_table_range(AMDVIAdd= ressSpace *as, /* PTE has been validated for major errors and pagesize is set */ assert(pagesize); page_mask =3D ~(pagesize - 1); - iova_next =3D (iova & page_mask) + pagesize; =20 if (ret =3D=3D -AMDVI_FR_PT_ENTRY_INV) { /* @@ -752,15 +823,26 @@ static void amdvi_sync_shadow_page_table_range(AMDVIA= ddressSpace *as, event.type =3D IOMMU_NOTIFIER_MAP; } =20 - /* Invoke the notifiers registered for this address space */ - memory_region_notify_iommu(&as->iommu, 0, event); + /* + * The following call might need to adjust event.entry.size in cas= es + * where the guest unmapped a series of large pages. + */ + amdvi_notify_iommu(as, &event); + /* + * In the special scenario where the guest is unmapping a large pa= ge, + * addr_mask has been adjusted before sending the notification. Up= date + * pagesize accordingly in order to correctly compute the next IOV= A. + */ + pagesize =3D event.entry.addr_mask + 1; =20 next: + iova &=3D ~(pagesize - 1); + /* Check for 64-bit overflow and terminate walk in such cases */ - if (iova_next < iova) { + if ((iova + pagesize) < iova) { break; } else { - iova =3D iova_next; + iova +=3D pagesize; } } } @@ -1845,6 +1927,7 @@ static AddressSpace *amdvi_host_dma_iommu(PCIBus *bus= , void *opaque, int devfn) iommu_as[devfn]->devfn =3D (uint8_t)devfn; iommu_as[devfn]->iommu_state =3D s; iommu_as[devfn]->notifier_flags =3D IOMMU_NOTIFIER_NONE; + iommu_as[devfn]->iova_tree =3D iova_tree_new(); =20 amdvi_dev_as =3D iommu_as[devfn]; =20 --=20 2.43.5 From nobody Sun Sep 28 16:28:07 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oracle.com ARC-Seal: i=1; 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Fri, 19 Sep 2025 21:35:47 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oracle.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=corp-2025-04-25; bh=/9+0K CE3r5tkaFKWr1+qwyZdMZMZ2is8s5wftLUBkCk=; b=bgSvd0vkZ8BVZFTtkKHaB ylyx8pkazr8z+c0cDJWpbJ8C7DOmOa43XJKjbgRcvYezge6KJFnkivPuvo3vboHd 7rHKXTRN2whlPnfr2o92++BV3AJy7uIaPhVuue0+amzUT+VYtscEpZ4gSJZ32+Tz yb69Bw65DLWc64rZcc0Ju8vXZ6mlEm2pGWZKUXUscZ3QuEUv/UNy57EsvQ9VT18X Ky0kYns4ItAoluqqY/3cTY+INuVifAAngvPDBR3DBZaKvnU1ta8Cp7a31MvQrN0t DqNieHFDhU5gqYBQBmWcgJAEeWJ7lHdIThvdUhC/THwQRN+mytBllYF4kM7ZDKjh Q== From: Alejandro Jimenez To: qemu-devel@nongnu.org Cc: mst@redhat.com, clement.mathieu--drif@eviden.com, pbonzini@redhat.com, richard.henderson@linaro.org, eduardo@habkost.net, peterx@redhat.com, david@redhat.com, philmd@linaro.org, marcel.apfelbaum@gmail.com, alex.williamson@redhat.com, imammedo@redhat.com, anisinha@redhat.com, vasant.hegde@amd.com, suravee.suthikulpanit@amd.com, santosh.shukla@amd.com, sarunkod@amd.com, Wei.Huang2@amd.com, Ankit.Soni@amd.com, ethan.milon@eviden.com, joao.m.martins@oracle.com, boris.ostrovsky@oracle.com, alejandro.j.jimenez@oracle.com Subject: [PATCH v3 12/22] amd_iommu: Unmap all address spaces under the AMD IOMMU on reset Date: Fri, 19 Sep 2025 21:35:05 +0000 Message-ID: <20250919213515.917111-13-alejandro.j.jimenez@oracle.com> X-Mailer: git-send-email 2.43.5 In-Reply-To: <20250919213515.917111-1-alejandro.j.jimenez@oracle.com> References: <20250919213515.917111-1-alejandro.j.jimenez@oracle.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-19_03,2025-09-19_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 phishscore=0 bulkscore=0 adultscore=0 mlxlogscore=999 spamscore=0 mlxscore=0 suspectscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2508110000 definitions=main-2509190201 X-Proofpoint-GUID: z6S4R3qRbT8cDZs2vKHfSO2MrD16wihO X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTE2MDIwMiBTYWx0ZWRfX3Qc59lY9vZEb sYnYp+IW2dVl9iYrfBYH+JXLC1c0a3mjwQQkMAAlbTe4yaTT0QsAkYMdiNBpypQF3jdfRHmXPQV 4uNSayNKQFa8wsHtUFXBM3uRhqkKaOhm50/q4lg3xV39S0O/eyN/NpAegC92dRolxv+BNiBxQnm ZS8+lgymIth63UDfauIFo6VDOwMnn+8081EUVDWdZPvYmzCK7EISqIUoFUBKuiRNZU9JGmJqZkk 5mQpuj7kUBz+OBlQ+cBxOMj0TnJRQcfKf+LvrGCZgWFgixssmIYpoG4agr9uXC4moi8eb4ZJYmd G33R9xIIdc3GWkAAupPa2JPOrP/5SlPiS1RL6ZeZ0mRj4VOVuvODz+S6yu/cdkKtbuLlKDtnZZO TjqJTTkk X-Authority-Analysis: v=2.4 cv=cerSrmDM c=1 sm=1 tr=0 ts=68cdccb5 b=1 cx=c_pps a=WeWmnZmh0fydH62SvGsd2A==:117 a=WeWmnZmh0fydH62SvGsd2A==:17 a=yJojWOMRYYMA:10 a=yPCof4ZbAAAA:8 a=0R8M-FwGblI3YPkDnqAA:9 X-Proofpoint-ORIG-GUID: z6S4R3qRbT8cDZs2vKHfSO2MrD16wihO Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Support dropping all existing mappings on reset. When the guest kernel reboots it will create new ones, but other components that run before the kernel (e.g. OVMF) should not be able to use existing mappings from the previous boot. Signed-off-by: Alejandro Jimenez --- hw/i386/amd_iommu.c | 74 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 74 insertions(+) diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index 4376e977f8886..497f18c540666 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -847,6 +847,77 @@ next: } } =20 +/* + * Unmap entire range that the notifier registered for i.e. the full AS. + * + * This is seemingly technically equivalent to directly calling + * memory_region_unmap_iommu_notifier_range(), but it allows to check for + * notifier boundaries and issue notifications with ranges within those bo= unds. + */ +static void amdvi_address_space_unmap(AMDVIAddressSpace *as, IOMMUNotifier= *n) +{ + + hwaddr start =3D n->start; + hwaddr end =3D n->end; + hwaddr remain; + DMAMap map; + + assert(start <=3D end); + remain =3D end - start + 1; + + /* + * Divide the notifier range into chunks that are aligned and do not e= xceed + * the notifier boundaries. + */ + while (remain >=3D AMDVI_PAGE_SIZE) { + + IOMMUTLBEvent event; + + uint64_t mask =3D dma_aligned_pow2_mask(start, end, 64); + + event.type =3D IOMMU_NOTIFIER_UNMAP; + + IOMMUTLBEntry entry =3D { + .target_as =3D &address_space_memory, + .iova =3D start, + .translated_addr =3D 0, /* irrelevant for unmap case */ + .addr_mask =3D mask, + .perm =3D IOMMU_NONE, + }; + event.entry =3D entry; + + /* Call notifier registered for updates on this address space */ + memory_region_notify_iommu_one(n, &event); + + start +=3D mask + 1; + remain -=3D mask + 1; + } + + assert(!remain); + + map.iova =3D n->start; + map.size =3D n->end - n->start; + + iova_tree_remove(as->iova_tree, map); +} + +/* + * For all the address spaces with notifiers registered, unmap the entire = range + * the notifier registered for i.e. clear all the address spaces managed b= y the + * IOMMU. + */ +static void amdvi_address_space_unmap_all(AMDVIState *s) +{ + AMDVIAddressSpace *as; + IOMMUNotifier *n; + + QLIST_FOREACH(as, &s->amdvi_as_with_notifiers, next) { + IOMMU_NOTIFIER_FOREACH(n, &as->iommu) { + amdvi_address_space_unmap(as, n); + } + } +} + /* log error without aborting since linux seems to be using reserved bits = */ static void amdvi_inval_devtab_entry(AMDVIState *s, uint64_t *cmd) { @@ -2099,6 +2170,9 @@ static void amdvi_sysbus_reset(DeviceState *dev) =20 msi_reset(&s->pci->dev); amdvi_init(s); + + /* Discard all mappings on device reset */ + amdvi_address_space_unmap_all(s); } =20 static const VMStateDescription vmstate_amdvi_sysbus_migratable =3D { --=20 2.43.5 From nobody Sun Sep 28 16:28:07 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oracle.com ARC-Seal: i=1; a=rsa-sha256; t=1758317813; cv=none; d=zohomail.com; s=zohoarc; b=UE1KiJ2qu+aZfJPCCGK25hLanQ5ZiIeAhLI346d06VQkKYQQM3k9TJJFQsTW3J82238pucPbjAxBHRkG5F7efuAOmGCviKFsH57jaLc2LqG33SHlgdEH94jWKWqYjbZkLe1bypiSauA2tz+yZ/eE0BkUX197mRlqmhfAzNOP3oc= ARC-Message-Signature: i=1; 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charset="utf-8" A replay() method is necessary to efficiently synchronize the host page tables after VFIO registers a notifier for IOMMU events. It is called to ensure that existing mappings from an IOMMU memory region are "replayed" to a specified notifier, initializing or updating the shadow page tables on the host. Signed-off-by: Alejandro Jimenez --- hw/i386/amd_iommu.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index 497f18c540666..9027f7c0544a7 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -918,6 +918,29 @@ static void amdvi_address_space_unmap_all(AMDVIState *= s) } } =20 +/* + * For every translation present in the IOMMU, construct IOMMUTLBEntry data + * and pass it as parameter to notifier callback. + */ +static void amdvi_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier = *n) +{ + AMDVIAddressSpace *as =3D container_of(iommu_mr, AMDVIAddressSpace, io= mmu); + uint64_t dte[4] =3D { 0 }; + + if (!(n->notifier_flags & IOMMU_NOTIFIER_MAP)) { + return; + } + + if (amdvi_as_to_dte(as, dte)) { + return; + } + + /* Dropping all mappings for the address space. Also clears the IOVA t= ree */ + amdvi_address_space_unmap(as, n); + + amdvi_sync_shadow_page_table_range(as, &dte[0], 0, UINT64_MAX, false); +} + /* log error without aborting since linux seems to be using reserved bits = */ static void amdvi_inval_devtab_entry(AMDVIState *s, uint64_t *cmd) { @@ -2364,6 +2387,7 @@ static void amdvi_iommu_memory_region_class_init(Obje= ctClass *klass, =20 imrc->translate =3D amdvi_translate; imrc->notify_flag_changed =3D amdvi_iommu_notify_flag_changed; + imrc->replay =3D amdvi_iommu_replay; } =20 static const TypeInfo amdvi_iommu_memory_region_info =3D { --=20 2.43.5 From nobody Sun Sep 28 16:28:07 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oracle.com ARC-Seal: i=1; a=rsa-sha256; t=1758317991; cv=none; d=zohomail.com; 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charset="utf-8" When the kernel IOMMU driver issues an INVALIDATE_IOMMU_ALL, the address translation and interrupt remapping information must be cleared for all Device IDs and all domains. Introduce a helper to sync the shadow page table for all the address spaces with registered notifiers, which replays both MAP and UNMAP events. Signed-off-by: Alejandro Jimenez --- hw/i386/amd_iommu.c | 48 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index 9027f7c0544a7..d74d42b3dda8e 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -941,6 +941,47 @@ static void amdvi_iommu_replay(IOMMUMemoryRegion *iomm= u_mr, IOMMUNotifier *n) amdvi_sync_shadow_page_table_range(as, &dte[0], 0, UINT64_MAX, false); } =20 +static void amdvi_address_space_sync(AMDVIAddressSpace *as) +{ + IOMMUNotifier *n; + uint64_t dte[4] =3D { 0 }; + + /* If only UNMAP notifiers are registered, drop all existing mappings = */ + if (!(as->notifier_flags & IOMMU_NOTIFIER_MAP)) { + IOMMU_NOTIFIER_FOREACH(n, &as->iommu) { + /* + * Directly calling memory_region_unmap_iommu_notifier_range()= does + * not guarantee that the addr_mask eventually passed as param= eter + * to the notifier is valid. Use amdvi_address_space_unmap() w= hich + * ensures the notifier range is divided into properly aligned + * regions, and issues notifications for each one. + */ + amdvi_address_space_unmap(as, n); + } + return; + } + + if (amdvi_as_to_dte(as, dte)) { + return; + } + + amdvi_sync_shadow_page_table_range(as, &dte[0], 0, UINT64_MAX, true); +} + +/* + * This differs from the replay() method in that it issues both MAP and UN= MAP + * notifications since it is called after global invalidation events in or= der to + * re-sync all address spaces. + */ +static void amdvi_iommu_address_space_sync_all(AMDVIState *s) +{ + AMDVIAddressSpace *as; + + QLIST_FOREACH(as, &s->amdvi_as_with_notifiers, next) { + amdvi_address_space_sync(as); + } +} + /* log error without aborting since linux seems to be using reserved bits = */ static void amdvi_inval_devtab_entry(AMDVIState *s, uint64_t *cmd) { @@ -983,6 +1024,13 @@ static void amdvi_inval_all(AMDVIState *s, uint64_t *= cmd) amdvi_intremap_inval_notify_all(s, true, 0, 0); =20 amdvi_iotlb_reset(s); + + /* + * Fully replay the address space i.e. send both UNMAP and MAP events = in + * order to synchronize guest and host IO page tables tables. + */ + amdvi_iommu_address_space_sync_all(s); + trace_amdvi_all_inval(); } =20 --=20 2.43.5 From nobody Sun Sep 28 16:28:07 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oracle.com ARC-Seal: i=1; a=rsa-sha256; t=1758317816; cv=none; d=zohomail.com; s=zohoarc; b=P0JcgP2ZNcpoOj0tsp81X8N5DZn5dmdZy/ne9B/G2eJS9lQa/vYylOZRS77yed8148LQTlNbPwtFppo4KdyOklzaiaz6CO8iRtTNuhIkYLY3OqS0mVFpNu4RTel3q9/V066QpiJlYd/Duf/QQvw0SN7cwd/rbPiIGR+03p42diI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758317816; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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charset="utf-8" Enable the appropriate memory region for an address space depending on the address translation mode selected for it. This is currently based on a generic x86 IOMMU property, and only done during the address space initialization. Extract the code into a helper and toggle the regions based on whether the specific address space is using address translation (via the newly introduced addr_translation field). Later, region activation will also be controlled by availability of DMA remapping capability (via dma-remap property to be introduced in follow up changes). Signed-off-by: Alejandro Jimenez --- hw/i386/amd_iommu.c | 23 +++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index d74d42b3dda8e..67a26f524706b 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -74,6 +74,8 @@ struct AMDVIAddressSpace { QLIST_ENTRY(AMDVIAddressSpace) next; /* Record DMA translation ranges */ IOVATree *iova_tree; + /* DMA address translation active */ + bool addr_translation; }; =20 /* AMDVI cache entry */ @@ -982,6 +984,23 @@ static void amdvi_iommu_address_space_sync_all(AMDVISt= ate *s) } } =20 +/* + * Toggle between address translation and passthrough modes by enabling the + * corresponding memory regions. + */ +static void amdvi_switch_address_space(AMDVIAddressSpace *amdvi_as) +{ + if (amdvi_as->addr_translation) { + /* Enabling DMA region */ + memory_region_set_enabled(&amdvi_as->iommu_nodma, false); + memory_region_set_enabled(MEMORY_REGION(&amdvi_as->iommu), true); + } else { + /* Disabling DMA region, using passthrough */ + memory_region_set_enabled(MEMORY_REGION(&amdvi_as->iommu), false); + memory_region_set_enabled(&amdvi_as->iommu_nodma, true); + } +} + /* log error without aborting since linux seems to be using reserved bits = */ static void amdvi_inval_devtab_entry(AMDVIState *s, uint64_t *cmd) { @@ -2070,6 +2089,7 @@ static AddressSpace *amdvi_host_dma_iommu(PCIBus *bus= , void *opaque, int devfn) iommu_as[devfn]->iommu_state =3D s; iommu_as[devfn]->notifier_flags =3D IOMMU_NOTIFIER_NONE; iommu_as[devfn]->iova_tree =3D iova_tree_new(); + iommu_as[devfn]->addr_translation =3D false; =20 amdvi_dev_as =3D iommu_as[devfn]; =20 @@ -2112,8 +2132,7 @@ static AddressSpace *amdvi_host_dma_iommu(PCIBus *bus= , void *opaque, int devfn) AMDVI_INT_ADDR_FIRST, &amdvi_dev_as->iommu_ir, 1); =20 - memory_region_set_enabled(&amdvi_dev_as->iommu_nodma, false); - memory_region_set_enabled(MEMORY_REGION(&amdvi_dev_as->iommu), tru= e); + amdvi_switch_address_space(amdvi_dev_as); } return &iommu_as[devfn]->as; } --=20 2.43.5 From nobody Sun Sep 28 16:28:07 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Fri, 19 Sep 2025 21:35:57 GMT Received: from alaljimee5bm-ol9-20250405.osdevelopmeniad.oraclevcn.com (alaljimee5bm-ol9-20250405.allregionaliads.osdevelopmeniad.oraclevcn.com [100.100.254.235]) by phxpaimrmta03.imrmtpd1.prodappphxaev1.oraclevcn.com (PPS) with ESMTP id 494y2gwra3-17; Fri, 19 Sep 2025 21:35:57 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oracle.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=corp-2025-04-25; bh=ryenD os+M1PXZvVQZvc90q+nONMqUaP5DpPVnLvfdhE=; b=HtI3uWn6mx6s5PUyVVYnJ 3x3iu/GqOgwCT9MOP7aB5D3ARNAvOP00q/sFgd1ulnrVEusD+2wwh5p6vH2XceTr XCsH+onxJHRa7OfHITnp+BXlDEwCb1HMQUxtO3p14oeWPljD6QgCcgRkFme+u4gr FoiQdQ/eUFPFOVjV4jMwrI7u002iK4gleASQIPjnLi5DrqUqxg6HVT8qoHGOsRQa AWvg8MzhEPZf1l7tsZGHnk+dobU7gxQORal2sR1ckzdgNh4S3l4tfvjrQaJPL0Cy 1zE2MbFxe84diwhuHSlV8XFUom1FAuKIMlr63nLikn4XrfI5YNFTBmO6y0/PYaGv Q== From: Alejandro Jimenez To: qemu-devel@nongnu.org Cc: mst@redhat.com, clement.mathieu--drif@eviden.com, pbonzini@redhat.com, richard.henderson@linaro.org, eduardo@habkost.net, peterx@redhat.com, david@redhat.com, philmd@linaro.org, marcel.apfelbaum@gmail.com, alex.williamson@redhat.com, imammedo@redhat.com, anisinha@redhat.com, vasant.hegde@amd.com, suravee.suthikulpanit@amd.com, santosh.shukla@amd.com, sarunkod@amd.com, Wei.Huang2@amd.com, Ankit.Soni@amd.com, ethan.milon@eviden.com, joao.m.martins@oracle.com, boris.ostrovsky@oracle.com, alejandro.j.jimenez@oracle.com Subject: [PATCH v3 16/22] amd_iommu: Set all address spaces to use passthrough mode on reset Date: Fri, 19 Sep 2025 21:35:09 +0000 Message-ID: <20250919213515.917111-17-alejandro.j.jimenez@oracle.com> X-Mailer: git-send-email 2.43.5 In-Reply-To: <20250919213515.917111-1-alejandro.j.jimenez@oracle.com> References: <20250919213515.917111-1-alejandro.j.jimenez@oracle.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-19_03,2025-09-19_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 phishscore=0 bulkscore=0 adultscore=0 mlxlogscore=999 spamscore=0 mlxscore=0 suspectscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2508110000 definitions=main-2509190201 X-Authority-Analysis: v=2.4 cv=TqbmhCXh c=1 sm=1 tr=0 ts=68cdccbe b=1 cx=c_pps a=WeWmnZmh0fydH62SvGsd2A==:117 a=WeWmnZmh0fydH62SvGsd2A==:17 a=yJojWOMRYYMA:10 a=yPCof4ZbAAAA:8 a=TyYeUvuNVc17vi0sGpoA:9 a=+jEqtf1s3R9VXZ0wqowq2kgwd+I=:19 X-Proofpoint-GUID: 9Giyg3iRePjXw3btv5P91ofstwVHx-_4 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTE2MDIwMiBTYWx0ZWRfX4DiKxvkQXSv0 fxr5wkiKymRpT7/DHiNO9rFQfrlWcgWNtirQl3kvffRvYzEzglKiGi6haIy0j05Co0H0DkwWZtQ JYkhnw4z4hojQhjV6LSwI9/pDCVzbyqd4HJE0oIkDH9Mev5nDzbNvkkNkdLHpGYipB5dF6SoL9g 3bxK8jvi91NJKkInTQlQrDg4aZUwCf5/MwDGggRzqtDBDbNEBwHz5joFe9NXVlw8BFfkqMY/bEy o21al+BPdBUduYSoGgVwJxU6N5X0uaqunPhWVqb+RL5WzJp32gMKJm6fnytOao5FyE8tiKa1uqS gPkOnq1eO7CBorX2n6N3Ti66Sb5U4HMc9qRjVdsY8FGeyRc495Z4xhJL9OBtvG7Zw6bkA+qzdSn OEkOAQAe X-Proofpoint-ORIG-GUID: 9Giyg3iRePjXw3btv5P91ofstwVHx-_4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" On reset, restore the default address translation mode (passthrough) for all the address spaces managed by the vIOMMU. Signed-off-by: Alejandro Jimenez --- hw/i386/amd_iommu.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index 67a26f524706b..e9ce7b46e854f 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -1001,6 +1001,35 @@ static void amdvi_switch_address_space(AMDVIAddressS= pace *amdvi_as) } } =20 +/* + * For all existing address spaces managed by the IOMMU, enable/disable the + * corresponding memory regions to reset the address translation mode and + * use passthrough by default. + */ +static void amdvi_reset_address_translation_all(AMDVIState *s) +{ + AMDVIAddressSpace **iommu_as; + + for (int bus_num =3D 0; bus_num < PCI_BUS_MAX; bus_num++) { + + /* Nothing to do if there are no devices on the current bus */ + if (!s->address_spaces[bus_num]) { + continue; + } + iommu_as =3D s->address_spaces[bus_num]; + + for (int devfn =3D 0; devfn < PCI_DEVFN_MAX; devfn++) { + + if (!iommu_as[devfn]) { + continue; + } + /* Use passthrough as default mode after reset */ + iommu_as[devfn]->addr_translation =3D false; + amdvi_switch_address_space(iommu_as[devfn]); + } + } +} + /* log error without aborting since linux seems to be using reserved bits = */ static void amdvi_inval_devtab_entry(AMDVIState *s, uint64_t *cmd) { @@ -2263,6 +2292,7 @@ static void amdvi_sysbus_reset(DeviceState *dev) =20 /* Discard all mappings on device reset */ amdvi_address_space_unmap_all(s); + amdvi_reset_address_translation_all(s); } =20 static const VMStateDescription vmstate_amdvi_sysbus_migratable =3D { --=20 2.43.5 From nobody Sun Sep 28 16:28:07 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oracle.com ARC-Seal: i=1; a=rsa-sha256; t=1758317816; cv=none; d=zohomail.com; s=zohoarc; b=Cy9nUSRlAwknVkHHSI0RIu2Jnm01eUqSWE5I3OGKJqk+ZhBj3TVQsNmt1JjclTvHOZcLVyVX20ViuMfrWZ2YUR1PibtHJj6Vk1Q4ofHKnQdxT949lloxQYv89CuASNzULciIvXEgOJHNyUxr4aOoZGUlWi1E5gfH4tH2dzAIFNM= ARC-Message-Signature: i=1; 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charset="utf-8" In order to enable device assignment with IOMMU protection and guest DMA address translation, IOMMU MAP notifier support is necessary to allow users like VFIO to synchronize the shadow page tables i.e. to receive notifications when the guest updates its I/O page tables and replay the mappings onto host I/O page tables. Provide a new dma-remap property to govern the ability to register for MAP notifications, effectively providing global control over the DMA address translation functionality that was implemented in previous changes. Note that DMA remapping support also requires the vIOMMU is configured with the NpCache capability, so a guest driver issues IOMMU invalidations for both map() and unmap() operations. This capability is already set by default and written to the configuration in amdvi_pci_realize() as part of AMDVI_CAPAB_FEATURES. Signed-off-by: Alejandro Jimenez --- hw/i386/amd_iommu.c | 24 +++++++++++++++++------- hw/i386/amd_iommu.h | 3 +++ 2 files changed, 20 insertions(+), 7 deletions(-) diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index e9ce7b46e854f..ce5d4c36624fd 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -990,7 +990,9 @@ static void amdvi_iommu_address_space_sync_all(AMDVISta= te *s) */ static void amdvi_switch_address_space(AMDVIAddressSpace *amdvi_as) { - if (amdvi_as->addr_translation) { + AMDVIState *s =3D amdvi_as->iommu_state; + + if (s->dma_remap && amdvi_as->addr_translation) { /* Enabling DMA region */ memory_region_set_enabled(&amdvi_as->iommu_nodma, false); memory_region_set_enabled(MEMORY_REGION(&amdvi_as->iommu), true); @@ -2193,12 +2195,19 @@ static int amdvi_iommu_notify_flag_changed(IOMMUMem= oryRegion *iommu, AMDVIAddressSpace *as =3D container_of(iommu, AMDVIAddressSpace, iommu= ); AMDVIState *s =3D as->iommu_state; =20 - if (new & IOMMU_NOTIFIER_MAP) { - error_setg(errp, - "device %02x.%02x.%x requires iommu notifier which is n= ot " - "currently supported", as->bus_num, PCI_SLOT(as->devfn), - PCI_FUNC(as->devfn)); - return -EINVAL; + /* + * Accurate synchronization of the vIOMMU page tables required to supp= ort + * MAP notifiers is provided by the dma-remap feature. In addition, th= is + * also requires that the vIOMMU presents the NpCache capability, so a= guest + * driver issues invalidations for both map() and unmap() operations. = The + * capability is already set by default as part of AMDVI_CAPAB_FEATURE= S and + * written to the configuration in amdvi_pci_realize(). + */ + if (!s->dma_remap && (new & IOMMU_NOTIFIER_MAP)) { + error_setg_errno(errp, ENOTSUP, + "device %02x.%02x.%x requires dma-remap=3D1", + as->bus_num, PCI_SLOT(as->devfn), PCI_FUNC(as->devfn)); + return -ENOTSUP; } =20 /* @@ -2423,6 +2432,7 @@ static void amdvi_sysbus_realize(DeviceState *dev, Er= ror **errp) static const Property amdvi_properties[] =3D { DEFINE_PROP_BOOL("xtsup", AMDVIState, xtsup, false), DEFINE_PROP_STRING("pci-id", AMDVIState, pci_id), + DEFINE_PROP_BOOL("dma-remap", AMDVIState, dma_remap, false), }; =20 static const VMStateDescription vmstate_amdvi_sysbus =3D { diff --git a/hw/i386/amd_iommu.h b/hw/i386/amd_iommu.h index b51aa74368995..e1354686b6f03 100644 --- a/hw/i386/amd_iommu.h +++ b/hw/i386/amd_iommu.h @@ -418,6 +418,9 @@ struct AMDVIState { /* Interrupt remapping */ bool ga_enabled; bool xtsup; + + /* DMA address translation */ + bool dma_remap; }; =20 uint64_t amdvi_extended_feature_register(AMDVIState *s); --=20 2.43.5 From nobody Sun Sep 28 16:28:07 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oracle.com ARC-Seal: i=1; a=rsa-sha256; t=1758317927; cv=none; d=zohomail.com; s=zohoarc; b=LzuTmPj+gAnHNgZN0VF9GT0u89acqfuBpJpcqRyMXHliPQgtpRsWanKWH2lSuabVNkTNUdDNIeHK4zxLsmewnWXBw0RYDipByuLIBKfHuakTbvtfIRja0TRGEBgR1zBMBLOIfmLNmRG/8c2EmhtHfgvuS4g1idEf8KG2wr4Cv5E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758317927; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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charset="utf-8" A guest must issue an INVALIDATE_DEVTAB_ENTRY command after changing a Device Table entry (DTE) e.g. after attaching a device and setting up its DTE. When intercepting this event, determine if the DTE has been configured for paging or not, and toggle the appropriate memory regions to allow DMA address translation for the address space if needed. Requires dma-remap=3Do= n. Signed-off-by: Alejandro Jimenez --- hw/i386/amd_iommu.c | 122 +++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 120 insertions(+), 2 deletions(-) diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index ce5d4c36624fd..e916dcb2be381 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -1032,18 +1032,136 @@ static void amdvi_reset_address_translation_all(AM= DVIState *s) } } =20 +static void enable_dma_mode(AMDVIAddressSpace *as, bool inval_current) +{ + /* + * When enabling DMA mode for the purpose of isolating guest devices on + * a failure to retrieve or invalid DTE, all existing mappings must be + * dropped. + */ + if (inval_current) { + IOMMUNotifier *n; + IOMMU_NOTIFIER_FOREACH(n, &as->iommu) { + amdvi_address_space_unmap(as, n); + } + } + + if (as->addr_translation) { + return; + } + + /* Installing DTE enabling translation, activate region */ + as->addr_translation =3D true; + amdvi_switch_address_space(as); + /* Sync shadow page tables */ + amdvi_address_space_sync(as); +} + +/* + * If paging was previously in use in the address space + * - invalidate all existing mappings + * - switch to no_dma memory region + */ +static void enable_nodma_mode(AMDVIAddressSpace *as) +{ + IOMMUNotifier *n; + + if (!as->addr_translation) { + /* passthrough is already active, nothing to do */ + return; + } + + as->addr_translation =3D false; + IOMMU_NOTIFIER_FOREACH(n, &as->iommu) { + /* Drop all mappings for the address space */ + amdvi_address_space_unmap(as, n); + } + amdvi_switch_address_space(as); +} + +/* + * A guest driver must issue the INVALIDATE_DEVTAB_ENTRY command to the IO= MMU + * after changing a Device Table entry. We can use this fact to detect whe= n a + * Device Table entry is created for a device attached to a paging domain = and + * enable the corresponding IOMMU memory region to allow for DMA translati= on if + * appropriate. + */ +static void amdvi_update_addr_translation_mode(AMDVIState *s, uint16_t dev= id) +{ + uint8_t bus_num, devfn, dte_mode; + AMDVIAddressSpace *as; + uint64_t dte[4] =3D { 0 }; + int ret; + + /* + * Convert the devid encoded in the command to a bus and devfn in + * order to retrieve the corresponding address space. + */ + bus_num =3D PCI_BUS_NUM(devid); + devfn =3D devid & 0xff; + + /* + * The main buffer of size (AMDVIAddressSpace *) * (PCI_BUS_MAX) has a= lready + * been allocated within AMDVIState, but must be careful to not access + * unallocated devfn. + */ + if (!s->address_spaces[bus_num] || !s->address_spaces[bus_num][devfn])= { + return; + } + as =3D s->address_spaces[bus_num][devfn]; + + ret =3D amdvi_as_to_dte(as, dte); + + if (!ret) { + dte_mode =3D (dte[0] >> AMDVI_DEV_MODE_RSHIFT) & AMDVI_DEV_MODE_MA= SK; + } + + switch (ret) { + case 0: + /* DTE was successfully retrieved */ + if (!dte_mode) { + enable_nodma_mode(as); /* DTE[V]=3D1 && DTE[Mode]=3D0 =3D> pas= sthrough */ + } else { + enable_dma_mode(as, false); /* Enable DMA translation */ + } + break; + case -AMDVI_FR_DTE_V: + /* DTE[V]=3D0, address is passed untranslated */ + enable_nodma_mode(as); + break; + case -AMDVI_FR_DTE_RTR_ERR: + case -AMDVI_FR_DTE_TV: + /* + * Enforce isolation by using DMA in rare scenarios where the DTE = cannot + * be retrieved or DTE[TV]=3D0. Existing mappings are dropped. + */ + enable_dma_mode(as, true); + break; + } +} + /* log error without aborting since linux seems to be using reserved bits = */ static void amdvi_inval_devtab_entry(AMDVIState *s, uint64_t *cmd) { uint16_t devid =3D cpu_to_le16((uint16_t)extract64(cmd[0], 0, 16)); =20 + trace_amdvi_devtab_inval(PCI_BUS_NUM(devid), PCI_SLOT(devid), + PCI_FUNC(devid)); + /* This command should invalidate internal caches of which there isn't= */ if (extract64(cmd[0], 16, 44) || cmd[1]) { amdvi_log_illegalcom_error(s, extract64(cmd[0], 60, 4), s->cmdbuf + s->cmdbuf_head); + return; + } + + /* + * When DMA remapping capability is enabled, check if updated DTE is s= etup + * for paging or not, and configure the corresponding memory regions. + */ + if (s->dma_remap) { + amdvi_update_addr_translation_mode(s, devid); } - trace_amdvi_devtab_inval(PCI_BUS_NUM(devid), PCI_SLOT(devid), - PCI_FUNC(devid)); } =20 static void amdvi_complete_ppr(AMDVIState *s, uint64_t *cmd) --=20 2.43.5 From nobody Sun Sep 28 16:28:07 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Fri, 19 Sep 2025 21:36:04 GMT Received: from alaljimee5bm-ol9-20250405.osdevelopmeniad.oraclevcn.com (alaljimee5bm-ol9-20250405.allregionaliads.osdevelopmeniad.oraclevcn.com [100.100.254.235]) by phxpaimrmta03.imrmtpd1.prodappphxaev1.oraclevcn.com (PPS) with ESMTP id 494y2gwra3-20; Fri, 19 Sep 2025 21:36:04 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oracle.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=corp-2025-04-25; bh=7OX4F NJlDrRvRn4oSTf+7azUzekRazrLSeDU9YZSaKQ=; b=d3KoWzLZHvDWRFZF6QeV/ 3HGnRP+FkyMDstbeNT/m5Xa09wfKEWoX5gDgDbNql/OKaLxi4emCmc1dVvljQnX5 k1iDoU02IICZqOeWKADA57Y+hrOGGM9PvYxmvRijMbzSX2oiE4eSaW9U8nqFEReI 3sMIwzH2I/yykJwyqlbrXjoHIDfe3Iq4IiU0S+Ms5rViuo1nroLyE9pXECXzw01+ oY+5GRuCcHnrOQfu53JjqvJ0zJoo59nTgb9bFw7CJ2rau4bNJh2aEcHZO5WmjnxZ FXhp7u3WfMNfNF21z3I0sSMDNQ+b7pXjxu4gmlN7NLaYmi5dzpJLFsSyc8ljWuFQ g== From: Alejandro Jimenez To: qemu-devel@nongnu.org Cc: mst@redhat.com, clement.mathieu--drif@eviden.com, pbonzini@redhat.com, richard.henderson@linaro.org, eduardo@habkost.net, peterx@redhat.com, david@redhat.com, philmd@linaro.org, marcel.apfelbaum@gmail.com, alex.williamson@redhat.com, imammedo@redhat.com, anisinha@redhat.com, vasant.hegde@amd.com, suravee.suthikulpanit@amd.com, santosh.shukla@amd.com, sarunkod@amd.com, Wei.Huang2@amd.com, Ankit.Soni@amd.com, ethan.milon@eviden.com, joao.m.martins@oracle.com, boris.ostrovsky@oracle.com, alejandro.j.jimenez@oracle.com Subject: [PATCH v3 19/22] amd_iommu: Do not assume passthrough translation when DTE[TV]=0 Date: Fri, 19 Sep 2025 21:35:12 +0000 Message-ID: <20250919213515.917111-20-alejandro.j.jimenez@oracle.com> X-Mailer: git-send-email 2.43.5 In-Reply-To: <20250919213515.917111-1-alejandro.j.jimenez@oracle.com> References: <20250919213515.917111-1-alejandro.j.jimenez@oracle.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-19_03,2025-09-19_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 phishscore=0 bulkscore=0 adultscore=0 mlxlogscore=999 spamscore=0 mlxscore=0 suspectscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2508110000 definitions=main-2509190201 X-Authority-Analysis: v=2.4 cv=JNU7s9Kb c=1 sm=1 tr=0 ts=68cdccc6 b=1 cx=c_pps a=WeWmnZmh0fydH62SvGsd2A==:117 a=WeWmnZmh0fydH62SvGsd2A==:17 a=yJojWOMRYYMA:10 a=yPCof4ZbAAAA:8 a=QsCEJq6UzS2LWQETwqwA:9 X-Proofpoint-ORIG-GUID: Ds6zCs30wDmsxPXSL-e64wSqQWoTQPKU X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTE2MDIwMiBTYWx0ZWRfX1pgJQ6fR8RHW NjiEPMNFzwsBl9Lpp08qpc/Q81pugSSK6Ehu0z2i9/MxJnwHnOUcA2kacicZiNj2Luk97IT12aZ TN65wVwrXsuOfFHRbaR5vgsphl8u3Gi3V4Tk/IAcGKBoGidkl0QzSrfgK5xLKLQh0ISZ7dRjd4X rr9HK64XWDRN3WWBtRcmTEEEyJExCsykYg/OHatq2ienqttMlYV89zHz2nXNtvLcWhBBlnuQBCa HAAA8SKauDxMmjGwu4VSCXezrZ16vtBTdrebkgeAjj+8LL+UjyxhjwH5kaKRE6gZIHpGwiAHu4X 5VQ7lrlNy4ZbvH3hkjAqYTyb3/0EeFUVCLiB2mq63/H3XToVrTisGz38TFdW7rzTbMhoHTPpVRt /rxtkuEJ X-Proofpoint-GUID: Ds6zCs30wDmsxPXSL-e64wSqQWoTQPKU Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" The AMD I/O Virtualization Technology (IOMMU) Specification (see Table 8: V, TV, and GV Fields in Device Table Entry), specifies that a DTE with V=3D1, TV=3D0 does not contain a valid address translation information. If a request requires a table walk, the walk is terminated when this condition is encountered. Do not assume that addresses for a device with DTE[TV]=3D0 are passed through (i.e. not remapped) and instead terminate the page table walk early. Fixes: d29a09ca6842 ("hw/i386: Introduce AMD IOMMU") Signed-off-by: Alejandro Jimenez --- hw/i386/amd_iommu.c | 87 +++++++++++++++++++++++++-------------------- 1 file changed, 48 insertions(+), 39 deletions(-) diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index e916dcb2be381..1bda2a8ac3a16 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -1722,51 +1722,60 @@ static void amdvi_page_walk(AMDVIAddressSpace *as, = uint64_t *dte, uint64_t pte =3D dte[0], pte_addr, page_mask; =20 /* make sure the DTE has TV =3D 1 */ - if (pte & AMDVI_DEV_TRANSLATION_VALID) { - level =3D get_pte_translation_mode(pte); - if (level >=3D 7) { - trace_amdvi_mode_invalid(level, addr); + if (!(pte & AMDVI_DEV_TRANSLATION_VALID)) { + /* + * A DTE with V=3D1, TV=3D0 does not have a valid Page Table Root = Pointer. + * An IOMMU processing a request that requires a table walk termin= ates + * the walk when it encounters this condition. Do the same and ret= urn + * instead of assuming that the address is forwarded without trans= lation + * i.e. the passthrough case, as it is done for the case where DTE= [V]=3D0. + */ + return; + } + + level =3D get_pte_translation_mode(pte); + if (level >=3D 7) { + trace_amdvi_mode_invalid(level, addr); + return; + } + if (level =3D=3D 0) { + goto no_remap; + } + + /* we are at the leaf page table or page table encodes a huge page */ + do { + pte_perms =3D amdvi_get_perms(pte); + present =3D pte & 1; + if (!present || perms !=3D (perms & pte_perms)) { + amdvi_page_fault(as->iommu_state, as->devfn, addr, perms); + trace_amdvi_page_fault(addr); return; } - if (level =3D=3D 0) { - goto no_remap; + /* go to the next lower level */ + pte_addr =3D pte & AMDVI_DEV_PT_ROOT_MASK; + /* add offset and load pte */ + pte_addr +=3D ((addr >> (3 + 9 * level)) & 0x1FF) << 3; + pte =3D amdvi_get_pte_entry(as->iommu_state, pte_addr, as->devfn); + if (!pte) { + return; } + oldlevel =3D level; + level =3D get_pte_translation_mode(pte); + } while (level > 0 && level < 7); =20 - /* we are at the leaf page table or page table encodes a huge page= */ - do { - pte_perms =3D amdvi_get_perms(pte); - present =3D pte & 1; - if (!present || perms !=3D (perms & pte_perms)) { - amdvi_page_fault(as->iommu_state, as->devfn, addr, perms); - trace_amdvi_page_fault(addr); - return; - } - - /* go to the next lower level */ - pte_addr =3D pte & AMDVI_DEV_PT_ROOT_MASK; - /* add offset and load pte */ - pte_addr +=3D ((addr >> (3 + 9 * level)) & 0x1FF) << 3; - pte =3D amdvi_get_pte_entry(as->iommu_state, pte_addr, as->dev= fn); - if (!pte || (pte =3D=3D (uint64_t)-1)) { - return; - } - oldlevel =3D level; - level =3D get_pte_translation_mode(pte); - } while (level > 0 && level < 7); + if (level =3D=3D 0x7) { + page_mask =3D pte_override_page_mask(pte); + } else { + page_mask =3D pte_get_page_mask(oldlevel); + } =20 - if (level =3D=3D 0x7) { - page_mask =3D pte_override_page_mask(pte); - } else { - page_mask =3D pte_get_page_mask(oldlevel); - } + /* get access permissions from pte */ + ret->iova =3D addr & page_mask; + ret->translated_addr =3D (pte & AMDVI_DEV_PT_ROOT_MASK) & page_mask; + ret->addr_mask =3D ~page_mask; + ret->perm =3D amdvi_get_perms(pte); + return; =20 - /* get access permissions from pte */ - ret->iova =3D addr & page_mask; - ret->translated_addr =3D (pte & AMDVI_DEV_PT_ROOT_MASK) & page_mas= k; - ret->addr_mask =3D ~page_mask; - ret->perm =3D amdvi_get_perms(pte); - return; - } no_remap: ret->iova =3D addr & AMDVI_PAGE_MASK_4K; ret->translated_addr =3D addr & AMDVI_PAGE_MASK_4K; --=20 2.43.5 From nobody Sun Sep 28 16:28:07 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oracle.com ARC-Seal: i=1; a=rsa-sha256; t=1758317931; cv=none; d=zohomail.com; s=zohoarc; b=DNuz45LZPUpxQ6TgIu/FPLlC80g8zEUTi51Stl7EE8I6bLo1JBBPB00hv7uqDahtrLzs5BsUNRon4csFufDySAFLQA4dYhqQXYLhCNUIALBU7T5yXn5RWKZgIyJEsVCIEz6sA/nN0gWAI0bhfYmpz3AZygXZKodaQMU953s+8/I= ARC-Message-Signature: i=1; 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b=JLk+pr+yWWWfDGfovcOPk 6n6TjaJ/jtA0ekI5M8qlmJCdcRhkVUshlxkcHv9NgViPV9xxRohZkM/jGVDJtiwb Hp785n6BaD/mIF6et72m8KY27CJci55xLEL3MZbuK8ieWUX8X04HaomZx/azb6JA YKuozFgjpaybAsxUdpYlh0lpAO5VuUpGU2tJUXK4m0iDz0lXb3p4TrXhDqBZbRw4 hG5QTMq2hDNkTXwwPaYyXsCsK15mhNj7JQguPy5j2uKxn9++CJPQEMqJoualKh+b NDb6+rL+x0XyyyzAx3AHsyPROD1TzwHuVLt8h9IUCKZj8Swb67rIGM5jqOi3tvfl Q== From: Alejandro Jimenez To: qemu-devel@nongnu.org Cc: mst@redhat.com, clement.mathieu--drif@eviden.com, pbonzini@redhat.com, richard.henderson@linaro.org, eduardo@habkost.net, peterx@redhat.com, david@redhat.com, philmd@linaro.org, marcel.apfelbaum@gmail.com, alex.williamson@redhat.com, imammedo@redhat.com, anisinha@redhat.com, vasant.hegde@amd.com, suravee.suthikulpanit@amd.com, santosh.shukla@amd.com, sarunkod@amd.com, Wei.Huang2@amd.com, Ankit.Soni@amd.com, ethan.milon@eviden.com, joao.m.martins@oracle.com, boris.ostrovsky@oracle.com, alejandro.j.jimenez@oracle.com Subject: [PATCH v3 20/22] amd_iommu: Refactor amdvi_page_walk() to use common code for page walk Date: Fri, 19 Sep 2025 21:35:13 +0000 Message-ID: <20250919213515.917111-21-alejandro.j.jimenez@oracle.com> X-Mailer: git-send-email 2.43.5 In-Reply-To: <20250919213515.917111-1-alejandro.j.jimenez@oracle.com> References: <20250919213515.917111-1-alejandro.j.jimenez@oracle.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-19_03,2025-09-19_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 phishscore=0 bulkscore=0 adultscore=0 mlxlogscore=999 spamscore=0 mlxscore=0 suspectscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2508110000 definitions=main-2509190201 X-Proofpoint-ORIG-GUID: DrL4KKJbdO6hEI9GFMJ5Wj4rY_Fdq7C3 X-Proofpoint-GUID: DrL4KKJbdO6hEI9GFMJ5Wj4rY_Fdq7C3 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTE2MDIwMiBTYWx0ZWRfX0VnVDMVAuXkB L7CaEBz0aNC+3s9ncoQZRwTu8fOuacAY5hiv8MRUu4pBc8mhCzEMGmT0fJ+ibFa0V990RJmPxll 9KpHmGxCQH6wXHccP9q2wd5M/uCWxftc0ayOujlypiADkXUtP5ddKeQQWKtXtOn3Au7Or1YDkGa 5eN6cvG/pBxksA2JsiT7yqLEvGdxa0ZpUPgG0gGWHZaSEsDYjpDR+qIbDNXa64+kWfoMpd7j1PF JUSWKyrQoC7ynH1rDCZcCpSTTPBUYnFCOB8O0JqzpYzylxzUS+cYeSu1H+5XztdKQhIw9ACwD8P 7Fx50qM2hIQJIzEdGx9pub+Wyz7vtqnbBNjgv5bB5N49GuHFVFxPqdEGsFBuqwUHhc7l5j51qPJ wLmBeqON X-Authority-Analysis: v=2.4 cv=N/QpF39B c=1 sm=1 tr=0 ts=68cdccc8 b=1 cx=c_pps a=WeWmnZmh0fydH62SvGsd2A==:117 a=WeWmnZmh0fydH62SvGsd2A==:17 a=yJojWOMRYYMA:10 a=yPCof4ZbAAAA:8 a=P9DecepiNGKYXCLT5xAA:9 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Simplify amdvi_page_walk() by making it call the fetch_pte() helper that is already in use by the shadow page synchronization code. Ensures all code uses the same page table walking algorithm. Signed-off-by: Alejandro Jimenez --- hw/i386/amd_iommu.c | 77 ++++++++++++++++----------------------------- 1 file changed, 27 insertions(+), 50 deletions(-) diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index 1bda2a8ac3a16..b6851784fb9f1 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -513,24 +513,6 @@ static inline uint8_t get_pte_translation_mode(uint64_= t pte) return (pte >> AMDVI_DEV_MODE_RSHIFT) & AMDVI_DEV_MODE_MASK; } =20 -static inline uint64_t pte_override_page_mask(uint64_t pte) -{ - uint8_t page_mask =3D 13; - uint64_t addr =3D (pte & AMDVI_DEV_PT_ROOT_MASK) >> 12; - /* find the first zero bit */ - while (addr & 1) { - page_mask++; - addr =3D addr >> 1; - } - - return ~((1ULL << page_mask) - 1); -} - -static inline uint64_t pte_get_page_mask(uint64_t oldlevel) -{ - return ~((1UL << ((oldlevel * 9) + 3)) - 1); -} - static inline uint64_t amdvi_get_pte_entry(AMDVIState *s, uint64_t pte_add= r, uint16_t devid) { @@ -1718,11 +1700,13 @@ static void amdvi_page_walk(AMDVIAddressSpace *as, = uint64_t *dte, IOMMUTLBEntry *ret, unsigned perms, hwaddr addr) { - unsigned level, present, pte_perms, oldlevel; - uint64_t pte =3D dte[0], pte_addr, page_mask; + hwaddr page_mask, pagesize =3D 0; + uint8_t mode; + uint64_t pte; + int fetch_ret; =20 /* make sure the DTE has TV =3D 1 */ - if (!(pte & AMDVI_DEV_TRANSLATION_VALID)) { + if (!(dte[0] & AMDVI_DEV_TRANSLATION_VALID)) { /* * A DTE with V=3D1, TV=3D0 does not have a valid Page Table Root = Pointer. * An IOMMU processing a request that requires a table walk termin= ates @@ -1733,42 +1717,35 @@ static void amdvi_page_walk(AMDVIAddressSpace *as, = uint64_t *dte, return; } =20 - level =3D get_pte_translation_mode(pte); - if (level >=3D 7) { - trace_amdvi_mode_invalid(level, addr); + mode =3D get_pte_translation_mode(dte[0]); + if (mode >=3D 7) { + trace_amdvi_mode_invalid(mode, addr); return; } - if (level =3D=3D 0) { + if (mode =3D=3D 0) { goto no_remap; } =20 - /* we are at the leaf page table or page table encodes a huge page */ - do { - pte_perms =3D amdvi_get_perms(pte); - present =3D pte & 1; - if (!present || perms !=3D (perms & pte_perms)) { - amdvi_page_fault(as->iommu_state, as->devfn, addr, perms); - trace_amdvi_page_fault(addr); - return; - } - /* go to the next lower level */ - pte_addr =3D pte & AMDVI_DEV_PT_ROOT_MASK; - /* add offset and load pte */ - pte_addr +=3D ((addr >> (3 + 9 * level)) & 0x1FF) << 3; - pte =3D amdvi_get_pte_entry(as->iommu_state, pte_addr, as->devfn); - if (!pte) { - return; - } - oldlevel =3D level; - level =3D get_pte_translation_mode(pte); - } while (level > 0 && level < 7); + /* Attempt to fetch the PTE to determine if a valid mapping exists */ + fetch_ret =3D fetch_pte(as, addr, dte[0], &pte, &pagesize); =20 - if (level =3D=3D 0x7) { - page_mask =3D pte_override_page_mask(pte); - } else { - page_mask =3D pte_get_page_mask(oldlevel); + /* + * If walking the page table results in an error of any type, returns = an + * empty PTE i.e. no mapping, or the permissions do not match, return = since + * there is no translation available. + */ + if (fetch_ret < 0 || !IOMMU_PTE_PRESENT(pte) || + perms !=3D (perms & amdvi_get_perms(pte))) { + + amdvi_page_fault(as->iommu_state, as->devfn, addr, perms); + trace_amdvi_page_fault(addr); + return; } =20 + /* A valid PTE and page size has been retrieved */ + assert(pagesize); + page_mask =3D ~(pagesize - 1); + /* get access permissions from pte */ ret->iova =3D addr & page_mask; ret->translated_addr =3D (pte & AMDVI_DEV_PT_ROOT_MASK) & page_mask; @@ -1780,7 +1757,7 @@ no_remap: ret->iova =3D addr & AMDVI_PAGE_MASK_4K; ret->translated_addr =3D addr & AMDVI_PAGE_MASK_4K; ret->addr_mask =3D ~AMDVI_PAGE_MASK_4K; - ret->perm =3D amdvi_get_perms(pte); + ret->perm =3D amdvi_get_perms(dte[0]); } =20 static void amdvi_do_translate(AMDVIAddressSpace *as, hwaddr addr, --=20 2.43.5 From nobody Sun Sep 28 16:28:07 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oracle.com ARC-Seal: i=1; a=rsa-sha256; t=1758317827; cv=none; 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charset="utf-8" From: Joao Martins To be later reused by AMD, now that it shares similar property. Signed-off-by: Joao Martins Signed-off-by: Alejandro Jimenez --- hw/i386/intel_iommu.c | 5 ++--- hw/i386/x86-iommu.c | 1 + include/hw/i386/x86-iommu.h | 1 + 3 files changed, 4 insertions(+), 3 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 83c5e444131a3..2b848d094cfb7 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -2701,7 +2701,7 @@ static void vtd_handle_gcmd_write(IntelIOMMUState *s) uint32_t changed =3D status ^ val; =20 trace_vtd_reg_write_gcmd(status, val); - if ((changed & VTD_GCMD_TE) && s->dma_translation) { + if ((changed & VTD_GCMD_TE) && x86_iommu->dma_translation) { /* Translation enable/disable */ vtd_handle_gcmd_te(s, val & VTD_GCMD_TE); } @@ -3835,7 +3835,6 @@ static const Property vtd_properties[] =3D { DEFINE_PROP_BOOL("snoop-control", IntelIOMMUState, snoop_control, fals= e), DEFINE_PROP_BOOL("x-pasid-mode", IntelIOMMUState, pasid, false), DEFINE_PROP_BOOL("dma-drain", IntelIOMMUState, dma_drain, true), - DEFINE_PROP_BOOL("dma-translation", IntelIOMMUState, dma_translation, = true), DEFINE_PROP_BOOL("stale-tm", IntelIOMMUState, stale_tm, false), DEFINE_PROP_BOOL("fs1gp", IntelIOMMUState, fs1gp, true), }; @@ -4553,7 +4552,7 @@ static void vtd_cap_init(IntelIOMMUState *s) if (s->dma_drain) { s->cap |=3D VTD_CAP_DRAIN; } - if (s->dma_translation) { + if (x86_iommu->dma_translation) { if (s->aw_bits >=3D VTD_HOST_AW_39BIT) { s->cap |=3D VTD_CAP_SAGAW_39bit; } diff --git a/hw/i386/x86-iommu.c b/hw/i386/x86-iommu.c index d34a6849f4ae9..c127a44bb4bc8 100644 --- a/hw/i386/x86-iommu.c +++ b/hw/i386/x86-iommu.c @@ -130,6 +130,7 @@ static const Property x86_iommu_properties[] =3D { intr_supported, ON_OFF_AUTO_AUTO), DEFINE_PROP_BOOL("device-iotlb", X86IOMMUState, dt_supported, false), DEFINE_PROP_BOOL("pt", X86IOMMUState, pt_supported, true), + DEFINE_PROP_BOOL("dma-translation", X86IOMMUState, dma_translation, tr= ue), }; =20 static void x86_iommu_class_init(ObjectClass *klass, const void *data) diff --git a/include/hw/i386/x86-iommu.h b/include/hw/i386/x86-iommu.h index bfd21649d0838..e89f55a5c215c 100644 --- a/include/hw/i386/x86-iommu.h +++ b/include/hw/i386/x86-iommu.h @@ -64,6 +64,7 @@ struct X86IOMMUState { OnOffAuto intr_supported; /* Whether vIOMMU supports IR */ bool dt_supported; /* Whether vIOMMU supports DT */ bool pt_supported; /* Whether vIOMMU supports pass-through */ + bool dma_translation; /* Whether vIOMMU supports DMA translation= */ QLIST_HEAD(, IEC_Notifier) iec_notifiers; /* IEC notify list */ }; =20 --=20 2.43.5 From nobody Sun Sep 28 16:28:07 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oracle.com ARC-Seal: i=1; a=rsa-sha256; t=1758317971; cv=none; d=zohomail.com; s=zohoarc; b=kL8tDlas3LEawpQyz1UIfAby4EBWDeqIgdzcXEjIIRVDJzq5fUOpaetAI6Pahjywua1kSI4XgWevPXoDDnNmxlsvXRRnBViJD55pFcydeipu/OtHM0DGkW9llHHlhrGCy5DcshqJY97QU0I+wxQanRpP4FhK3dQhnocTX+ZZfHg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758317971; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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charset="utf-8" From: Joao Martins Add a way to disable DMA translation support in AMD IOMMU by allowing to set IVHD HATDis to 1, and exposing HATS (Host Address Translation Size) as Reserved value. Signed-off-by: Joao Martins Signed-off-by: Alejandro Jimenez --- hw/i386/acpi-build.c | 6 +++++- hw/i386/amd_iommu.c | 19 +++++++++++++++++++ hw/i386/amd_iommu.h | 1 + 3 files changed, 25 insertions(+), 1 deletion(-) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 423c4959fe809..9446a9f862ca4 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -1863,7 +1863,11 @@ build_amd_iommu(GArray *table_data, BIOSLinker *link= er, const char *oem_id, /* IOMMU info */ build_append_int_noprefix(table_data, 0, 2); /* IOMMU Attributes */ - build_append_int_noprefix(table_data, 0, 4); + if (!s->iommu.dma_translation) { + build_append_int_noprefix(table_data, (1UL << 0) /* HATDis */, 4); + } else { + build_append_int_noprefix(table_data, 0, 4); + } /* EFR Register Image */ build_append_int_noprefix(table_data, amdvi_extended_feature_register(s), diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index b6851784fb9f1..378e0cb55eab6 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -107,6 +107,9 @@ uint64_t amdvi_extended_feature_register(AMDVIState *s) if (s->xtsup) { feature |=3D AMDVI_FEATURE_XT; } + if (!s->iommu.dma_translation) { + feature |=3D AMDVI_HATS_MODE_RESERVED; + } =20 return feature; } @@ -472,6 +475,9 @@ static inline uint64_t amdvi_get_perms(uint64_t entry) static bool amdvi_validate_dte(AMDVIState *s, uint16_t devid, uint64_t *dte) { + + uint64_t root; + if ((dte[0] & AMDVI_DTE_QUAD0_RESERVED) || (dte[1] & AMDVI_DTE_QUAD1_RESERVED) || (dte[2] & AMDVI_DTE_QUAD2_RESERVED) || @@ -482,6 +488,19 @@ static bool amdvi_validate_dte(AMDVIState *s, uint16_t= devid, return false; } =20 + /* + * 1 =3D Host Address Translation is not supported. Value in MMIO Offs= et + * 0030h[HATS] is not meaningful. A non-zero host page table root poin= ter + * in the DTE would result in an ILLEGAL_DEV_TABLE_ENTRY event. + */ + root =3D (dte[0] & AMDVI_DEV_PT_ROOT_MASK) >> 12; + if (root && !s->iommu.dma_translation) { + amdvi_log_illegaldevtab_error(s, devid, + s->devtab + + devid * AMDVI_DEVTAB_ENTRY_SIZE, 0); + return false; + } + return true; } =20 diff --git a/hw/i386/amd_iommu.h b/hw/i386/amd_iommu.h index e1354686b6f03..daf82fc85f961 100644 --- a/hw/i386/amd_iommu.h +++ b/hw/i386/amd_iommu.h @@ -177,6 +177,7 @@ /* AMDVI paging mode */ #define AMDVI_GATS_MODE (2ULL << 12) #define AMDVI_HATS_MODE (2ULL << 10) +#define AMDVI_HATS_MODE_RESERVED (3ULL << 10) =20 /* Page Table format */ =20 --=20 2.43.5