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a="60304406" X-IronPort-AV: E=Sophos;i="6.18,277,1751266800"; d="scan'208";a="60304406" X-CSE-ConnectionGUID: x7hH4QgDQ4+sn4D/CIahNw== X-CSE-MsgGUID: rdfd8FlkQ7CSYh9O0TMuFQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.18,277,1751266800"; d="scan'208";a="175584363" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, yi.l.liu@intel.com, clement.mathieu--drif@eviden.com, Zhenzhong Duan Subject: [PATCH 1/2] intel_iommu: Enable Enhanced Set Root Table Pointer Support (ESRTPS) Date: Fri, 19 Sep 2025 03:06:37 -0400 Message-ID: <20250919070638.983549-2-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250919070638.983549-1-zhenzhong.duan@intel.com> References: <20250919070638.983549-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.20; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.005, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1758265696319116600 Content-Type: text/plain; charset="utf-8" According to VTD spec rev 4.1 section 6.6: "For implementations reporting the Enhanced Set Root Table Pointer Support (ESRTPS) field as Clear, on a 'Set Root Table Pointer' operation, software must perform a global invalidate of the context cache, PASID-cache (if applicable), and IOTLB, in that order. This is required to ensure hardware references only the remapping structures referenced by the new root table pointer and not stale cached entries. For implementations reporting the Enhanced Set Root Table Pointer Support (ESRTPS) field as Set, as part of 'Set Root Table Pointer' operation, hardware performs global invalidation on all DMA remapping translation caches and hence software is not required to perform additional invalidations" We already implemented ESRTPS capability in vtd_handle_gcmd_srtp() by calling vtd_reset_caches(), just set ESRTPS in DMAR_CAP_REG to avoid unnecessary global invalidation requests of context, PASID-cache and IOTLB from guest. This change doesn't impact migration as the content of DMAR_CAP_REG is migrated too. Signed-off-by: Zhenzhong Duan Reviewed-by: Cl=C3=A9ment Mathieu--Drif --- hw/i386/intel_iommu_internal.h | 1 + hw/i386/intel_iommu.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index 360e937989..5dd92d388d 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -214,6 +214,7 @@ #define VTD_CAP_DRAIN_WRITE (1ULL << 54) #define VTD_CAP_DRAIN_READ (1ULL << 55) #define VTD_CAP_FS1GP (1ULL << 56) +#define VTD_CAP_ESRTPS (1ULL << 63) #define VTD_CAP_DRAIN (VTD_CAP_DRAIN_READ | VTD_CAP_DRAIN_WR= ITE) #define VTD_CAP_CM (1ULL << 7) #define VTD_PASID_ID_SHIFT 20 diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 83c5e44413..f04300022e 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -4549,7 +4549,7 @@ static void vtd_cap_init(IntelIOMMUState *s) =20 s->cap =3D VTD_CAP_FRO | VTD_CAP_NFR | VTD_CAP_ND | VTD_CAP_MAMV | VTD_CAP_PSI | VTD_CAP_SLLPS | - VTD_CAP_MGAW(s->aw_bits); + VTD_CAP_ESRTPS | VTD_CAP_MGAW(s->aw_bits); if (s->dma_drain) { s->cap |=3D VTD_CAP_DRAIN; } --=20 2.47.1 From nobody Sat Nov 15 00:44:23 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1758265693; cv=none; d=zohomail.com; s=zohoarc; b=LpjoY9CL9hFEIWFTTryz5LfYj3Ys1e7T1rksDKpW8ofs5VI/g8tNtIKbsVmtDHNlVgz6RcIkO2hgQkmy2L/ALGswgQ/ZNSc5gZhbLyBoI4uMPTUlk9NWIWZaP3nJTLryK17zp0Qf/oxMW9OhDwFAksk85mSXcVS7z340Zerg7Pk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758265693; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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X-CSE-ConnectionGUID: UU+ZBo3EQqSwzPN3ukyLVg== X-CSE-MsgGUID: 20qLdBjZQc2ynL7sap6B4A== X-IronPort-AV: E=McAfee;i="6800,10657,11557"; a="60304413" X-IronPort-AV: E=Sophos;i="6.18,277,1751266800"; d="scan'208";a="60304413" X-CSE-ConnectionGUID: Up86aWRsSuOUIPjUQoNP3w== X-CSE-MsgGUID: WQqhTtc2S7aLJTkSqWwJjw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.18,277,1751266800"; d="scan'208";a="175584374" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, yi.l.liu@intel.com, clement.mathieu--drif@eviden.com, Zhenzhong Duan Subject: [PATCH 2/2] intel_iommu: Simplify caching mode check with VFIO device Date: Fri, 19 Sep 2025 03:06:38 -0400 Message-ID: <20250919070638.983549-3-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250919070638.983549-1-zhenzhong.duan@intel.com> References: <20250919070638.983549-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.20; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.005, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1758265696582116600 Content-Type: text/plain; charset="utf-8" In early days, we have different tricks to ensure caching-mode=3Don with VF= IO device: 28cf553afe ("intel_iommu: Sanity check vfio-pci config on machine init done= ") c6cbc29d36 ("pc/q35: Disallow vfio-pci hotplug without VT-d caching mode") b8d78277c0 ("intel-iommu: fail MAP notifier without caching mode") Because without caching mode, MAP notifier won't work correctly since guest won't send IOTLB update event when it establishes new mappings in the I/O p= age tables. Now with host IOMMU device interface between VFIO and vIOMMU, we can simpli= fy it with a small check in set_iommu_device(). This also works for future VDPA implementation which may also need caching mode on. For coldplug VFIO device: qemu-system-x86_64: -device vfio-pci,host=3D0000:3b:00.0,id=3Dhostdev3,bus= =3Droot0,iommufd=3Diommufd0: vfio 0000:3b:00.0: Failed to set vIOMMU: Devic= e assignment is not allowed without enabling caching-mode=3Don for Intel IO= MMU. For hotplug VFIO device: Error: vfio 0000:3b:00.0: Failed to set vIOMMU: Device assignment is not al= lowed without enabling caching-mode=3Don for Intel IOMMU. Signed-off-by: Zhenzhong Duan Acked-by: C=C3=A9dric Le Goater Reviewed-by: Cl=C3=A9ment Mathieu--Drif --- hw/i386/intel_iommu.c | 47 ++++++------------------------------------- hw/i386/pc.c | 20 ------------------ 2 files changed, 6 insertions(+), 61 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index f04300022e..5c67b42dde 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -85,13 +85,6 @@ struct vtd_iotlb_key { static void vtd_address_space_refresh_all(IntelIOMMUState *s); static void vtd_address_space_unmap(VTDAddressSpace *as, IOMMUNotifier *n); =20 -static void vtd_panic_require_caching_mode(void) -{ - error_report("We need to set caching-mode=3Don for intel-iommu to enab= le " - "device assignment with IOMMU protection."); - exit(1); -} - static void vtd_define_quad(IntelIOMMUState *s, hwaddr addr, uint64_t val, uint64_t wmask, uint64_t w1cmask) { @@ -3731,13 +3724,6 @@ static int vtd_iommu_notify_flag_changed(IOMMUMemory= Region *iommu, "Snoop Control with vhost or VFIO is not supporte= d"); return -ENOTSUP; } - if (!s->caching_mode && (new & IOMMU_NOTIFIER_MAP)) { - error_setg_errno(errp, ENOTSUP, - "device %02x.%02x.%x requires caching mode", - pci_bus_num(vtd_as->bus), PCI_SLOT(vtd_as->devfn), - PCI_FUNC(vtd_as->devfn)); - return -ENOTSUP; - } if (!x86_iommu->dt_supported && (new & IOMMU_NOTIFIER_DEVIOTLB_UNMAP))= { error_setg_errno(errp, ENOTSUP, "device %02x.%02x.%x requires device IOTLB mode", @@ -4378,6 +4364,12 @@ static bool vtd_dev_set_iommu_device(PCIBus *bus, vo= id *opaque, int devfn, =20 assert(hiod); =20 + if (!s->caching_mode) { + error_setg(errp, "Device assignment is not allowed without enablin= g " + "caching-mode=3Don for Intel IOMMU."); + return false; + } + vtd_iommu_lock(s); =20 if (g_hash_table_lookup(s->vtd_host_iommu_dev, &key)) { @@ -4910,32 +4902,6 @@ static bool vtd_decide_config(IntelIOMMUState *s, Er= ror **errp) return true; } =20 -static int vtd_machine_done_notify_one(Object *child, void *unused) -{ - IntelIOMMUState *iommu =3D INTEL_IOMMU_DEVICE(x86_iommu_get_default()); - - /* - * We hard-coded here because vfio-pci is the only special case - * here. Let's be more elegant in the future when we can, but so - * far there seems to be no better way. - */ - if (object_dynamic_cast(child, "vfio-pci") && !iommu->caching_mode) { - vtd_panic_require_caching_mode(); - } - - return 0; -} - -static void vtd_machine_done_hook(Notifier *notifier, void *unused) -{ - object_child_foreach_recursive(object_get_root(), - vtd_machine_done_notify_one, NULL); -} - -static Notifier vtd_machine_done_notify =3D { - .notify =3D vtd_machine_done_hook, -}; - static void vtd_realize(DeviceState *dev, Error **errp) { MachineState *ms =3D MACHINE(qdev_get_machine()); @@ -4990,7 +4956,6 @@ static void vtd_realize(DeviceState *dev, Error **err= p) pci_setup_iommu(bus, &vtd_iommu_ops, dev); /* Pseudo address space under root PCI bus. */ x86ms->ioapic_as =3D vtd_host_dma_iommu(bus, s, Q35_PSEUDO_DEVFN_IOAPI= C); - qemu_add_machine_init_done_notifier(&vtd_machine_done_notify); } =20 static void vtd_class_init(ObjectClass *klass, const void *data) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index bc048a6d13..01cd9a67db 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1720,25 +1720,6 @@ static void pc_machine_wakeup(MachineState *machine) cpu_synchronize_all_post_reset(); } =20 -static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error *= *errp) -{ - X86IOMMUState *iommu =3D x86_iommu_get_default(); - IntelIOMMUState *intel_iommu; - - if (iommu && - object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) && - object_dynamic_cast((Object *)dev, "vfio-pci")) { - intel_iommu =3D INTEL_IOMMU_DEVICE(iommu); - if (!intel_iommu->caching_mode) { - error_setg(errp, "Device assignment is not allowed without " - "enabling caching-mode=3Don for Intel IOMMU."); - return false; - } - } - - return true; -} - static void pc_machine_class_init(ObjectClass *oc, const void *data) { MachineClass *mc =3D MACHINE_CLASS(oc); @@ -1758,7 +1739,6 @@ static void pc_machine_class_init(ObjectClass *oc, co= nst void *data) x86mc->apic_xrupt_override =3D true; assert(!mc->get_hotplug_handler); mc->get_hotplug_handler =3D pc_get_hotplug_handler; - mc->hotplug_allowed =3D pc_hotplug_allowed; mc->auto_enable_numa_with_memhp =3D true; mc->auto_enable_numa_with_memdev =3D true; mc->has_hotpluggable_cpus =3D true; --=20 2.47.1